OV - exec - Loop 2953

	Loop Id: 2953	Module: exec	Source: csr_matvec.c:166-167	Coverage: 0.04%

0x547a56 VMOVSD	(%R14,%RAX,8),%XMM0    [1]

0x547a5c LEA	0x1(%RAX),%RDI

0x547a60 VMOVSD	%XMM0,(%R15,%RAX,8)    [2]

0x547a66 VMOVSD	(%R14,%RDI,8),%XMM4    [1]

0x547a6c LEA	0x2(%RAX),%RDX

0x547a70 VMOVSD	%XMM4,(%R15,%RDI,8)    [2]

0x547a76 VMOVSD	(%R14,%RDX,8),%XMM3    [1]

0x547a7c LEA	0x3(%RAX),%R10

0x547a80 VMOVSD	%XMM3,(%R15,%RDX,8)    [2]

0x547a86 VMOVSD	(%R14,%R10,8),%XMM5    [1]

0x547a8c LEA	0x4(%RAX),%R11

0x547a90 VMOVSD	%XMM5,(%R15,%R10,8)    [2]

0x547a96 VMOVSD	(%R14,%R11,8),%XMM1    [1]

0x547a9c LEA	0x5(%RAX),%R9

0x547aa0 VMOVSD	%XMM1,(%R15,%R11,8)    [2]

0x547aa6 VMOVSD	(%R14,%R9,8),%XMM6    [1]

0x547aac LEA	0x6(%RAX),%RCX

0x547ab0 VMOVSD	%XMM6,(%R15,%R9,8)    [2]

0x547ab6 VMOVSD	(%R14,%RCX,8),%XMM8    [1]

0x547abc LEA	0x7(%RAX),%RSI

0x547ac0 VMOVSD	%XMM8,(%R15,%RCX,8)    [2]

0x547ac6 VMOVSD	(%R14,%RSI,8),%XMM9    [1]

0x547acc ADD	$0x8,%RAX

0x547ad0 VMOVSD	%XMM9,(%R15,%RSI,8)    [2]

0x547ad6 CMP	%RAX,%RBX

0x547ad9 JNE	547a56

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 166 - 167

--------------------------------------------------------------------------------

166:             for (i = 0; i < num_rows*num_vectors; i++)

167:                y_data[i] = b_data[i];

Coverage (%)	Name	Source Location	Module
►96.90+	hypre_ParCSRMatrixMatvecOutOfP[...]	par_csr_matvec.c:232	exec
○	hypre_PCGSolve	pcg.c:496	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
►3.10+	hypre_ParCSRMatrixMatvecOutOfP[...]	par_csr_matvec.c:232	exec
○	hypre_PCGSolve	pcg.c:496	exec
○	main	amg.c:419	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.04
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecOutOfPlace
Source	csr_matvec.c:166-167
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.17
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.17
CQA cycles if fully vectorized	0.52
Front-end cycles	4.17
P0 cycles	0.50
P1 cycles	0.00
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	4.00
P5 cycles	0.00
P6 cycles	0.50
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.00
P11 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	25.00
Nb loads	8.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.72
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.04
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecOutOfPlace
Source	csr_matvec.c:166-167
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.17
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.17
CQA cycles if fully vectorized	0.52
Front-end cycles	4.17
P0 cycles	0.50
P1 cycles	0.00
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	4.00
P5 cycles	0.00
P6 cycles	0.50
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.00
P11 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	25.00
Nb loads	8.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.72
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMatvecOutOfPlace
Source file and lines	csr_matvec.c:166-167
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:166-167.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.17 to 0.52 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	26
nb uops	25
loop length	137
used x86 registers	11
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.17 cycles
front end	4.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	0.50	0.00	2.67	2.67	4.00	0.00	0.50	4.00	4.00	4.00	0.00	2.67
cycles	0.50	0.00	2.67	2.67	4.00	0.00	0.50	4.00	4.00	4.00	0.00	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.17
Dispatch	4.00
Data deps.	1.00
Overall L1	4.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.17 cycles. At this rate:

8% of peak load performance is reached (15.36 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (15.36 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 547a56

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVSD (%R14,%RAX,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RAX),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM0,(%R15,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R14,%RDI,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x2(%RAX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM4,(%R15,%RDI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R14,%RDX,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x3(%RAX),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM3,(%R15,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R14,%R10,8),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x4(%RAX),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM5,(%R15,%R10,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R14,%R11,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x5(%RAX),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM1,(%R15,%R11,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R14,%R9,8),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x6(%RAX),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM6,(%R15,%R9,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R14,%RCX,8),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x7(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM8,(%R15,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R14,%RSI,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM9,(%R15,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RAX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 547a56 <hypre_CSRMatrixMatvecOutOfPlace+0x316>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	hypre_CSRMatrixMatvecOutOfPlace
Source file and lines	csr_matvec.c:166-167
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:166-167.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.17 to 0.52 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 64 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	26
nb uops	25
loop length	137
used x86 registers	11
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.17 cycles
front end	4.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	0.50	0.00	2.67	2.67	4.00	0.00	0.50	4.00	4.00	4.00	0.00	2.67
cycles	0.50	0.00	2.67	2.67	4.00	0.00	0.50	4.00	4.00	4.00	0.00	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.17
Dispatch	4.00
Data deps.	1.00
Overall L1	4.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.17 cycles. At this rate:

8% of peak load performance is reached (15.36 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (15.36 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 547a56

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVSD (%R14,%RAX,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x1(%RAX),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM0,(%R15,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R14,%RDI,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x2(%RAX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM4,(%R15,%RDI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R14,%RDX,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x3(%RAX),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM3,(%R15,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R14,%R10,8),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x4(%RAX),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM5,(%R15,%R10,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R14,%R11,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x5(%RAX),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM1,(%R15,%R11,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R14,%R9,8),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x6(%RAX),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM6,(%R15,%R9,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R14,%RCX,8),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x7(%RAX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM8,(%R15,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R14,%RSI,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM9,(%R15,%RSI,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RAX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 547a56 <hypre_CSRMatrixMatvecOutOfPlace+0x316>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code