OV - exec - Loop 2928

	Loop Id: 2928	Module: exec	Source: csr_matvec.c:334-341	Coverage: 1.80%

0x545a18 MOV	(%R10,%R14,8),%R11

0x545a1c MOV	0x8(%R10,%R14,8),%RAX

0x545a21 VMOVSD	(%RDI,%R14,8),%XMM8

0x545a27 CMP	%RAX,%R11

0x545a2a JGE	545bad

0x545a30 MOV	%RAX,%RCX

0x545a33 SUB	%R11,%RCX

0x545a36 AND	$0x7,%ECX

0x545a39 JE	545afc

0x545a3f CMP	$0x1,%RCX

0x545a43 JE	545adf

0x545a49 CMP	$0x2,%RCX

0x545a4d JE	545acb

0x545a4f CMP	$0x3,%RCX

0x545a53 JE	545ab7

0x545a55 CMP	$0x4,%RCX

0x545a59 JE	545aa3

0x545a5b CMP	$0x5,%RCX

0x545a5f JE	545a8f

0x545a61 CMP	$0x6,%RCX

0x545a65 JE	545a7b

0x545a67 MOV	(%R12,%R11,8),%R8

0x545a6b VMOVSD	(%R13,%R11,8),%XMM0

0x545a72 INC	%R11

0x545a75 VFMADD231SD	(%RBX,%R8,8),%XMM0,%XMM8

0x545a7b MOV	(%R12,%R11,8),%RDX

0x545a7f VMOVSD	(%R13,%R11,8),%XMM3

0x545a86 INC	%R11

0x545a89 VFMADD231SD	(%RBX,%RDX,8),%XMM3,%XMM8

0x545a8f MOV	(%R12,%R11,8),%RSI

0x545a93 VMOVSD	(%R13,%R11,8),%XMM2

0x545a9a INC	%R11

0x545a9d VFMADD231SD	(%RBX,%RSI,8),%XMM2,%XMM8

0x545aa3 MOV	(%R12,%R11,8),%RCX

0x545aa7 VMOVSD	(%R13,%R11,8),%XMM4

0x545aae INC	%R11

0x545ab1 VFMADD231SD	(%RBX,%RCX,8),%XMM4,%XMM8

0x545ab7 MOV	(%R12,%R11,8),%R8

0x545abb VMOVSD	(%R13,%R11,8),%XMM5

0x545ac2 INC	%R11

0x545ac5 VFMADD231SD	(%RBX,%R8,8),%XMM5,%XMM8

0x545acb MOV	(%R12,%R11,8),%RDX

0x545acf VMOVSD	(%R13,%R11,8),%XMM6

0x545ad6 INC	%R11

0x545ad9 VFMADD231SD	(%RBX,%RDX,8),%XMM6,%XMM8

0x545adf MOV	(%R12,%R11,8),%RSI

0x545ae3 VMOVSD	(%R13,%R11,8),%XMM10

0x545aea INC	%R11

0x545aed VFMADD231SD	(%RBX,%RSI,8),%XMM10,%XMM8

0x545af3 CMP	%RAX,%R11

0x545af6 JE	545bad

  (2929) 0x545afc MOV	(%R12,%R11,8),%RCX

  (2929) 0x545b00 VMOVSD	(%R13,%R11,8),%XMM11

  (2929) 0x545b07 LEA	0x1(%R11),%R8

  (2929) 0x545b0b VFMADD231SD	(%RBX,%RCX,8),%XMM11,%XMM8

  (2929) 0x545b11 MOV	(%R12,%R8,8),%RDX

  (2929) 0x545b15 VMOVSD	(%R13,%R8,8),%XMM13

  (2929) 0x545b1c LEA	0x2(%R11),%RCX

  (2929) 0x545b20 MOV	(%R12,%RCX,8),%RSI

  (2929) 0x545b24 VFMADD231SD	(%RBX,%RDX,8),%XMM13,%XMM8

  (2929) 0x545b2a VMOVSD	(%R13,%RCX,8),%XMM14

  (2929) 0x545b31 LEA	0x3(%R11),%R8

  (2929) 0x545b35 MOV	(%R12,%R8,8),%RDX

  (2929) 0x545b39 VMOVSD	(%R13,%R8,8),%XMM12

  (2929) 0x545b40 VFMADD231SD	(%RBX,%RSI,8),%XMM14,%XMM8

  (2929) 0x545b46 LEA	0x4(%R11),%RCX

  (2929) 0x545b4a MOV	(%R12,%RCX,8),%RSI

  (2929) 0x545b4e VMOVSD	(%R13,%RCX,8),%XMM15

  (2929) 0x545b55 LEA	0x5(%R11),%R8

  (2929) 0x545b59 VFMADD231SD	(%RBX,%RDX,8),%XMM12,%XMM8

  (2929) 0x545b5f VMOVSD	(%R13,%R8,8),%XMM9

  (2929) 0x545b66 MOV	(%R12,%R8,8),%RDX

  (2929) 0x545b6a LEA	0x6(%R11),%RCX

  (2929) 0x545b6e VMOVSD	(%R13,%RCX,8),%XMM1

  (2929) 0x545b75 VFMADD231SD	(%RBX,%RSI,8),%XMM15,%XMM8

  (2929) 0x545b7b MOV	(%R12,%RCX,8),%RSI

  (2929) 0x545b7f LEA	0x7(%R11),%R8

  (2929) 0x545b83 VMOVSD	(%R13,%R8,8),%XMM7

  (2929) 0x545b8a ADD	$0x8,%R11

  (2929) 0x545b8e VFMADD231SD	(%RBX,%RDX,8),%XMM9,%XMM8

  (2929) 0x545b94 MOV	(%R12,%R8,8),%RDX

  (2929) 0x545b98 VFMADD231SD	(%RBX,%RSI,8),%XMM1,%XMM8

  (2929) 0x545b9e VFMADD231SD	(%RBX,%RDX,8),%XMM7,%XMM8

  (2929) 0x545ba4 CMP	%RAX,%R11

  (2929) 0x545ba7 JNE	545afc

0x545bad VMOVSD	%XMM8,(%R15,%R14,8)

0x545bb3 INC	%R14

0x545bb6 CMP	%R14,%R9

0x545bb9 JNE	545a18

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 334 - 341

--------------------------------------------------------------------------------

334:             for (i = iBegin; i < iEnd; i++)

335:             {

336:                tempx = b_data[i];

337:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

338:                {

339:                   tempx += A_data[jj] * x_data[A_j[jj]];

340:                }

341:                y_data[i] = tempx;

Coverage (%)	Name	Source Location	Module
○97.57	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.43	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.69
CQA speedup if FP arith vectorized	1.79
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.27
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source	csr_matvec.c:334-341
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.17
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	5.67
CQA cycles if fully vectorized	1.27
Front-end cycles	10.17
P0 cycles	6.00
P1 cycles	5.50
P2 cycles	8.00
P3 cycles	8.00
P4 cycles	0.50
P5 cycles	5.00
P6 cycles	5.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	5.00
P11 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	54.00
Nb loads	24.00
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.38
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	7.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.67
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.69
CQA speedup if FP arith vectorized	1.79
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.27
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source	csr_matvec.c:334-341
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.17
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	5.67
CQA cycles if fully vectorized	1.27
Front-end cycles	10.17
P0 cycles	6.00
P1 cycles	5.50
P2 cycles	8.00
P3 cycles	8.00
P4 cycles	0.50
P5 cycles	5.00
P6 cycles	5.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	5.00
P11 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	54.00
Nb loads	24.00
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.38
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	7.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.67
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source file and lines	csr_matvec.c:334-341
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:334-341.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 16 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.17 to 6.00 cycles (1.69x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 10.17 to 1.27 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 7 FMA (fused multiply-add) operations.

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

7: addition or subtraction (all inside FMA instructions)
7: multiply (all inside FMA instructions)

The binary loop is loading 192 bytes (24 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	55
nb uops	54
loop length	246
used x86 registers	14
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.17 cycles
front end	10.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.00	5.50	8.00	8.00	0.50	5.00	5.50	0.50	0.50	0.50	5.00	8.00
cycles	6.00	5.50	8.00	8.00	0.50	5.00	5.50	0.50	0.50	0.50	5.00	8.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.17
Dispatch	8.00
Overall L1	10.17

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.17 cycles. At this rate:

9% of peak load performance is reached (18.89 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.79 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.17 to 8.00 cycles (1.27x speedup).

ASM code

In the binary file, the address of the loop is: 545a18

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%R10,%R14,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R10,%R14,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RDI,%R14,8),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %RAX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 545bad <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x13fd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R11,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 545afc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x134c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 545adf <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x132f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 545acb <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x131b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 545ab7 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1307>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 545aa3 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x12f3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 545a8f <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x12df>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 545a7b <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x12cb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R12,%R11,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%R11,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%R8,8),%XMM0,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%R11,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%R11,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%RDX,8),%XMM3,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%R11,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%R11,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%RSI,8),%XMM2,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%R11,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%R11,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%RCX,8),%XMM4,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%R11,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%R11,8),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%R8,8),%XMM5,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%R11,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%R11,8),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%RDX,8),%XMM6,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%R11,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%R11,8),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%RSI,8),%XMM10,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
CMP %RAX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 545bad <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x13fd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD %XMM8,(%R15,%R14,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R14,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 545a18 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1268>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source file and lines	csr_matvec.c:334-341
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:334-341.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.17 to 6.00 cycles (1.69x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 10.17 to 1.27 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 7 FMA (fused multiply-add) operations.

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

7: addition or subtraction (all inside FMA instructions)
7: multiply (all inside FMA instructions)

The binary loop is loading 192 bytes (24 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	55
nb uops	54
loop length	246
used x86 registers	14
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.17 cycles
front end	10.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.00	5.50	8.00	8.00	0.50	5.00	5.50	0.50	0.50	0.50	5.00	8.00
cycles	6.00	5.50	8.00	8.00	0.50	5.00	5.50	0.50	0.50	0.50	5.00	8.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.17
Dispatch	8.00
Overall L1	10.17

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.17 cycles. At this rate:

9% of peak load performance is reached (18.89 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.79 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 545a18

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%R10,%R14,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R10,%R14,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RDI,%R14,8),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %RAX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 545bad <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x13fd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R11,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 545afc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x134c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 545adf <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x132f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 545acb <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x131b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 545ab7 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1307>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 545aa3 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x12f3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 545a8f <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x12df>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 545a7b <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x12cb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R12,%R11,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%R11,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%R8,8),%XMM0,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%R11,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%R11,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%RDX,8),%XMM3,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%R11,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%R11,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%RSI,8),%XMM2,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%R11,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%R11,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%RCX,8),%XMM4,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%R11,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%R11,8),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%R8,8),%XMM5,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%R11,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%R11,8),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%RDX,8),%XMM6,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%R11,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%R11,8),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%RSI,8),%XMM10,%XMM8	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
CMP %RAX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 545bad <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x13fd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD %XMM8,(%R15,%R14,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R14,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 545a18 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1268>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code