OV - exec - Loop 2920

	Loop Id: 2920	Module: exec	Source: csr_matvec.c:256-263	Coverage: 1.03%

0x544a90 MOV	(%R10,%R14,8),%RDI

0x544a94 MOV	0x8(%R10,%R14,8),%R11

0x544a99 VMOVAPD	%XMM8,%XMM11

0x544a9e CMP	%R11,%RDI

0x544aa1 JGE	544c24

0x544aa7 MOV	%R11,%RDX

0x544aaa SUB	%RDI,%RDX

0x544aad AND	$0x7,%EDX

0x544ab0 JE	544b73

0x544ab6 CMP	$0x1,%RDX

0x544aba JE	544b56

0x544ac0 CMP	$0x2,%RDX

0x544ac4 JE	544b42

0x544ac6 CMP	$0x3,%RDX

0x544aca JE	544b2e

0x544acc CMP	$0x4,%RDX

0x544ad0 JE	544b1a

0x544ad2 CMP	$0x5,%RDX

0x544ad6 JE	544b06

0x544ad8 CMP	$0x6,%RDX

0x544adc JE	544af2

0x544ade MOV	(%R12,%RDI,8),%RCX

0x544ae2 VMOVSD	(%R13,%RDI,8),%XMM11

0x544ae9 INC	%RDI

0x544aec VFMADD132SD	(%RBX,%RCX,8),%XMM8,%XMM11

0x544af2 MOV	(%R12,%RDI,8),%RAX

0x544af6 VMOVSD	(%R13,%RDI,8),%XMM14

0x544afd INC	%RDI

0x544b00 VFMADD231SD	(%RBX,%RAX,8),%XMM14,%XMM11

0x544b06 MOV	(%R12,%RDI,8),%R8

0x544b0a VMOVSD	(%R13,%RDI,8),%XMM12

0x544b11 INC	%RDI

0x544b14 VFMADD231SD	(%RBX,%R8,8),%XMM12,%XMM11

0x544b1a MOV	(%R12,%RDI,8),%RSI

0x544b1e VMOVSD	(%R13,%RDI,8),%XMM15

0x544b25 INC	%RDI

0x544b28 VFMADD231SD	(%RBX,%RSI,8),%XMM15,%XMM11

0x544b2e MOV	(%R12,%RDI,8),%RDX

0x544b32 VMOVSD	(%R13,%RDI,8),%XMM9

0x544b39 INC	%RDI

0x544b3c VFMADD231SD	(%RBX,%RDX,8),%XMM9,%XMM11

0x544b42 MOV	(%R12,%RDI,8),%RCX

0x544b46 VMOVSD	(%R13,%RDI,8),%XMM1

0x544b4d INC	%RDI

0x544b50 VFMADD231SD	(%RBX,%RCX,8),%XMM1,%XMM11

0x544b56 MOV	(%R12,%RDI,8),%RAX

0x544b5a VMOVSD	(%R13,%RDI,8),%XMM7

0x544b61 INC	%RDI

0x544b64 VFMADD231SD	(%RBX,%RAX,8),%XMM7,%XMM11

0x544b6a CMP	%R11,%RDI

0x544b6d JE	544c24

  (2921) 0x544b73 MOV	(%R12,%RDI,8),%R8

  (2921) 0x544b77 VMOVSD	(%R13,%RDI,8),%XMM0

  (2921) 0x544b7e LEA	0x1(%RDI),%RDX

  (2921) 0x544b82 VFMADD231SD	(%RBX,%R8,8),%XMM0,%XMM11

  (2921) 0x544b88 MOV	(%R12,%RDX,8),%RSI

  (2921) 0x544b8c VMOVSD	(%R13,%RDX,8),%XMM3

  (2921) 0x544b93 LEA	0x2(%RDI),%RCX

  (2921) 0x544b97 MOV	(%R12,%RCX,8),%RAX

  (2921) 0x544b9b VFMADD231SD	(%RBX,%RSI,8),%XMM3,%XMM11

  (2921) 0x544ba1 VMOVSD	(%R13,%RCX,8),%XMM4

  (2921) 0x544ba8 LEA	0x3(%RDI),%R8

  (2921) 0x544bac MOV	(%R12,%R8,8),%RDX

  (2921) 0x544bb0 VMOVSD	(%R13,%R8,8),%XMM10

  (2921) 0x544bb7 VFMADD231SD	(%RBX,%RAX,8),%XMM4,%XMM11

  (2921) 0x544bbd LEA	0x4(%RDI),%RCX

  (2921) 0x544bc1 MOV	(%R12,%RCX,8),%RSI

  (2921) 0x544bc5 VMOVSD	(%R13,%RCX,8),%XMM2

  (2921) 0x544bcc LEA	0x5(%RDI),%RAX

  (2921) 0x544bd0 VFMADD231SD	(%RBX,%RDX,8),%XMM10,%XMM11

  (2921) 0x544bd6 MOV	(%R12,%RAX,8),%R8

  (2921) 0x544bda VMOVSD	(%R13,%RAX,8),%XMM5

  (2921) 0x544be1 LEA	0x6(%RDI),%RDX

  (2921) 0x544be5 MOV	(%R12,%RDX,8),%RCX

  (2921) 0x544be9 VFMADD231SD	(%RBX,%RSI,8),%XMM2,%XMM11

  (2921) 0x544bef VMOVSD	(%R13,%RDX,8),%XMM6

  (2921) 0x544bf6 LEA	0x7(%RDI),%RAX

  (2921) 0x544bfa MOV	(%R12,%RAX,8),%RSI

  (2921) 0x544bfe VMOVSD	(%R13,%RAX,8),%XMM13

  (2921) 0x544c05 VFMADD231SD	(%RBX,%R8,8),%XMM5,%XMM11

  (2921) 0x544c0b ADD	$0x8,%RDI

  (2921) 0x544c0f VFMADD231SD	(%RBX,%RCX,8),%XMM6,%XMM11

  (2921) 0x544c15 VFMADD231SD	(%RBX,%RSI,8),%XMM13,%XMM11

  (2921) 0x544c1b CMP	%R11,%RDI

  (2921) 0x544c1e JNE	544b73

0x544c24 VMOVSD	%XMM11,(%R15,%R14,8)

0x544c2a INC	%R14

0x544c2d CMP	%R14,%R9

0x544c30 JNE	544a90

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 256 - 263

--------------------------------------------------------------------------------

256:             for (i = iBegin; i < iEnd; i++)

257:             {

258:                tempx = 0.0;

259:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

260:                {

261:                   tempx += A_data[jj] * x_data[A_j[jj]];

262:                }

263:                y_data[i] = tempx;

Coverage (%)	Name	Source Location	Module
○97.68	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.32	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.69
CQA speedup if FP arith vectorized	1.91
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source	csr_matvec.c:256-263
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.17
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	5.33
CQA cycles if fully vectorized	1.27
Front-end cycles	10.17
P0 cycles	6.00
P1 cycles	5.50
P2 cycles	7.67
P3 cycles	7.67
P4 cycles	0.50
P5 cycles	5.00
P6 cycles	5.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	5.00
P11 cycles	7.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	54.00
Nb loads	23.00
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.38
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	7.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.89
Bytes prefetched	0.00
Bytes loaded	184.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	4.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	11.11
Vector-efficiency ratio all	13.00
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.89

Metric	Value
CQA speedup if no scalar integer	1.69
CQA speedup if FP arith vectorized	1.91
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source	csr_matvec.c:256-263
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.17
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	5.33
CQA cycles if fully vectorized	1.27
Front-end cycles	10.17
P0 cycles	6.00
P1 cycles	5.50
P2 cycles	7.67
P3 cycles	7.67
P4 cycles	0.50
P5 cycles	5.00
P6 cycles	5.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	5.00
P11 cycles	7.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	54.00
Nb loads	23.00
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.38
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	7.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.89
Bytes prefetched	0.00
Bytes loaded	184.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	4.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	11.11
Vector-efficiency ratio all	13.00
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.89

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source file and lines	csr_matvec.c:256-263
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:256-263.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 16 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.17 to 6.00 cycles (1.69x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 10.17 to 1.27 cycles (8.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 7 FMA (fused multiply-add) operations.

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

7: addition or subtraction (all inside FMA instructions)
7: multiply (all inside FMA instructions)

The binary loop is loading 184 bytes (23 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	55
nb uops	54
loop length	245
used x86 registers	14
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.17 cycles
front end	10.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.00	5.50	7.67	7.67	0.50	5.00	5.50	0.50	0.50	0.50	5.00	7.67
cycles	6.00	5.50	7.67	7.67	0.50	5.00	5.50	0.50	0.50	0.50	5.00	7.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.17
Dispatch	7.67
Overall L1	10.17

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.17 cycles. At this rate:

9% of peak load performance is reached (18.10 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.79 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.17 to 7.67 cycles (1.33x speedup).

ASM code

In the binary file, the address of the loop is: 544a90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%R10,%R14,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R10,%R14,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVAPD %XMM8,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
CMP %R11,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544c24 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x474>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R11,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 544b73 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x3c3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544b56 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x3a6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544b42 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x392>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544b2e <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x37e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544b1a <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x36a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544b06 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x356>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544af2 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x342>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R12,%RDI,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%RDI,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD132SD (%RBX,%RCX,8),%XMM8,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%RDI,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%RDI,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%RAX,8),%XMM14,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%RDI,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%RDI,8),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%R8,8),%XMM12,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%RDI,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%RDI,8),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%RSI,8),%XMM15,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%RDI,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%RDI,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%RDX,8),%XMM9,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%RDI,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%RDI,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%RCX,8),%XMM1,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%RDI,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%RDI,8),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%RAX,8),%XMM7,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
CMP %R11,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544c24 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x474>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD %XMM11,(%R15,%R14,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R14,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 544a90 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6
Source file and lines	csr_matvec.c:256-263
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:256-263.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.17 to 6.00 cycles (1.69x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 7 FMA (fused multiply-add) operations.

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

7: addition or subtraction (all inside FMA instructions)
7: multiply (all inside FMA instructions)

The binary loop is loading 184 bytes (23 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	55
nb uops	54
loop length	245
used x86 registers	14
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.17 cycles
front end	10.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.00	5.50	7.67	7.67	0.50	5.00	5.50	0.50	0.50	0.50	5.00	7.67
cycles	6.00	5.50	7.67	7.67	0.50	5.00	5.50	0.50	0.50	0.50	5.00	7.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.17
Dispatch	7.67
Overall L1	10.17

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.17 cycles. At this rate:

9% of peak load performance is reached (18.10 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.79 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 544a90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%R10,%R14,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R10,%R14,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVAPD %XMM8,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
CMP %R11,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544c24 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x474>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R11,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 544b73 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x3c3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544b56 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x3a6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544b42 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x392>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544b2e <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x37e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544b1a <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x36a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544b06 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x356>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544af2 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x342>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R12,%RDI,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%RDI,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD132SD (%RBX,%RCX,8),%XMM8,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%RDI,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%RDI,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%RAX,8),%XMM14,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%RDI,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%RDI,8),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%R8,8),%XMM12,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%RDI,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%RDI,8),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%RSI,8),%XMM15,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%RDI,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%RDI,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%RDX,8),%XMM9,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%RDI,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%RDI,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%RCX,8),%XMM1,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R12,%RDI,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R13,%RDI,8),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RBX,%RAX,8),%XMM7,%XMM11	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
CMP %R11,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544c24 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x474>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD %XMM11,(%R15,%R14,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R14,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 544a90 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code