OV - exec - Loop 2904

	Loop Id: 2904	Module: exec	Source: csr_matvec.c:194-195	Coverage: 0.04%

0x543fee MOV	(%RCX,%R9,8),%R12    [2]

0x543ff2 LEA	0x1(%R9),%RDI

0x543ff6 VMOVSD	(%RDX,%R12,8),%XMM11    [3]

0x543ffc MOV	(%RCX,%RDI,8),%RBX    [2]

0x544000 VFMADD231SD	(%RSI,%R9,8),%XMM11,%XMM10    [1]

0x544006 VMOVSD	(%RDX,%RBX,8),%XMM12    [3]

0x54400b LEA	0x2(%R9),%RAX

0x54400f MOV	(%RCX,%RAX,8),%R12    [2]

0x544013 VFMADD231SD	(%RSI,%RDI,8),%XMM12,%XMM10    [1]

0x544019 VMOVSD	(%RDX,%R12,8),%XMM13    [3]

0x54401f LEA	0x3(%R9),%RDI

0x544023 MOV	(%RCX,%RDI,8),%RBX    [2]

0x544027 VFMADD231SD	(%RSI,%RAX,8),%XMM13,%XMM10    [1]

0x54402d VMOVSD	(%RDX,%RBX,8),%XMM14    [3]

0x544032 LEA	0x4(%R9),%RAX

0x544036 MOV	(%RCX,%RAX,8),%R12    [2]

0x54403a VFMADD231SD	(%RSI,%RDI,8),%XMM14,%XMM10    [1]

0x544040 VMOVSD	(%RDX,%R12,8),%XMM15    [3]

0x544046 LEA	0x5(%R9),%RDI

0x54404a MOV	(%RCX,%RDI,8),%RBX    [2]

0x54404e VFMADD231SD	(%RSI,%RAX,8),%XMM15,%XMM10    [1]

0x544054 VMOVSD	(%RDX,%RBX,8),%XMM0    [3]

0x544059 LEA	0x6(%R9),%RAX

0x54405d MOV	(%RCX,%RAX,8),%R12    [2]

0x544061 VFMADD231SD	(%RSI,%RDI,8),%XMM0,%XMM10    [1]

0x544067 VMOVSD	(%RDX,%R12,8),%XMM8    [3]

0x54406d LEA	0x7(%R9),%RDI

0x544071 MOV	(%RCX,%RDI,8),%RBX    [2]

0x544075 ADD	$0x8,%R9

0x544079 VFMADD231SD	(%RSI,%RAX,8),%XMM8,%XMM10    [1]

0x54407f VMOVSD	(%RDX,%RBX,8),%XMM9    [3]

0x544084 VFMADD231SD	(%RSI,%RDI,8),%XMM9,%XMM10    [1]

0x54408a CMP	%R11,%R9

0x54408d JNE	543fee

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 194 - 195

--------------------------------------------------------------------------------

194:                for (jj = A_i[m]; jj < A_i[m+1]; jj++)

195:                   tempx +=  A_data[jj] * x_data[A_j[jj]];

Coverage (%)	Name	Source Location	Module
○98.25	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.75	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.31
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	4.00
Bottlenecks
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3
Source	csr_matvec.c:194-195
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.00
CQA cycles if no scalar integer	32.00
CQA cycles if FP arith vectorized	13.88
CQA cycles if fully vectorized	4.00
Front-end cycles	6.83
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	8.00
P3 cycles	8.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	32
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	34.00
Nb uops	33.00
Nb loads	24.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.50
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.00
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.31
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	4.00
Bottlenecks
Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3
Source	csr_matvec.c:194-195
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.00
CQA cycles if no scalar integer	32.00
CQA cycles if FP arith vectorized	13.88
CQA cycles if fully vectorized	4.00
Front-end cycles	6.83
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	8.00
P3 cycles	8.00
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	32
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	34.00
Nb uops	33.00
Nb loads	24.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.50
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.00
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3
Source file and lines	csr_matvec.c:194-195
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:194-195.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 32.00 to 4.00 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 8 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	34
nb uops	33
loop length	165
used x86 registers	9
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.83 cycles
front end	6.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	4.00	8.00	8.00	0.00	0.00	1.00	0.00	0.00	0.00	0.00	8.00
cycles	4.00	4.00	8.00	8.00	0.00	0.00	1.00	0.00	0.00	0.00	0.00	8.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	32.00

Cycles summary

Front-end	6.83
Dispatch	8.00
Data deps.	32.00
Overall L1	32.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.00 cycles. At this rate:

3% of peak load performance is reached (6.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 543fee

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%RCX,%R9,8),%R12	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%R9),%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD (%RDX,%R12,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RCX,%RDI,8),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VFMADD231SD (%RSI,%R9,8),%XMM11,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RDX,%RBX,8),%XMM12	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x2(%R9),%RAX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RCX,%RAX,8),%R12	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VFMADD231SD (%RSI,%RDI,8),%XMM12,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RDX,%R12,8),%XMM13	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x3(%R9),%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RCX,%RDI,8),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VFMADD231SD (%RSI,%RAX,8),%XMM13,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RDX,%RBX,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x4(%R9),%RAX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RCX,%RAX,8),%R12	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VFMADD231SD (%RSI,%RDI,8),%XMM14,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RDX,%R12,8),%XMM15	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x5(%R9),%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RCX,%RDI,8),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VFMADD231SD (%RSI,%RAX,8),%XMM15,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RDX,%RBX,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x6(%R9),%RAX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RCX,%RAX,8),%R12	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VFMADD231SD (%RSI,%RDI,8),%XMM0,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RDX,%R12,8),%XMM8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x7(%R9),%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RCX,%RDI,8),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
ADD $0x8,%R9	1	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RSI,%RAX,8),%XMM8,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RDX,%RBX,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231SD (%RSI,%RDI,8),%XMM9,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
CMP %R11,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 543fee <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x84e>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3
Source file and lines	csr_matvec.c:194-195
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:194-195.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 32.00 to 4.00 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 8 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	34
nb uops	33
loop length	165
used x86 registers	9
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.83 cycles
front end	6.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	4.00	8.00	8.00	0.00	0.00	1.00	0.00	0.00	0.00	0.00	8.00
cycles	4.00	4.00	8.00	8.00	0.00	0.00	1.00	0.00	0.00	0.00	0.00	8.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	32.00

Cycles summary

Front-end	6.83
Dispatch	8.00
Data deps.	32.00
Overall L1	32.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.00 cycles. At this rate:

3% of peak load performance is reached (6.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 543fee

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%RCX,%R9,8),%R12	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%R9),%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD (%RDX,%R12,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RCX,%RDI,8),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VFMADD231SD (%RSI,%R9,8),%XMM11,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RDX,%RBX,8),%XMM12	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x2(%R9),%RAX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RCX,%RAX,8),%R12	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VFMADD231SD (%RSI,%RDI,8),%XMM12,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RDX,%R12,8),%XMM13	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x3(%R9),%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RCX,%RDI,8),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VFMADD231SD (%RSI,%RAX,8),%XMM13,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RDX,%RBX,8),%XMM14	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x4(%R9),%RAX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RCX,%RAX,8),%R12	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VFMADD231SD (%RSI,%RDI,8),%XMM14,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RDX,%R12,8),%XMM15	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x5(%R9),%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RCX,%RDI,8),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VFMADD231SD (%RSI,%RAX,8),%XMM15,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RDX,%RBX,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x6(%R9),%RAX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RCX,%RAX,8),%R12	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
VFMADD231SD (%RSI,%RDI,8),%XMM0,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RDX,%R12,8),%XMM8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x7(%R9),%RDI	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RCX,%RDI,8),%RBX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
ADD $0x8,%R9	1	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD231SD (%RSI,%RAX,8),%XMM8,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RDX,%RBX,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VFMADD231SD (%RSI,%RDI,8),%XMM9,%XMM10	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (12.5%)
CMP %R11,%R9	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 543fee <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x84e>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code