OV - exec - Loop 2693

	Loop Id: 2693	Module: exec	Source: IJMatrix_parcsr.c:3383-3454 [...]	Coverage: 1.12%

0x52e030 MOV	(%R8,%R15,8),%RDX

0x52e034 CMP	%RDX,-0x48(%RBP)

0x52e038 JG	52e210

0x52e03e CMP	%RDX,-0x58(%RBP)

0x52e042 JL	52e210

0x52e048 MOV	-0x90(%RBP),%R14

0x52e04f MOV	(%R14,%R10,1),%RAX

0x52e053 CMP	%RAX,%RCX

0x52e056 JLE	52e176

0x52e05c MOV	%RCX,%R14

0x52e05f SUB	%RAX,%R14

0x52e062 AND	$0x7,%R14D

0x52e066 JE	52e0f7

0x52e06c CMP	$0x1,%R14

0x52e070 JE	52e0e4

0x52e072 CMP	$0x2,%R14

0x52e076 JE	52e0d6

0x52e078 CMP	$0x3,%R14

0x52e07c JE	52e0c8

0x52e07e CMP	$0x4,%R14

0x52e082 JE	52e0ba

0x52e084 CMP	$0x5,%R14

0x52e088 JE	52e0ac

0x52e08a CMP	$0x6,%R14

0x52e08e JE	52e09e

0x52e090 CMP	(%R13,%RAX,8),%RDX

0x52e095 JE	52e380

0x52e09b INC	%RAX

0x52e09e CMP	(%R13,%RAX,8),%RDX

0x52e0a3 JE	52e380

0x52e0a9 INC	%RAX

0x52e0ac CMP	(%R13,%RAX,8),%RDX

0x52e0b1 JE	52e380

0x52e0b7 INC	%RAX

0x52e0ba CMP	(%R13,%RAX,8),%RDX

0x52e0bf JE	52e380

0x52e0c5 INC	%RAX

0x52e0c8 CMP	(%R13,%RAX,8),%RDX

0x52e0cd JE	52e380

0x52e0d3 INC	%RAX

0x52e0d6 CMP	(%R13,%RAX,8),%RDX

0x52e0db JE	52e380

0x52e0e1 INC	%RAX

0x52e0e4 CMP	(%R13,%RAX,8),%RDX

0x52e0e9 JE	52e380

0x52e0ef INC	%RAX

0x52e0f2 CMP	%RAX,%RCX

0x52e0f5 JE	52e176

  (2695) 0x52e0f7 CMP	(%R13,%RAX,8),%RDX

  (2695) 0x52e0fc JE	52e380

  (2695) 0x52e102 LEA	0x1(%RAX),%R14

  (2695) 0x52e106 MOV	%R14,%RAX

  (2695) 0x52e109 CMP	(%R13,%R14,8),%RDX

  (2695) 0x52e10e JE	52e380

  (2695) 0x52e114 INC	%RAX

  (2695) 0x52e117 CMP	(%R13,%RAX,8),%RDX

  (2695) 0x52e11c JE	52e380

  (2695) 0x52e122 LEA	0x2(%R14),%RAX

  (2695) 0x52e126 CMP	0x10(%R13,%R14,8),%RDX

  (2695) 0x52e12b JE	52e380

  (2695) 0x52e131 LEA	0x3(%R14),%RAX

  (2695) 0x52e135 CMP	0x18(%R13,%R14,8),%RDX

  (2695) 0x52e13a JE	52e380

  (2695) 0x52e140 LEA	0x4(%R14),%RAX

  (2695) 0x52e144 CMP	0x20(%R13,%R14,8),%RDX

  (2695) 0x52e149 JE	52e380

  (2695) 0x52e14f LEA	0x5(%R14),%RAX

  (2695) 0x52e153 CMP	0x28(%R13,%R14,8),%RDX

  (2695) 0x52e158 JE	52e380

  (2695) 0x52e15e LEA	0x6(%R14),%RAX

  (2695) 0x52e162 CMP	0x30(%R13,%R14,8),%RDX

  (2695) 0x52e167 JE	52e380

  (2695) 0x52e16d LEA	0x7(%R14),%RAX

  (2695) 0x52e171 CMP	%RAX,%RCX

  (2695) 0x52e174 JNE	52e0f7

0x52e176 CMP	%RBX,-0x40(%RBP)

0x52e17a JLE	52ecf5

0x52e180 MOV	%RDX,(%R13,%RBX,8)

0x52e185 VMOVSD	(%R9,%R15,8),%XMM0

0x52e18b MOV	-0xa0(%RBP),%RDX

0x52e192 LEA	(,%RBX,8),%R14

0x52e19a VMOVSD	%XMM0,(%RDX,%R14,1)

0x52e1a0 INC	%RBX

0x52e1a3 NOPL	(%RAX,%RAX,1)

0x52e1a8 INC	%R15

0x52e1ab CMP	%RDI,%R15

0x52e1ae JNE	52e030

0x52e210 MOV	-0x50(%RBP),%RAX

0x52e214 MOV	(%RAX,%R10,1),%RAX

0x52e218 CMP	%RAX,%RSI

0x52e21b JLE	52e321

0x52e221 MOV	%RSI,%R14

0x52e224 SUB	%RAX,%R14

0x52e227 AND	$0x7,%R14D

0x52e22b JE	52e2b5

0x52e231 CMP	$0x1,%R14

0x52e235 JE	52e2a3

0x52e237 CMP	$0x2,%R14

0x52e23b JE	52e296

0x52e23d CMP	$0x3,%R14

0x52e241 JE	52e289

0x52e243 CMP	$0x4,%R14

0x52e247 JE	52e27c

0x52e249 CMP	$0x5,%R14

0x52e24d JE	52e26f

0x52e24f CMP	$0x6,%R14

0x52e253 JE	52e262

0x52e255 CMP	(%R12,%RAX,8),%RDX

0x52e259 JE	52e368

0x52e25f INC	%RAX

0x52e262 CMP	(%R12,%RAX,8),%RDX

0x52e266 JE	52e368

0x52e26c INC	%RAX

0x52e26f CMP	(%R12,%RAX,8),%RDX

0x52e273 JE	52e368

0x52e279 INC	%RAX

0x52e27c CMP	(%R12,%RAX,8),%RDX

0x52e280 JE	52e368

0x52e286 INC	%RAX

0x52e289 CMP	(%R12,%RAX,8),%RDX

0x52e28d JE	52e368

0x52e293 INC	%RAX

0x52e296 CMP	(%R12,%RAX,8),%RDX

0x52e29a JE	52e368

0x52e2a0 INC	%RAX

0x52e2a3 CMP	(%R12,%RAX,8),%RDX

0x52e2a7 JE	52e368

0x52e2ad INC	%RAX

0x52e2b0 CMP	%RAX,%RSI

0x52e2b3 JE	52e321

  (2694) 0x52e2b5 CMP	(%R12,%RAX,8),%RDX

  (2694) 0x52e2b9 JE	52e368

  (2694) 0x52e2bf LEA	0x1(%RAX),%R14

  (2694) 0x52e2c3 MOV	%R14,%RAX

  (2694) 0x52e2c6 CMP	(%R12,%R14,8),%RDX

  (2694) 0x52e2ca JE	52e368

  (2694) 0x52e2d0 INC	%RAX

  (2694) 0x52e2d3 CMP	(%R12,%RAX,8),%RDX

  (2694) 0x52e2d7 JE	52e368

  (2694) 0x52e2dd LEA	0x2(%R14),%RAX

  (2694) 0x52e2e1 CMP	0x10(%R12,%R14,8),%RDX

  (2694) 0x52e2e6 JE	52e368

  (2694) 0x52e2ec LEA	0x3(%R14),%RAX

  (2694) 0x52e2f0 CMP	0x18(%R12,%R14,8),%RDX

  (2694) 0x52e2f5 JE	52e368

  (2694) 0x52e2f7 LEA	0x4(%R14),%RAX

  (2694) 0x52e2fb CMP	0x20(%R12,%R14,8),%RDX

  (2694) 0x52e300 JE	52e368

  (2694) 0x52e302 LEA	0x5(%R14),%RAX

  (2694) 0x52e306 CMP	0x28(%R12,%R14,8),%RDX

  (2694) 0x52e30b JE	52e368

  (2694) 0x52e30d LEA	0x6(%R14),%RAX

  (2694) 0x52e311 CMP	0x30(%R12,%R14,8),%RDX

  (2694) 0x52e316 JE	52e368

  (2694) 0x52e318 LEA	0x7(%R14),%RAX

  (2694) 0x52e31c CMP	%RAX,%RSI

  (2694) 0x52e31f JNE	52e2b5

0x52e321 CMP	%R11,-0x38(%RBP)

0x52e325 JLE	52ec05

0x52e32b VMOVSD	(%R9,%R15,8),%XMM2

0x52e331 MOV	-0x60(%RBP),%RAX

0x52e335 LEA	(,%R11,8),%R14

0x52e33d MOV	%RDX,(%R12,%R11,8)

0x52e341 INC	%R11

0x52e344 VMOVSD	%XMM2,(%RAX,%R14,1)

0x52e34a JMP	52e1a8

0x52e368 VMOVSD	(%R9,%R15,8),%XMM3

0x52e36e MOV	-0x60(%RBP),%RDX

0x52e372 VMOVSD	%XMM3,(%RDX,%RAX,8)

0x52e377 JMP	52e1a8

0x52e380 VMOVSD	(%R9,%R15,8),%XMM1

0x52e386 MOV	-0xa0(%RBP),%R14

0x52e38d VMOVSD	%XMM1,(%R14,%RAX,8)

0x52e393 JMP	52e1a8

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3383 - 3454

--------------------------------------------------------------------------------

3383:   	          for (i=0; i < n; i++)

3384: 	          {

3385: 	             if (cols[indx] < col_0 || cols[indx] > col_n)

3386:                      /* insert into offd */

3387: 	             {

3388: 	                for (j=offd_i[row_local]; j < offd_indx; j++)

3389: 	                {

3390: 		           if (offd_j[j] == cols[indx])

3391: 		           {

3392:                               offd_data[j] = values[indx];

3393: 		              not_found = 0;

3394: 		              break;

3395: 		           }

3396: 	                }

3397: 	                if (not_found)

3398: 	                {

3399: 	                   if (cnt_offd < offd_space)

3400: 	                   {

3401: 	                      offd_j[cnt_offd] = cols[indx];

3402: 	                      offd_data[cnt_offd++] = values[indx];

[...]

3422: 	                for (j=diag_i[row_local]; j < diag_indx; j++)

3423: 	                {

3424: 		           if (diag_j[j] == cols[indx])

3425: 		           {

3426:                               diag_data[j] = values[indx];

3427: 		              not_found = 0;

3428: 		              break;

3429: 		           }

3430: 	                }

3431: 	                if (not_found)

3432: 	                {

3433: 	                   if (cnt_diag < diag_space)

3434: 	                   {

3435: 	                      diag_j[cnt_diag] = cols[indx];

3436: 	                      diag_data[cnt_diag++] = values[indx];

[...]

3454: 	             indx++;

Coverage (%)	Name	Source Location	Module
○97.71	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.29	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.21
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	micro-operation queue,
Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source	IJMatrix_parcsr.c:3383-3385,IJMatrix_parcsr.c:3388-3392,IJMatrix_parcsr.c:3397-3402,IJMatrix_parcsr.c:3422-3426,IJMatrix_parcsr.c:3431-3436,IJMatrix_parcsr.c:3454-3454
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	22.33
CQA cycles if no scalar integer	18.50
CQA cycles if FP arith vectorized	22.33
CQA cycles if fully vectorized	2.79
Front-end cycles	22.33
P0 cycles	18.50
P1 cycles	13.00
P2 cycles	10.33
P3 cycles	10.33
P4 cycles	3.00
P5 cycles	13.00
P6 cycles	18.50
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	13.00
P11 cycles	10.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	120.00
Nb uops	120.00
Nb loads	31.00
Nb stores	6.00
Nb stack references	8.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.25
Bytes prefetched	0.00
Bytes loaded	248.00
Bytes stored	48.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.21
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	micro-operation queue,
Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source	IJMatrix_parcsr.c:3383-3385,IJMatrix_parcsr.c:3388-3392,IJMatrix_parcsr.c:3397-3402,IJMatrix_parcsr.c:3422-3426,IJMatrix_parcsr.c:3431-3436,IJMatrix_parcsr.c:3454-3454
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	22.33
CQA cycles if no scalar integer	18.50
CQA cycles if FP arith vectorized	22.33
CQA cycles if fully vectorized	2.79
Front-end cycles	22.33
P0 cycles	18.50
P1 cycles	13.00
P2 cycles	10.33
P3 cycles	10.33
P4 cycles	3.00
P5 cycles	13.00
P6 cycles	18.50
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	13.00
P11 cycles	10.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	120.00
Nb uops	120.00
Nb loads	31.00
Nb stores	6.00
Nb stack references	8.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.25
Bytes prefetched	0.00
Bytes loaded	248.00
Bytes stored	48.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source file and lines	IJMatrix_parcsr.c:3383-3454
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3383-3402,3422-3436,3454.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3383-3385,3388-3392,3397-3402,3422-3426,3431-3436,3454.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 324 paths individually, rerun with max-paths=324
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 324 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.33 to 18.50 cycles (1.21x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 22.33 to 2.79 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 248 bytes. The binary loop is storing 48 bytes.

General properties

nb instructions	120
nb uops	120
loop length	516
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.33 cycles
front end	22.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	18.50	13.00	10.33	10.33	3.00	13.00	18.50	3.00	3.00	3.00	13.00	10.33
cycles	18.50	13.00	10.33	10.33	3.00	13.00	18.50	3.00	3.00	3.00	13.00	10.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	22.33
Dispatch	18.50
Overall L1	22.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 22.33 cycles. At this rate:

5% of peak load performance is reached (11.10 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.15 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 22.33 to 18.50 cycles (1.21x speedup).

ASM code

In the binary file, the address of the loop is: 52e030

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%R8,%R15,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDX,-0x48(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JG 52e210 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %RDX,-0x58(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JL 52e210 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x90(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14,%R10,1),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 52e176 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x626>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 52e0f7 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x5a7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e0e4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x594>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e0d6 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x586>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e0c8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x578>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e0ba <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x56a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e0ac <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x55c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e09e <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x54e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP (%R13,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e380 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x830>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R13,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e380 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x830>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R13,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e380 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x830>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R13,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e380 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x830>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R13,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e380 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x830>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R13,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e380 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x830>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R13,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e380 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x830>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e176 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x626>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %RBX,-0x40(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JLE 52ecf5 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x11a5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,(%R13,%RBX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R9,%R15,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xa0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RBX,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM0,(%RDX,%R14,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 52e030 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x4e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R10,1),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 52e321 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7d1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 52e2b5 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x765>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e2a3 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x753>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e296 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x746>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e289 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x739>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e27c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x72c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e26f <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x71f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e262 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x712>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP (%R12,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e368 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x818>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R12,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e368 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x818>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R12,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e368 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x818>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R12,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e368 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x818>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R12,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e368 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x818>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R12,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e368 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x818>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R12,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e368 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x818>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e321 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7d1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R11,-0x38(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JLE 52ec05 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x10b5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R9,%R15,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R11,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,(%R12,%R11,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM2,(%RAX,%R14,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 52e1a8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x658>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVSD (%R9,%R15,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM3,(%RDX,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 52e1a8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x658>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVSD (%R9,%R15,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xa0(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM1,(%R14,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 52e1a8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x658>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source file and lines	IJMatrix_parcsr.c:3383-3454
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 324 paths individually, rerun with max-paths=324
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 248 bytes. The binary loop is storing 48 bytes.

General properties

nb instructions	120
nb uops	120
loop length	516
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.33 cycles
front end	22.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	18.50	13.00	10.33	10.33	3.00	13.00	18.50	3.00	3.00	3.00	13.00	10.33
cycles	18.50	13.00	10.33	10.33	3.00	13.00	18.50	3.00	3.00	3.00	13.00	10.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	22.33
Dispatch	18.50
Overall L1	22.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 22.33 cycles. At this rate:

5% of peak load performance is reached (11.10 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.15 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 52e030

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%R8,%R15,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDX,-0x48(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JG 52e210 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %RDX,-0x58(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JL 52e210 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x6c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x90(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14,%R10,1),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 52e176 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x626>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 52e0f7 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x5a7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e0e4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x594>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e0d6 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x586>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e0c8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x578>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e0ba <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x56a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e0ac <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x55c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e09e <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x54e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP (%R13,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e380 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x830>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R13,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e380 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x830>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R13,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e380 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x830>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R13,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e380 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x830>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R13,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e380 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x830>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R13,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e380 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x830>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R13,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e380 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x830>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e176 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x626>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %RBX,-0x40(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JLE 52ecf5 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x11a5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,(%R13,%RBX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R9,%R15,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xa0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RBX,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM0,(%RDX,%R14,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 52e030 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x4e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R10,1),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 52e321 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7d1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 52e2b5 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x765>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e2a3 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x753>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e296 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x746>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e289 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x739>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e27c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x72c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e26f <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x71f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e262 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x712>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP (%R12,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e368 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x818>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R12,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e368 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x818>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R12,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e368 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x818>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R12,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e368 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x818>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R12,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e368 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x818>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R12,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e368 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x818>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP (%R12,%RAX,8),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 52e368 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x818>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 52e321 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7d1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R11,-0x38(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JLE 52ec05 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x10b5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R9,%R15,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R11,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,(%R12,%R11,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM2,(%RAX,%R14,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 52e1a8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x658>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVSD (%R9,%R15,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x60(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM3,(%RDX,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 52e1a8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x658>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVSD (%R9,%R15,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xa0(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM1,(%R14,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 52e1a8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x658>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code