OV - exec - Loop 2358

	Loop Id: 2358	Module: exec	Source: par_csr_matop.c:865-989 [...]	Coverage: 0.02%

0x50fd90 CMPQ	$0,-0x118(%RBP)

0x50fd98 MOV	%R12,%RDX

0x50fd9b JNE	50ff01

0x50fda5 MOV	-0xb0(%RBP),%R9

0x50fdac MOV	-0xa0(%RBP),%R11

0x50fdb3 MOV	(%R9,%R11,8),%R14

0x50fdb7 CMP	0x8(%R9,%R11,8),%R14

0x50fdbc JGE	50fea5

0x50fdc2 MOV	%R14,-0x48(%RBP)

0x50fdc6 MOV	-0x128(%RBP),%R11

0x50fdcd MOV	-0x130(%RBP),%R13

0x50fdd4 NOPL	(%RAX)

  (2362) 0x50fdd8 MOV	-0x48(%RBP),%R10

  (2362) 0x50fddc MOV	-0xc8(%RBP),%RDI

  (2362) 0x50fde3 MOV	-0xc0(%RBP),%R15

  (2362) 0x50fdea MOV	(%RDI,%R10,8),%RDI

  (2362) 0x50fdee MOV	-0xd0(%RBP),%RCX

  (2362) 0x50fdf5 LEA	0x8(,%RDI,8),%R9

  (2362) 0x50fdfd LEA	(%R15,%R9,1),%R14

  (2362) 0x50fe01 VMOVSD	(%RCX,%R10,8),%XMM7

  (2362) 0x50fe07 MOV	(%R15,%RDI,8),%RAX

  (2362) 0x50fe0b MOV	(%R14),%R10

  (2362) 0x50fe0e CMP	%R10,%RAX

  (2362) 0x50fe11 JGE	50fe76

  (2362) 0x50fe13 MOV	%R9,-0xa8(%RBP)

  (2362) 0x50fe1a NOPW	%CS:(%RAX,%RAX,1)

  (2362) 0x50fe25 NOPW	%CS:(%RAX,%RAX,1)

  (2362) 0x50fe30 NOPW	%CS:(%RAX,%RAX,1)

  (2362) 0x50fe3b NOPL	(%RAX,%RAX,1)

    (2364) 0x50fe40 MOV	(%R11,%RAX,8),%RCX

    (2364) 0x50fe44 VMULSD	(%R13,%RAX,8),%XMM7,%XMM8

    (2364) 0x50fe4b LEA	(%R8,%RCX,8),%R9

    (2364) 0x50fe4f MOV	(%R9),%R15

    (2364) 0x50fe52 CMP	%R12,%R15

    (2364) 0x50fe55 JL	510060

    (2364) 0x50fe5b LEA	(%RBX,%R15,8),%RCX

    (2364) 0x50fe5f VADDSD	(%RCX),%XMM8,%XMM9

    (2364) 0x50fe63 INC	%RAX

    (2364) 0x50fe66 VMOVSD	%XMM9,(%RCX)

    (2364) 0x50fe6a CMP	%R10,%RAX

    (2364) 0x50fe6d JL	50fe40

  (2362) 0x50fe6f MOV	-0xa8(%RBP),%R9

  (2362) 0x50fe76 CMPQ	$0,-0xb8(%RBP)

  (2362) 0x50fe7e JNE	510090

  (2362) 0x50fe84 INCQ	-0x48(%RBP)

  (2362) 0x50fe88 MOV	-0xb0(%RBP),%R14

  (2362) 0x50fe8f MOV	-0xa0(%RBP),%R15

  (2362) 0x50fe96 MOV	-0x48(%RBP),%RAX

  (2362) 0x50fe9a CMP	%RAX,0x8(%R14,%R15,8)

  (2362) 0x50fe9f JG	50fdd8

0x50fea5 INCQ	-0xa0(%RBP)

0x50feac MOV	-0xa0(%RBP),%R12

0x50feb3 CMP	%R12,-0x120(%RBP)

0x50feba JE	5101a3

0x50fec0 CMPQ	$0,-0x110(%RBP)

0x50fec8 MOV	%RSI,-0x50(%RBP)

0x50fecc MOV	%RDX,%R12

0x50fecf JE	50fd90

0x50ff01 MOV	-0xe0(%RBP),%RDI

0x50ff08 MOV	-0xa0(%RBP),%RSI

0x50ff0f MOV	(%RDI,%RSI,8),%R9

0x50ff13 CMP	0x8(%RDI,%RSI,8),%R9

0x50ff18 JGE	50fda1

0x50ff1e MOV	-0x50(%RBP),%R11

0x50ff22 MOV	%RBX,-0x48(%RBP)

0x50ff26 MOV	-0x58(%RBP),%R14

0x50ff2a MOV	%R11,%RSI

0x50ff2d NOPL	(%RAX)

  (2357) 0x50ff30 MOV	-0x100(%RBP),%RAX

  (2357) 0x50ff37 MOV	-0xe8(%RBP),%R10

  (2357) 0x50ff3e MOV	(%RAX,%R9,8),%RDI

  (2357) 0x50ff42 MOV	-0x108(%RBP),%RBX

  (2357) 0x50ff49 LEA	0x8(,%RDI,8),%R13

  (2357) 0x50ff51 MOV	(%R10,%RDI,8),%RAX

  (2357) 0x50ff55 ADD	%R13,%R10

  (2357) 0x50ff58 MOV	%R10,-0xa8(%RBP)

  (2357) 0x50ff5f MOV	(%R10),%R10

  (2357) 0x50ff62 VMOVSD	(%RBX,%R9,8),%XMM2

  (2357) 0x50ff68 CMP	%R10,%RAX

  (2357) 0x50ff6b JGE	50ffc4

  (2357) 0x50ff6d MOV	%RDX,-0xd8(%RBP)

  (2357) 0x50ff74 NOPW	%CS:(%RAX,%RAX,1)

  (2357) 0x50ff7f NOP

    (2360) 0x50ff80 MOV	-0x60(%RBP),%R15

    (2360) 0x50ff84 MOV	(%R15,%RAX,8),%RCX

    (2360) 0x50ff88 LEA	(%R14,%RCX,1),%RDX

    (2360) 0x50ff8c LEA	(%R8,%RDX,8),%RBX

    (2360) 0x50ff90 MOV	(%RBX),%R15

    (2360) 0x50ff93 MOV	-0x68(%RBP),%RDX

    (2360) 0x50ff97 VMULSD	(%RDX,%RAX,8),%XMM2,%XMM1

    (2360) 0x50ff9c CMP	%R11,%R15

    (2360) 0x50ff9f JL	510170

    (2360) 0x50ffa5 MOV	-0x40(%RBP),%RCX

    (2360) 0x50ffa9 INC	%RAX

    (2360) 0x50ffac LEA	(%RCX,%R15,8),%RBX

    (2360) 0x50ffb0 VADDSD	(%RBX),%XMM1,%XMM4

    (2360) 0x50ffb4 VMOVSD	%XMM4,(%RBX)

    (2360) 0x50ffb8 CMP	%R10,%RAX

    (2360) 0x50ffbb JL	50ff80

  (2357) 0x50ffbd MOV	-0xd8(%RBP),%RDX

  (2357) 0x50ffc4 MOV	-0xf0(%RBP),%RCX

  (2357) 0x50ffcb MOV	(%RCX,%RDI,8),%RAX

  (2357) 0x50ffcf LEA	(%RCX,%R13,1),%RDI

  (2357) 0x50ffd3 MOV	(%RDI),%R10

  (2357) 0x50ffd6 MOV	%RDI,%R15

  (2357) 0x50ffd9 CMP	%R10,%RAX

  (2357) 0x50ffdc JGE	51003a

  (2357) 0x50ffde NOPW	%CS:(%RAX,%RAX,1)

  (2357) 0x50ffe9 NOPW	%CS:(%RAX,%RAX,1)

  (2357) 0x50fff4 NOPW	%CS:(%RAX,%RAX,1)

  (2357) 0x50ffff NOP

    (2359) 0x510000 MOV	-0x70(%RBP),%R13

    (2359) 0x510004 MOV	-0x78(%RBP),%RBX

    (2359) 0x510008 MOV	(%R13,%RAX,8),%RCX

    (2359) 0x51000d VMULSD	(%RBX,%RAX,8),%XMM2,%XMM5

    (2359) 0x510012 LEA	(%R8,%RCX,8),%RDI

    (2359) 0x510016 MOV	(%RDI),%R13

    (2359) 0x510019 CMP	%R12,%R13

    (2359) 0x51001c JL	510140

    (2359) 0x510022 MOV	-0x48(%RBP),%RCX

    (2359) 0x510026 INC	%RAX

    (2359) 0x510029 LEA	(%RCX,%R13,8),%RDI

    (2359) 0x51002d VADDSD	(%RDI),%XMM5,%XMM6

    (2359) 0x510031 VMOVSD	%XMM6,(%RDI)

    (2359) 0x510035 CMP	%R10,%RAX

    (2359) 0x510038 JL	510000

  (2357) 0x51003a MOV	-0xe0(%RBP),%RAX

  (2357) 0x510041 MOV	-0xa0(%RBP),%R15

  (2357) 0x510048 INC	%R9

  (2357) 0x51004b CMP	%R9,0x8(%RAX,%R15,8)

  (2357) 0x510050 JG	50ff30

0x510056 MOV	-0x48(%RBP),%RBX

0x51005a JMP	50fda5

    (2364) 0x510060 MOV	-0x38(%RBP),%R10

    (2364) 0x510064 MOV	%RDX,(%R9)

    (2364) 0x510067 VMOVSD	%XMM8,(%RBX,%RDX,8)

    (2364) 0x51006c MOV	%RCX,(%R10,%RDX,8)

    (2364) 0x510070 INC	%RAX

    (2364) 0x510073 INC	%RDX

    (2364) 0x510076 MOV	(%R14),%R10

    (2364) 0x510079 CMP	%RAX,%R10

    (2364) 0x51007c JG	50fe40

  (2362) 0x510082 JMP	50fe6f

  (2362) 0x510090 MOV	-0xf8(%RBP),%R14

  (2362) 0x510097 MOV	(%R14,%RDI,8),%RAX

  (2362) 0x51009b LEA	(%R14,%R9,1),%R14

  (2362) 0x51009f MOV	(%R14),%R10

  (2362) 0x5100a2 CMP	%R10,%RAX

  (2362) 0x5100a5 JGE	50fe84

  (2362) 0x5100ab NOPL	(%RAX,%RAX,1)

    (2363) 0x5100b0 MOV	-0x90(%RBP),%RDI

    (2363) 0x5100b7 MOV	-0x88(%RBP),%RCX

    (2363) 0x5100be MOV	(%RDI,%RAX,8),%R15

    (2363) 0x5100c2 MOV	-0x58(%RBP),%R9

    (2363) 0x5100c6 MOV	(%RCX,%R15,8),%RCX

    (2363) 0x5100ca MOV	-0x98(%RBP),%R15

    (2363) 0x5100d1 ADD	%RCX,%R9

    (2363) 0x5100d4 LEA	(%R8,%R9,8),%RDI

    (2363) 0x5100d8 VMULSD	(%R15,%RAX,8),%XMM7,%XMM10

    (2363) 0x5100de MOV	(%RDI),%R9

    (2363) 0x5100e1 MOV	-0x50(%RBP),%R15

    (2363) 0x5100e5 CMP	%R15,%R9

    (2363) 0x5100e8 JL	510110

    (2363) 0x5100ea MOV	-0x40(%RBP),%RCX

    (2363) 0x5100ee INC	%RAX

    (2363) 0x5100f1 LEA	(%RCX,%R9,8),%RDI

    (2363) 0x5100f5 VADDSD	(%RDI),%XMM10,%XMM11

    (2363) 0x5100f9 VMOVSD	%XMM11,(%RDI)

    (2363) 0x5100fd CMP	%R10,%RAX

    (2363) 0x510100 JL	5100b0

  (2362) 0x510102 JMP	50fe84

    (2363) 0x510110 MOV	-0x40(%RBP),%R10

    (2363) 0x510114 MOV	-0x80(%RBP),%R9

    (2363) 0x510118 MOV	%RSI,(%RDI)

    (2363) 0x51011b VMOVSD	%XMM10,(%R10,%RSI,8)

    (2363) 0x510121 MOV	%RCX,(%R9,%RSI,8)

    (2363) 0x510125 INC	%RAX

    (2363) 0x510128 INC	%RSI

    (2363) 0x51012b MOV	(%R14),%R10

    (2363) 0x51012e CMP	%RAX,%R10

    (2363) 0x510131 JG	5100b0

  (2362) 0x510137 JMP	50fe84

    (2359) 0x510140 MOV	-0x48(%RBP),%R10

    (2359) 0x510144 MOV	-0x38(%RBP),%R13

    (2359) 0x510148 MOV	%RDX,(%RDI)

    (2359) 0x51014b VMOVSD	%XMM5,(%R10,%RDX,8)

    (2359) 0x510151 MOV	%RCX,(%R13,%RDX,8)

    (2359) 0x510156 INC	%RAX

    (2359) 0x510159 INC	%RDX

    (2359) 0x51015c MOV	(%R15),%R10

    (2359) 0x51015f CMP	%RAX,%R10

    (2359) 0x510162 JG	510000

  (2357) 0x510168 JMP	51003a

    (2360) 0x510170 MOV	-0x40(%RBP),%R10

    (2360) 0x510174 MOV	-0x80(%RBP),%R15

    (2360) 0x510178 MOV	%RSI,(%RBX)

    (2360) 0x51017b VMOVSD	%XMM1,(%R10,%RSI,8)

    (2360) 0x510181 MOV	%RCX,(%R15,%RSI,8)

    (2360) 0x510185 MOV	-0xa8(%RBP),%RDX

    (2360) 0x51018c INC	%RAX

    (2360) 0x51018f MOV	(%RDX),%R10

    (2360) 0x510192 INC	%RSI

    (2360) 0x510195 CMP	%RAX,%R10

    (2360) 0x510198 JG	50ff80

  (2357) 0x51019e JMP	50ffbd

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 865 - 989

--------------------------------------------------------------------------------

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

Coverage (%)	Name	Source Location	Module
○96.76	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○3.24	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.40
Bottlenecks	micro-operation queue,
Function	hypre_ParMatmul._omp_fn.3
Source	par_csr_matop.c:865-865,par_csr_matop.c:874-874,par_csr_matop.c:886-888,par_csr_matop.c:937-937
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	0.75
Front-end cycles	6.00
P0 cycles	2.50
P1 cycles	2.00
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	2.50
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	6.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	34.00
Nb loads	18.00
Nb stores	4.00
Nb stack references	11.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.33
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.40
Bottlenecks	micro-operation queue,
Function	hypre_ParMatmul._omp_fn.3
Source	par_csr_matop.c:865-865,par_csr_matop.c:874-874,par_csr_matop.c:886-888,par_csr_matop.c:937-937
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	0.75
Front-end cycles	6.00
P0 cycles	2.50
P1 cycles	2.00
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	2.50
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	6.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	34.00
Nb loads	18.00
Nb stores	4.00
Nb stack references	11.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.33
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul._omp_fn.3
Source file and lines	par_csr_matop.c:865-989
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874,886-891,897-899,907-928,937-940,946-948,956-972,980-989.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874,886-888,937.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 0.75 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 144 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	32
nb uops	34
loop length	172
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	2.00	6.00	6.00	2.00	2.00	2.50	2.00	2.00	2.00	2.00	6.00
cycles	2.50	2.00	6.00	6.00	2.00	2.00	2.50	2.00	2.00	2.00	2.00	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	6.00
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

12% of peak load performance is reached (24.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 2.50 cycles (2.40x speedup).

ASM code

In the binary file, the address of the loop is: 50fda5

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
CMPQ $0,-0x118(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 50ff01 <hypre_ParMatmul._omp_fn.3+0x371>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb0(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xa0(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R9,%R11,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP 0x8(%R9,%R11,8),%R14	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 50fea5 <hypre_ParMatmul._omp_fn.3+0x315>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x128(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x130(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INCQ -0xa0(%RBP)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV -0xa0(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %R12,-0x120(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 5101a3 <hypre_ParMatmul._omp_fn.3+0x613>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPQ $0,-0x110(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %RSI,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 50fd90 <hypre_ParMatmul._omp_fn.3+0x200>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xe0(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xa0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI,%RSI,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP 0x8(%RDI,%RSI,8),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JGE 50fda1 <hypre_ParMatmul._omp_fn.3+0x211>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x50(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x58(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R11,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x48(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 50fda5 <hypre_ParMatmul._omp_fn.3+0x215>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_ParMatmul._omp_fn.3
Source file and lines	par_csr_matop.c:865-989
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 0.75 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 144 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	32
nb uops	34
loop length	172
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	2.00	6.00	6.00	2.00	2.00	2.50	2.00	2.00	2.00	2.00	6.00
cycles	2.50	2.00	6.00	6.00	2.00	2.00	2.50	2.00	2.00	2.00	2.00	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	6.00
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

12% of peak load performance is reached (24.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 50fda5

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
CMPQ $0,-0x118(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 50ff01 <hypre_ParMatmul._omp_fn.3+0x371>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb0(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xa0(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R9,%R11,8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP 0x8(%R9,%R11,8),%R14	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 50fea5 <hypre_ParMatmul._omp_fn.3+0x315>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x128(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x130(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INCQ -0xa0(%RBP)	3	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV -0xa0(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %R12,-0x120(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 5101a3 <hypre_ParMatmul._omp_fn.3+0x613>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPQ $0,-0x110(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %RSI,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 50fd90 <hypre_ParMatmul._omp_fn.3+0x200>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xe0(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xa0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI,%RSI,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP 0x8(%RDI,%RSI,8),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JGE 50fda1 <hypre_ParMatmul._omp_fn.3+0x211>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x50(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x58(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R11,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x48(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 50fda5 <hypre_ParMatmul._omp_fn.3+0x215>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code