OV - exec - Loop 2352

	Loop Id: 2352	Module: exec	Source: par_csr_matop.c:187-231 [...]	Coverage: 0.67%

0x50f0d8 MOV	-0x70(%RBP),%RAX

0x50f0dc MOV	-0x68(%RBP),%RDX

0x50f0e0 MOV	(%RAX,%R11,8),%R15

0x50f0e4 LEA	0x8(,%R15,8),%R13

0x50f0ec LEA	(%RDX,%R13,1),%R12

0x50f0f0 MOV	(%RDX,%R15,8),%RAX

0x50f0f4 MOV	(%R12),%RSI

0x50f0f8 CMP	%RSI,%RAX

0x50f0fb JGE	50f119

0x50f0fd NOPL	(%RAX)

  (2354) 0x50f100 MOV	(%R9,%RAX,8),%RDX

  (2354) 0x50f104 LEA	(%RDI,%RDX,8),%RDX

  (2354) 0x50f108 CMP	%RBX,(%RDX)

  (2354) 0x50f10b JL	50f280

  (2354) 0x50f111 INC	%RAX

  (2354) 0x50f114 CMP	%RSI,%RAX

  (2354) 0x50f117 JL	50f100

0x50f119 CMPQ	$0,-0x60(%RBP)

0x50f11e JNE	50f2a1

0x50f124 MOV	-0x50(%RBP),%R13

0x50f128 MOV	-0x48(%RBP),%RAX

0x50f12c INC	%R11

0x50f12f CMP	%R11,0x8(%R13,%RAX,8)

0x50f134 JG	50f0d8

  (2354) 0x50f280 MOV	%RCX,(%RDX)

  (2354) 0x50f283 INC	%RAX

  (2354) 0x50f286 INC	%RCX

  (2354) 0x50f289 MOV	(%R12),%RSI

  (2354) 0x50f28d CMP	%RAX,%RSI

  (2354) 0x50f290 JG	50f100

0x50f296 CMPQ	$0,-0x60(%RBP)

0x50f29b JE	50f124

0x50f2a1 MOV	-0x90(%RBP),%R12

0x50f2a8 ADD	%R12,%R13

0x50f2ab MOV	(%R12,%R15,8),%RAX

0x50f2af MOV	(%R13),%RSI

0x50f2b3 CMP	%RSI,%RAX

0x50f2b6 JGE	50f124

0x50f2bc NOPL	(%RAX)

  (2353) 0x50f2c0 MOV	(%R14,%RAX,8),%RDX

  (2353) 0x50f2c4 MOV	-0x40(%RBP),%R12

  (2353) 0x50f2c8 MOV	-0x38(%RBP),%R15

  (2353) 0x50f2cc ADD	(%R12,%RDX,8),%R15

  (2353) 0x50f2d0 LEA	(%RDI,%R15,8),%RDX

  (2353) 0x50f2d4 CMP	%R10,(%RDX)

  (2353) 0x50f2d7 JL	50f2f0

  (2353) 0x50f2d9 INC	%RAX

  (2353) 0x50f2dc CMP	%RSI,%RAX

  (2353) 0x50f2df JL	50f2c0

0x50f2e1 JMP	50f124

  (2353) 0x50f2f0 MOV	%R8,(%RDX)

  (2353) 0x50f2f3 INC	%RAX

  (2353) 0x50f2f6 INC	%R8

  (2353) 0x50f2f9 MOV	(%R13),%RSI

  (2353) 0x50f2fd CMP	%RAX,%RSI

  (2353) 0x50f300 JG	50f2c0

0x50f302 JMP	50f124

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 187 - 231

--------------------------------------------------------------------------------

187:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

[...]

195:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

[...]

205:             if (B_marker[i3] < jj_row_begin_diag)

206:             {

207:                B_marker[i3] = jj_count_diag;

208:                jj_count_diag++;

[...]

216:          if (num_cols_offd_B)

217:          {

218:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

219:             {

220:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

228:                if (B_marker[i3] < jj_row_begin_offd)

229:                {

230:                   B_marker[i3] = jj_count_offd;

231:                   jj_count_offd++;

Coverage (%)	Name	Source Location	Module
○98.07	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.93	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.12
Bottlenecks	micro-operation queue,
Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source	par_csr_matop.c:187-187,par_csr_matop.c:195-195,par_csr_matop.c:216-218
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.83
CQA cycles if no scalar integer	4.83
CQA cycles if FP arith vectorized	4.83
CQA cycles if fully vectorized	0.60
Front-end cycles	4.83
P0 cycles	2.50
P1 cycles	2.00
P2 cycles	4.33
P3 cycles	4.33
P4 cycles	0.00
P5 cycles	2.00
P6 cycles	2.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	2.00
P11 cycles	4.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	28.00
Nb loads	13.00
Nb stores	0.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.52
Bytes prefetched	0.00
Bytes loaded	104.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.12
Bottlenecks	micro-operation queue,
Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source	par_csr_matop.c:187-187,par_csr_matop.c:195-195,par_csr_matop.c:216-218
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.83
CQA cycles if no scalar integer	4.83
CQA cycles if FP arith vectorized	4.83
CQA cycles if fully vectorized	0.60
Front-end cycles	4.83
P0 cycles	2.50
P1 cycles	2.00
P2 cycles	4.33
P3 cycles	4.33
P4 cycles	0.00
P5 cycles	2.00
P6 cycles	2.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	2.00
P11 cycles	4.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	28.00
Nb loads	13.00
Nb stores	0.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.52
Bytes prefetched	0.00
Bytes loaded	104.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source file and lines	par_csr_matop.c:187-231
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:187,195,205-208,216-220,228-231.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:187,195,216-218.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=12
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 12 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.83 to 0.60 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 104 bytes.

General properties

nb instructions	28
nb uops	28
loop length	121
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.83 cycles
front end	4.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	2.00	4.33	4.33	0.00	2.00	2.50	0.00	0.00	0.00	2.00	4.33
cycles	2.50	2.00	4.33	4.33	0.00	2.00	2.50	0.00	0.00	0.00	2.00	4.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.83
Dispatch	4.33
Overall L1	4.83

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.83 cycles. At this rate:

11% of peak load performance is reached (21.52 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.83 to 4.33 cycles (1.12x speedup).

ASM code

In the binary file, the address of the loop is: 50f0d8

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x70(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R11,8),%R15	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
LEA 0x8(,%R15,8),%R13	1	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RDX,%R13,1),%R12	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDX,%R15,8),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%R12),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %RSI,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JGE 50f119 <hypre_ParMatmul_RowSizes._omp_fn.0+0x259>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMPQ $0,-0x60(%RBP)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JNE 50f2a1 <hypre_ParMatmul_RowSizes._omp_fn.0+0x3e1>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x50(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
INC %R11	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11,0x8(%R13,%RAX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JG 50f0d8 <hypre_ParMatmul_RowSizes._omp_fn.0+0x218>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMPQ $0,-0x60(%RBP)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 50f124 <hypre_ParMatmul_RowSizes._omp_fn.0+0x264>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x90(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
ADD %R12,%R13	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV (%R12,%R15,8),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%R13),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %RSI,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JGE 50f124 <hypre_ParMatmul_RowSizes._omp_fn.0+0x264>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 50f124 <hypre_ParMatmul_RowSizes._omp_fn.0+0x264>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 50f124 <hypre_ParMatmul_RowSizes._omp_fn.0+0x264>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source file and lines	par_csr_matop.c:187-231
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=12
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.83 to 0.60 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 104 bytes.

General properties

nb instructions	28
nb uops	28
loop length	121
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.83 cycles
front end	4.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	2.00	4.33	4.33	0.00	2.00	2.50	0.00	0.00	0.00	2.00	4.33
cycles	2.50	2.00	4.33	4.33	0.00	2.00	2.50	0.00	0.00	0.00	2.00	4.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.83
Dispatch	4.33
Overall L1	4.83

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.83 cycles. At this rate:

11% of peak load performance is reached (21.52 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 50f0d8

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x70(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R11,8),%R15	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
LEA 0x8(,%R15,8),%R13	1	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RDX,%R13,1),%R12	1	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDX,%R15,8),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%R12),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %RSI,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (12.5%)
JGE 50f119 <hypre_ParMatmul_RowSizes._omp_fn.0+0x259>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMPQ $0,-0x60(%RBP)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JNE 50f2a1 <hypre_ParMatmul_RowSizes._omp_fn.0+0x3e1>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x50(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
INC %R11	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11,0x8(%R13,%RAX,8)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JG 50f0d8 <hypre_ParMatmul_RowSizes._omp_fn.0+0x218>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
CMPQ $0,-0x60(%RBP)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JE 50f124 <hypre_ParMatmul_RowSizes._omp_fn.0+0x264>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x90(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
ADD %R12,%R13	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV (%R12,%R15,8),%RAX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOV (%R13),%RSI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
CMP %RSI,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JGE 50f124 <hypre_ParMatmul_RowSizes._omp_fn.0+0x264>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 50f124 <hypre_ParMatmul_RowSizes._omp_fn.0+0x264>	1	0	0	0	0	0	0	0	0	0	2.08	N/A
JMP 50f124 <hypre_ParMatmul_RowSizes._omp_fn.0+0x264>	1	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code