OV - exec - Loop 2347

	Loop Id: 2347	Module: exec	Source: par_csr_matop.c:127-242 [...]	Coverage: 0.03%

0x50f0a5 CMPQ	$0,-0xb0(%RBP)

0x50f0ad MOV	%RBX,%RCX

0x50f0b0 MOV	%R10,%R8

0x50f0b3 JNE	50f195

0x50f0b9 MOV	-0x50(%RBP),%R13

0x50f0bd MOV	-0x48(%RBP),%R15

0x50f0c1 MOV	-0xc8(%RBP),%R9

0x50f0c8 MOV	(%R13,%R15,8),%R11

0x50f0cd CMP	0x8(%R13,%R15,8),%R11

0x50f0d2 JGE	50f136

0x50f0d4 NOPL	(%RAX)

  (2352) 0x50f0d8 MOV	-0x70(%RBP),%RAX

  (2352) 0x50f0dc MOV	-0x68(%RBP),%RDX

  (2352) 0x50f0e0 MOV	(%RAX,%R11,8),%R15

  (2352) 0x50f0e4 LEA	0x8(,%R15,8),%R13

  (2352) 0x50f0ec LEA	(%RDX,%R13,1),%R12

  (2352) 0x50f0f0 MOV	(%RDX,%R15,8),%RAX

  (2352) 0x50f0f4 MOV	(%R12),%RSI

  (2352) 0x50f0f8 CMP	%RSI,%RAX

  (2352) 0x50f0fb JGE	50f119

  (2352) 0x50f0fd NOPL	(%RAX)

    (2354) 0x50f100 MOV	(%R9,%RAX,8),%RDX

    (2354) 0x50f104 LEA	(%RDI,%RDX,8),%RDX

    (2354) 0x50f108 CMP	%RBX,(%RDX)

    (2354) 0x50f10b JL	50f280

    (2354) 0x50f111 INC	%RAX

    (2354) 0x50f114 CMP	%RSI,%RAX

    (2354) 0x50f117 JL	50f100

  (2352) 0x50f119 CMPQ	$0,-0x60(%RBP)

  (2352) 0x50f11e JNE	50f2a1

  (2352) 0x50f124 MOV	-0x50(%RBP),%R13

  (2352) 0x50f128 MOV	-0x48(%RBP),%RAX

  (2352) 0x50f12c INC	%R11

  (2352) 0x50f12f CMP	%R11,0x8(%R13,%RAX,8)

  (2352) 0x50f134 JG	50f0d8

0x50f136 MOV	-0x48(%RBP),%R9

0x50f13a MOV	-0xb8(%RBP),%R11

0x50f141 MOV	%RBX,(%R11,%R9,8)

0x50f145 MOV	-0xc0(%RBP),%RBX

0x50f14c MOV	%R10,(%RBX,%R9,8)

0x50f150 INC	%R9

0x50f153 MOV	%R9,-0x48(%RBP)

0x50f157 CMP	%R9,-0xa0(%RBP)

0x50f15e JE	50f34a

0x50f164 CMPQ	$0,-0xa8(%RBP)

0x50f16c MOV	%R8,%R10

0x50f16f MOV	%RCX,%RBX

0x50f172 JE	50f0a5

0x50f195 MOV	-0x78(%RBP),%R12

0x50f199 MOV	-0x48(%RBP),%R9

0x50f19d MOV	(%R12,%R9,8),%R11

0x50f1a1 MOV	%R11,-0x58(%RBP)

0x50f1a5 CMP	0x8(%R12,%R9,8),%R11

0x50f1aa JGE	50f0b9

0x50f1b0 MOV	%R14,-0xd0(%RBP)

0x50f1b7 MOV	-0x38(%RBP),%R13

0x50f1bb MOV	-0xe0(%RBP),%R11

0x50f1c2 MOV	-0xe8(%RBP),%R15

0x50f1c9 NOPL	(%RAX)

  (2348) 0x50f1d0 MOV	-0x58(%RBP),%RAX

  (2348) 0x50f1d4 MOV	-0x98(%RBP),%R14

  (2348) 0x50f1db MOV	-0x80(%RBP),%RSI

  (2348) 0x50f1df MOV	(%R14,%RAX,8),%R14

  (2348) 0x50f1e3 LEA	0x8(,%R14,8),%R9

  (2348) 0x50f1eb LEA	(%RSI,%R9,1),%R12

  (2348) 0x50f1ef MOV	(%RSI,%R14,8),%RAX

  (2348) 0x50f1f3 MOV	(%R12),%RSI

  (2348) 0x50f1f7 CMP	%RSI,%RAX

  (2348) 0x50f1fa JGE	50f21c

  (2348) 0x50f1fc NOPL	(%RAX)

    (2350) 0x50f200 MOV	(%R11,%RAX,8),%RDX

    (2350) 0x50f204 ADD	%R13,%RDX

    (2350) 0x50f207 LEA	(%RDI,%RDX,8),%RDX

    (2350) 0x50f20b CMP	%R10,(%RDX)

    (2350) 0x50f20e JL	50f310

    (2350) 0x50f214 INC	%RAX

    (2350) 0x50f217 CMP	%RSI,%RAX

    (2350) 0x50f21a JL	50f200

  (2348) 0x50f21c MOV	-0x88(%RBP),%R12

  (2348) 0x50f223 ADD	%R12,%R9

  (2348) 0x50f226 MOV	(%R12,%R14,8),%R14

  (2348) 0x50f22a MOV	(%R9),%RSI

  (2348) 0x50f22d CMP	%RSI,%R14

  (2348) 0x50f230 JGE	50f259

  (2348) 0x50f232 NOPW	%CS:(%RAX,%RAX,1)

  (2348) 0x50f23d NOPL	(%RAX)

    (2349) 0x50f240 MOV	(%R15,%R14,8),%RAX

    (2349) 0x50f244 LEA	(%RDI,%RAX,8),%RDX

    (2349) 0x50f248 CMP	%RBX,(%RDX)

    (2349) 0x50f24b JL	50f330

    (2349) 0x50f251 INC	%R14

    (2349) 0x50f254 CMP	%RSI,%R14

    (2349) 0x50f257 JL	50f240

  (2348) 0x50f259 INCQ	-0x58(%RBP)

  (2348) 0x50f25d MOV	-0x78(%RBP),%R12

  (2348) 0x50f261 MOV	-0x48(%RBP),%R14

  (2348) 0x50f265 MOV	-0x58(%RBP),%R9

  (2348) 0x50f269 CMP	%R9,0x8(%R12,%R14,8)

  (2348) 0x50f26e JG	50f1d0

0x50f274 MOV	-0xd0(%RBP),%R14

0x50f27b JMP	50f0b9

    (2354) 0x50f280 MOV	%RCX,(%RDX)

    (2354) 0x50f283 INC	%RAX

    (2354) 0x50f286 INC	%RCX

    (2354) 0x50f289 MOV	(%R12),%RSI

    (2354) 0x50f28d CMP	%RAX,%RSI

    (2354) 0x50f290 JG	50f100

  (2352) 0x50f296 CMPQ	$0,-0x60(%RBP)

  (2352) 0x50f29b JE	50f124

  (2352) 0x50f2a1 MOV	-0x90(%RBP),%R12

  (2352) 0x50f2a8 ADD	%R12,%R13

  (2352) 0x50f2ab MOV	(%R12,%R15,8),%RAX

  (2352) 0x50f2af MOV	(%R13),%RSI

  (2352) 0x50f2b3 CMP	%RSI,%RAX

  (2352) 0x50f2b6 JGE	50f124

  (2352) 0x50f2bc NOPL	(%RAX)

    (2353) 0x50f2c0 MOV	(%R14,%RAX,8),%RDX

    (2353) 0x50f2c4 MOV	-0x40(%RBP),%R12

    (2353) 0x50f2c8 MOV	-0x38(%RBP),%R15

    (2353) 0x50f2cc ADD	(%R12,%RDX,8),%R15

    (2353) 0x50f2d0 LEA	(%RDI,%R15,8),%RDX

    (2353) 0x50f2d4 CMP	%R10,(%RDX)

    (2353) 0x50f2d7 JL	50f2f0

    (2353) 0x50f2d9 INC	%RAX

    (2353) 0x50f2dc CMP	%RSI,%RAX

    (2353) 0x50f2df JL	50f2c0

  (2352) 0x50f2e1 JMP	50f124

    (2353) 0x50f2f0 MOV	%R8,(%RDX)

    (2353) 0x50f2f3 INC	%RAX

    (2353) 0x50f2f6 INC	%R8

    (2353) 0x50f2f9 MOV	(%R13),%RSI

    (2353) 0x50f2fd CMP	%RAX,%RSI

    (2353) 0x50f300 JG	50f2c0

  (2352) 0x50f302 JMP	50f124

    (2350) 0x50f310 MOV	%R8,(%RDX)

    (2350) 0x50f313 INC	%RAX

    (2350) 0x50f316 INC	%R8

    (2350) 0x50f319 MOV	(%R12),%RSI

    (2350) 0x50f31d CMP	%RAX,%RSI

    (2350) 0x50f320 JG	50f200

  (2348) 0x50f326 JMP	50f21c

    (2349) 0x50f330 MOV	%RCX,(%RDX)

    (2349) 0x50f333 INC	%R14

    (2349) 0x50f336 INC	%RCX

    (2349) 0x50f339 MOV	(%R9),%RSI

    (2349) 0x50f33c CMP	%R14,%RSI

    (2349) 0x50f33f JG	50f240

  (2348) 0x50f345 JMP	50f259

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 127 - 242

--------------------------------------------------------------------------------

127:     for (i1 = ns; i1 < ne; i1++)

[...]

135:       if ( allsquare ) {

[...]

144:       if (num_cols_offd_A)

145:       {

146:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

[...]

154:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

155:             {

156:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

164:                if (B_marker[i3] < jj_row_begin_offd)

165:                {

166:                   B_marker[i3] = jj_count_offd;

167:                   jj_count_offd++;

168:                }

169:             }

170:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

171:             {

172:                i3 = B_ext_diag_j[jj3];

173:

174:                if (B_marker[i3] < jj_row_begin_diag)

175:                {

176:                   B_marker[i3] = jj_count_diag;

177:                   jj_count_diag++;

[...]

187:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

[...]

195:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

[...]

205:             if (B_marker[i3] < jj_row_begin_diag)

206:             {

207:                B_marker[i3] = jj_count_diag;

208:                jj_count_diag++;

[...]

216:          if (num_cols_offd_B)

217:          {

218:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

219:             {

220:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

228:                if (B_marker[i3] < jj_row_begin_offd)

229:                {

230:                   B_marker[i3] = jj_count_offd;

231:                   jj_count_offd++;

[...]

241:       (*C_diag_i)[i1] = jj_row_begin_diag;

242:       (*C_offd_i)[i1] = jj_row_begin_offd;

Coverage (%)	Name	Source Location	Module
○98.65	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.35	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source	par_csr_matop.c:127-127,par_csr_matop.c:135-135,par_csr_matop.c:144-146,par_csr_matop.c:187-187,par_csr_matop.c:241-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.50
CQA cycles if no scalar integer	6.50
CQA cycles if FP arith vectorized	6.50
CQA cycles if fully vectorized	0.81
Front-end cycles	6.50
P0 cycles	2.50
P1 cycles	1.80
P2 cycles	6.33
P3 cycles	6.33
P4 cycles	2.50
P5 cycles	1.60
P6 cycles	2.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	1.60
P11 cycles	6.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	19.00
Nb stores	5.00
Nb stack references	14.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.54
Bytes prefetched	0.00
Bytes loaded	152.00
Bytes stored	40.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source	par_csr_matop.c:127-127,par_csr_matop.c:135-135,par_csr_matop.c:144-146,par_csr_matop.c:187-187,par_csr_matop.c:241-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.50
CQA cycles if no scalar integer	6.50
CQA cycles if FP arith vectorized	6.50
CQA cycles if fully vectorized	0.81
Front-end cycles	6.50
P0 cycles	2.50
P1 cycles	1.80
P2 cycles	6.33
P3 cycles	6.33
P4 cycles	2.50
P5 cycles	1.60
P6 cycles	2.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	1.60
P11 cycles	6.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	19.00
Nb stores	5.00
Nb stack references	14.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.54
Bytes prefetched	0.00
Bytes loaded	152.00
Bytes stored	40.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source file and lines	par_csr_matop.c:127-242
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135,144-146,154-156,164-177,187,195,205-208,216-220,228-231,241-242.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135,144-146,187,241-242.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.50 to 0.81 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 152 bytes. The binary loop is storing 40 bytes.

General properties

nb instructions	37
nb uops	37
loop length	188
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	1.80	6.33	6.33	2.50	1.60	2.50	2.50	2.50	2.50	1.60	6.33
cycles	2.50	1.80	6.33	6.33	2.50	1.60	2.50	2.50	2.50	2.50	1.60	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.50
Dispatch	6.33
Overall L1	6.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.50 cycles. At this rate:

12% of peak load performance is reached (23.38 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.15 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 50f0b9

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
CMPQ $0,-0xb0(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 50f195 <hypre_ParMatmul_RowSizes._omp_fn.0+0x2d5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x50(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xc8(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R13,%R15,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP 0x8(%R13,%R15,8),%R11	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 50f136 <hypre_ParMatmul_RowSizes._omp_fn.0+0x276>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x48(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xb8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,(%R11,%R9,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xc0(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10,(%RBX,%R9,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %R9,-0xa0(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 50f34a <hypre_ParMatmul_RowSizes._omp_fn.0+0x48a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPQ $0,-0xa8(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %R8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 50f0a5 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1e5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x78(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R12,%R9,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP 0x8(%R12,%R9,8),%R11	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JGE 50f0b9 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1f9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x38(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xe0(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xe8(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xd0(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 50f0b9 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1f9>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source file and lines	par_csr_matop.c:127-242
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.50 to 0.81 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 152 bytes. The binary loop is storing 40 bytes.

General properties

nb instructions	37
nb uops	37
loop length	188
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	1.80	6.33	6.33	2.50	1.60	2.50	2.50	2.50	2.50	1.60	6.33
cycles	2.50	1.80	6.33	6.33	2.50	1.60	2.50	2.50	2.50	2.50	1.60	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.50
Dispatch	6.33
Overall L1	6.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.50 cycles. At this rate:

12% of peak load performance is reached (23.38 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.15 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 50f0b9

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
CMPQ $0,-0xb0(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 50f195 <hypre_ParMatmul_RowSizes._omp_fn.0+0x2d5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x50(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xc8(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R13,%R15,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP 0x8(%R13,%R15,8),%R11	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 50f136 <hypre_ParMatmul_RowSizes._omp_fn.0+0x276>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x48(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xb8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,(%R11,%R9,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xc0(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10,(%RBX,%R9,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %R9,-0xa0(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 50f34a <hypre_ParMatmul_RowSizes._omp_fn.0+0x48a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPQ $0,-0xa8(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %R8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 50f0a5 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1e5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x78(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R12,%R9,8),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP 0x8(%R12,%R9,8),%R11	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JGE 50f0b9 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1f9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R14,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x38(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xe0(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xe8(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xd0(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 50f0b9 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1f9>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code