OV - exec - Loop 2050

	Loop Id: 2050	Module: exec	Source: ams.c:3662-3682 [...]	Coverage: 6.38%

0x4ef9e0 INC	%RDX

0x4ef9e3 CMP	%RDX,%RAX

0x4ef9e6 JE	4efd24

0x4ef9ec MOV	(%R12,%RDX,8),%RCX

0x4ef9f0 VMOVSD	(%RSI,%RCX,8),%XMM1

0x4ef9f5 VCOMISD	%XMM1,%XMM2

0x4ef9f9 JE	4ef9e0

0x4ef9fb MOV	-0x40(%RBP),%RBX

0x4ef9ff MOV	0x8(%R12,%RDX,8),%R13

0x4efa04 VMOVSD	(%RBX,%RDX,8),%XMM0

0x4efa09 MOV	%R13,-0x38(%RBP)

0x4efa0d CMP	%R13,%RCX

0x4efa10 JGE	4efb7f

0x4efa16 MOV	%RCX,%RBX

0x4efa19 NOT	%RBX

0x4efa1c ADD	%R13,%RBX

0x4efa1f AND	$0x7,%EBX

0x4efa22 JE	4efd90

0x4efa28 MOV	(%RDI,%RCX,8),%R13

0x4efa2c INC	%RCX

0x4efa2f VFNMADD231SD	(%R8,%R13,8),%XMM1,%XMM0

0x4efa35 VMOVSD	(%RSI,%RCX,8),%XMM1

0x4efa3a CMP	$0x1,%RBX

0x4efa3e JE	4efd80

0x4efa44 CMP	$0x2,%RBX

0x4efa48 JE	4efaae

0x4efa4a CMP	$0x3,%RBX

0x4efa4e JE	4efa9c

0x4efa50 CMP	$0x4,%RBX

0x4efa54 JE	4efa8a

0x4efa56 CMP	$0x5,%RBX

0x4efa5a JE	4efa78

0x4efa5c CMP	$0x6,%RBX

0x4efa60 JNE	4efd48

0x4efa66 MOV	(%RDI,%RCX,8),%R13

0x4efa6a INC	%RCX

0x4efa6d VFNMADD231SD	(%R8,%R13,8),%XMM1,%XMM0

0x4efa73 VMOVSD	(%RSI,%RCX,8),%XMM1

0x4efa78 MOV	(%RDI,%RCX,8),%RBX

0x4efa7c INC	%RCX

0x4efa7f VFNMADD231SD	(%R8,%RBX,8),%XMM1,%XMM0

0x4efa85 VMOVSD	(%RSI,%RCX,8),%XMM1

0x4efa8a MOV	(%RDI,%RCX,8),%R13

0x4efa8e INC	%RCX

0x4efa91 VFNMADD231SD	(%R8,%R13,8),%XMM1,%XMM0

0x4efa97 VMOVSD	(%RSI,%RCX,8),%XMM1

0x4efa9c MOV	(%RDI,%RCX,8),%RBX

0x4efaa0 INC	%RCX

0x4efaa3 VFNMADD231SD	(%R8,%RBX,8),%XMM1,%XMM0

0x4efaa9 VMOVSD	(%RSI,%RCX,8),%XMM1

0x4efaae MOV	(%RDI,%RCX,8),%R13

0x4efab2 INC	%RCX

0x4efab5 VFNMADD231SD	(%R8,%R13,8),%XMM1,%XMM0

0x4efabb MOV	%RAX,-0x50(%RBP)

0x4efabf VMOVSD	(%RSI,%RCX,8),%XMM1

0x4efac4 MOV	-0x38(%RBP),%R13

0x4efac8 MOV	%RDX,%RBX

0x4efacb JMP	4efb61

  (2052) 0x4efad0 MOV	(%RDI,%RDX,8),%RAX

  (2052) 0x4efad4 VMOVSD	(%R8,%RAX,8),%XMM8

  (2052) 0x4efada VFNMADD231SD	(%RSI,%RDX,8),%XMM8,%XMM0

  (2052) 0x4efae0 LEA	0x2(%RCX),%RDX

  (2052) 0x4efae4 MOV	(%RDI,%RDX,8),%RAX

  (2052) 0x4efae8 VMOVSD	(%R8,%RAX,8),%XMM9

  (2052) 0x4efaee VFNMADD231SD	(%RSI,%RDX,8),%XMM9,%XMM0

  (2052) 0x4efaf4 LEA	0x3(%RCX),%RDX

  (2052) 0x4efaf8 MOV	(%RDI,%RDX,8),%RAX

  (2052) 0x4efafc VMOVSD	(%R8,%RAX,8),%XMM10

  (2052) 0x4efb02 VFNMADD231SD	(%RSI,%RDX,8),%XMM10,%XMM0

  (2052) 0x4efb08 LEA	0x4(%RCX),%RDX

  (2052) 0x4efb0c MOV	(%RDI,%RDX,8),%RAX

  (2052) 0x4efb10 VMOVSD	(%R8,%RAX,8),%XMM11

  (2052) 0x4efb16 VFNMADD231SD	(%RSI,%RDX,8),%XMM11,%XMM0

  (2052) 0x4efb1c LEA	0x5(%RCX),%RDX

  (2052) 0x4efb20 MOV	(%RDI,%RDX,8),%RAX

  (2052) 0x4efb24 VMOVSD	(%R8,%RAX,8),%XMM12

  (2052) 0x4efb2a VFNMADD231SD	(%RSI,%RDX,8),%XMM12,%XMM0

  (2052) 0x4efb30 LEA	0x6(%RCX),%RDX

  (2052) 0x4efb34 MOV	(%RDI,%RDX,8),%RAX

  (2052) 0x4efb38 VMOVSD	(%R8,%RAX,8),%XMM13

  (2052) 0x4efb3e VFNMADD231SD	(%RSI,%RDX,8),%XMM13,%XMM0

  (2052) 0x4efb44 LEA	0x7(%RCX),%RDX

  (2052) 0x4efb48 MOV	(%RDI,%RDX,8),%RAX

  (2052) 0x4efb4c ADD	$0x8,%RCX

  (2052) 0x4efb50 VMOVSD	(%R8,%RAX,8),%XMM14

  (2052) 0x4efb56 VMOVSD	(%RSI,%RCX,8),%XMM1

  (2052) 0x4efb5b VFNMADD231SD	(%RSI,%RDX,8),%XMM14,%XMM0

  (2052) 0x4efb61 MOV	(%RDI,%RCX,8),%RAX

  (2052) 0x4efb65 LEA	0x1(%RCX),%RDX

  (2052) 0x4efb69 VFNMADD231SD	(%R8,%RAX,8),%XMM1,%XMM0

  (2052) 0x4efb6f CMP	%R13,%RDX

  (2052) 0x4efb72 JNE	4efad0

0x4efb78 MOV	-0x50(%RBP),%RAX

0x4efb7c MOV	%RBX,%RDX

0x4efb7f MOV	(%R15,%RDX,8),%RCX

0x4efb83 MOV	0x8(%R15,%RDX,8),%RBX

0x4efb88 CMP	%RBX,%RCX

0x4efb8b JGE	4efcff

0x4efb91 MOV	%RBX,%R13

0x4efb94 SUB	%RCX,%R13

0x4efb97 AND	$0x7,%R13D

0x4efb9b JE	4efc48

0x4efba1 CMP	$0x1,%R13

0x4efba5 JE	4efc2c

0x4efbab CMP	$0x2,%R13

0x4efbaf JE	4efc19

0x4efbb1 CMP	$0x3,%R13

0x4efbb5 JE	4efc06

0x4efbb7 CMP	$0x4,%R13

0x4efbbb JE	4efbf3

0x4efbbd CMP	$0x5,%R13

0x4efbc1 JE	4efbe0

0x4efbc3 CMP	$0x6,%R13

0x4efbc7 JNE	4efd60

0x4efbcd MOV	(%R10,%RCX,8),%R13

0x4efbd1 VMOVSD	(%R9,%RCX,8),%XMM5

0x4efbd7 INC	%RCX

0x4efbda VFNMADD231SD	(%R11,%R13,8),%XMM5,%XMM0

0x4efbe0 MOV	(%R10,%RCX,8),%R13

0x4efbe4 VMOVSD	(%R9,%RCX,8),%XMM6

0x4efbea INC	%RCX

0x4efbed VFNMADD231SD	(%R11,%R13,8),%XMM6,%XMM0

0x4efbf3 MOV	(%R10,%RCX,8),%R13

0x4efbf7 VMOVSD	(%R9,%RCX,8),%XMM7

0x4efbfd INC	%RCX

0x4efc00 VFNMADD231SD	(%R11,%R13,8),%XMM7,%XMM0

0x4efc06 MOV	(%R10,%RCX,8),%R13

0x4efc0a VMOVSD	(%R9,%RCX,8),%XMM8

0x4efc10 INC	%RCX

0x4efc13 VFNMADD231SD	(%R11,%R13,8),%XMM8,%XMM0

0x4efc19 MOV	(%R10,%RCX,8),%R13

0x4efc1d VMOVSD	(%R9,%RCX,8),%XMM9

0x4efc23 INC	%RCX

0x4efc26 VFNMADD231SD	(%R11,%R13,8),%XMM9,%XMM0

0x4efc2c MOV	(%R10,%RCX,8),%R13

0x4efc30 VMOVSD	(%R9,%RCX,8),%XMM10

0x4efc36 INC	%RCX

0x4efc39 VFNMADD231SD	(%R11,%R13,8),%XMM10,%XMM0

0x4efc3f CMP	%RBX,%RCX

0x4efc42 JE	4efcff

0x4efc48 MOV	%RAX,-0x38(%RBP)

0x4efc4c MOV	%RDX,%R13

  (2051) 0x4efc4f MOV	(%R10,%RCX,8),%RAX

  (2051) 0x4efc53 VMOVSD	(%R9,%RCX,8),%XMM11

  (2051) 0x4efc59 LEA	0x1(%RCX),%RDX

  (2051) 0x4efc5d VFNMADD231SD	(%R11,%RAX,8),%XMM11,%XMM0

  (2051) 0x4efc63 VMOVSD	(%R9,%RDX,8),%XMM12

  (2051) 0x4efc69 MOV	(%R10,%RDX,8),%RAX

  (2051) 0x4efc6d LEA	0x2(%RCX),%RDX

  (2051) 0x4efc71 VMOVSD	(%R9,%RDX,8),%XMM13

  (2051) 0x4efc77 VFNMADD231SD	(%R11,%RAX,8),%XMM12,%XMM0

  (2051) 0x4efc7d MOV	(%R10,%RDX,8),%RAX

  (2051) 0x4efc81 LEA	0x3(%RCX),%RDX

  (2051) 0x4efc85 VMOVSD	(%R9,%RDX,8),%XMM14

  (2051) 0x4efc8b VFNMADD231SD	(%R11,%RAX,8),%XMM13,%XMM0

  (2051) 0x4efc91 MOV	(%R10,%RDX,8),%RAX

  (2051) 0x4efc95 LEA	0x4(%RCX),%RDX

  (2051) 0x4efc99 VMOVSD	(%R9,%RDX,8),%XMM15

  (2051) 0x4efc9f VFNMADD231SD	(%R11,%RAX,8),%XMM14,%XMM0

  (2051) 0x4efca5 MOV	(%R10,%RDX,8),%RAX

  (2051) 0x4efca9 LEA	0x5(%RCX),%RDX

  (2051) 0x4efcad VMOVSD	(%R9,%RDX,8),%XMM1

  (2051) 0x4efcb3 VFNMADD231SD	(%R11,%RAX,8),%XMM15,%XMM0

  (2051) 0x4efcb9 MOV	(%R10,%RDX,8),%RAX

  (2051) 0x4efcbd LEA	0x6(%RCX),%RDX

  (2051) 0x4efcc1 VMOVSD	(%R9,%RDX,8),%XMM4

  (2051) 0x4efcc7 VFNMADD231SD	(%R11,%RAX,8),%XMM1,%XMM0

  (2051) 0x4efccd MOV	(%R10,%RDX,8),%RAX

  (2051) 0x4efcd1 LEA	0x7(%RCX),%RDX

  (2051) 0x4efcd5 VMOVSD	(%R9,%RDX,8),%XMM5

  (2051) 0x4efcdb ADD	$0x8,%RCX

  (2051) 0x4efcdf VFNMADD231SD	(%R11,%RAX,8),%XMM4,%XMM0

  (2051) 0x4efce5 MOV	(%R10,%RDX,8),%RAX

  (2051) 0x4efce9 VFNMADD231SD	(%R11,%RAX,8),%XMM5,%XMM0

  (2051) 0x4efcef CMP	%RBX,%RCX

  (2051) 0x4efcf2 JNE	4efc4f

0x4efcf8 MOV	-0x38(%RBP),%RAX

0x4efcfc MOV	%R13,%RDX

0x4efcff VMULSD	%XMM0,%XMM3,%XMM0

0x4efd03 MOV	-0x48(%RBP),%RCX

0x4efd07 VDIVSD	(%RCX,%RDX,8),%XMM0,%XMM6

0x4efd0c VADDSD	(%R14,%RDX,8),%XMM6,%XMM7

0x4efd12 VMOVSD	%XMM7,(%R14,%RDX,8)

0x4efd18 INC	%RDX

0x4efd1b CMP	%RDX,%RAX

0x4efd1e JNE	4ef9ec

0x4efd48 MOV	(%RDI,%RCX,8),%RBX

0x4efd4c INC	%RCX

0x4efd4f VFNMADD231SD	(%R8,%RBX,8),%XMM1,%XMM0

0x4efd55 VMOVSD	(%RSI,%RCX,8),%XMM1

0x4efd5a JMP	4efa66

0x4efd60 MOV	(%R10,%RCX,8),%R13

0x4efd64 VMOVSD	(%R9,%RCX,8),%XMM4

0x4efd6a INC	%RCX

0x4efd6d VFNMADD231SD	(%R11,%R13,8),%XMM4,%XMM0

0x4efd73 JMP	4efbcd

0x4efd80 MOV	%RAX,-0x50(%RBP)

0x4efd84 MOV	-0x38(%RBP),%R13

0x4efd88 MOV	%RDX,%RBX

0x4efd8b JMP	4efb61

0x4efd90 MOV	%RAX,-0x50(%RBP)

0x4efd94 MOV	%RDX,%RBX

0x4efd97 JMP	4efb61

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682

--------------------------------------------------------------------------------

3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE

[...]

3669:          if (A_diag_data[A_diag_i[i]] != zero)

3670:          {

3671:             res = f_data[i];

3672:             for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++)

3673:             {

3674:                ii = A_diag_j[jj];

3675:                res -= A_diag_data[jj] * Vtemp_data[ii];

3676:             }

3677:             for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

3678:             {

3679:                ii = A_offd_j[jj];

3680:                res -= A_offd_data[jj] * Vext_data[ii];

3681:             }

3682:             u_data[i] += (relax_weight*res)/l1_norms[i];

Coverage (%)	Name	Source Location	Module
○97.60	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.40	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.72
CQA speedup if FP arith vectorized	2.05
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source	ams.c:3662-3662,ams.c:3669-3672,ams.c:3675-3677,ams.c:3680-3682
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.17
CQA cycles if no scalar integer	14.67
CQA cycles if FP arith vectorized	12.25
CQA cycles if fully vectorized	3.15
Front-end cycles	25.17
P0 cycles	13.00
P1 cycles	12.50
P2 cycles	18.67
P3 cycles	18.67
P4 cycles	3.00
P5 cycles	11.60
P6 cycles	11.50
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	11.40
P11 cycles	18.67
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	135.00
Nb uops	135.00
Nb loads	56.00
Nb stores	6.00
Nb stack references	4.00
FLOP/cycle	1.23
Nb FLOP add-sub	1.00
Nb FLOP mul	1.00
Nb FLOP fma	14.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.71
Bytes prefetched	0.00
Bytes loaded	448.00
Bytes stored	48.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.72
CQA speedup if FP arith vectorized	2.05
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source	ams.c:3662-3662,ams.c:3669-3672,ams.c:3675-3677,ams.c:3680-3682
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.17
CQA cycles if no scalar integer	14.67
CQA cycles if FP arith vectorized	12.25
CQA cycles if fully vectorized	3.15
Front-end cycles	25.17
P0 cycles	13.00
P1 cycles	12.50
P2 cycles	18.67
P3 cycles	18.67
P4 cycles	3.00
P5 cycles	11.60
P6 cycles	11.50
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	11.40
P11 cycles	18.67
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	135.00
Nb uops	135.00
Nb loads	56.00
Nb stores	6.00
Nb stack references	4.00
FLOP/cycle	1.23
Nb FLOP add-sub	1.00
Nb FLOP mul	1.00
Nb FLOP fma	14.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.71
Bytes prefetched	0.00
Bytes loaded	448.00
Bytes stored	48.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source file and lines	ams.c:3662-3682
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3682.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3672,3675-3677,3680-3682.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 153 paths individually, rerun with max-paths=153
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 153 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.17 to 14.67 cycles (1.72x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 25.17 to 3.15 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 14 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Type of elements and instruction set

18 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 31 FP arithmetical operations:

15: addition or subtraction (14 inside FMA instructions)
15: multiply (14 inside FMA instructions)
1: divide

The binary loop is loading 448 bytes (56 double precision FP elements). The binary loop is storing 48 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	135
nb uops	135
loop length	574
used x86 registers	15
used mmx registers	0
used xmm registers	11
used ymm registers	0
used zmm registers	0
nb stack references	4
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.17 cycles
front end	25.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.00	12.50	18.67	18.67	3.00	11.60	11.50	3.00	3.00	3.00	11.40	18.67
cycles	13.00	12.50	18.67	18.67	3.00	11.60	11.50	3.00	3.00	3.00	11.40	18.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	25.17
Dispatch	18.67
DIV/SQRT	4.00
Overall L1	25.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	12%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.17 cycles. At this rate:

9% of peak load performance is reached (17.80 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.91 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 25.17 to 18.67 cycles (1.35x speedup).

ASM code

In the binary file, the address of the loop is: 4ef9ec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efd24 <hypre_ParCSRRelaxThreads._omp_fn.1+0x3e4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R12,%RDX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RSI,%RCX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD %XMM1,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JE 4ef9e0 <hypre_ParCSRRelaxThreads._omp_fn.1+0xa0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x40(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R12,%RDX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RBX,%RDX,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R13,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %R13,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4efb7f <hypre_ParCSRRelaxThreads._omp_fn.1+0x23f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOT %RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R13,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4efd90 <hypre_ParCSRRelaxThreads._omp_fn.1+0x450>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%RDI,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R8,%R13,8),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RSI,%RCX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP $0x1,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efd80 <hypre_ParCSRRelaxThreads._omp_fn.1+0x440>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efaae <hypre_ParCSRRelaxThreads._omp_fn.1+0x16e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efa9c <hypre_ParCSRRelaxThreads._omp_fn.1+0x15c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efa8a <hypre_ParCSRRelaxThreads._omp_fn.1+0x14a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efa78 <hypre_ParCSRRelaxThreads._omp_fn.1+0x138>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4efd48 <hypre_ParCSRRelaxThreads._omp_fn.1+0x408>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%RDI,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R8,%R13,8),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RSI,%RCX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RDI,%RCX,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R8,%RBX,8),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RSI,%RCX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RDI,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R8,%R13,8),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RSI,%RCX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RDI,%RCX,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R8,%RBX,8),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RSI,%RCX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RDI,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R8,%R13,8),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RSI,%RCX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x38(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4efb61 <hypre_ParCSRRelaxThreads._omp_fn.1+0x221>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R15,%RDX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R15,%RDX,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RBX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4efcff <hypre_ParCSRRelaxThreads._omp_fn.1+0x3bf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RCX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4efc48 <hypre_ParCSRRelaxThreads._omp_fn.1+0x308>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efc2c <hypre_ParCSRRelaxThreads._omp_fn.1+0x2ec>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efc19 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2d9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efc06 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2c6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efbf3 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2b3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efbe0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4efd60 <hypre_ParCSRRelaxThreads._omp_fn.1+0x420>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R10,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R9,%RCX,8),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R11,%R13,8),%XMM5,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R10,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R9,%RCX,8),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R11,%R13,8),%XMM6,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R10,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R9,%RCX,8),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R11,%R13,8),%XMM7,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R10,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R9,%RCX,8),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R11,%R13,8),%XMM8,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R10,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R9,%RCX,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R11,%R13,8),%XMM9,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R10,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R9,%RCX,8),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R11,%R13,8),%XMM10,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
CMP %RBX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efcff <hypre_ParCSRRelaxThreads._omp_fn.1+0x3bf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R13,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD %XMM0,%XMM3,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x48(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VDIVSD (%RCX,%RDX,8),%XMM0,%XMM6	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VADDSD (%R14,%RDX,8),%XMM6,%XMM7	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM7,(%R14,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4ef9ec <hypre_ParCSRRelaxThreads._omp_fn.1+0xac>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%RDI,%RCX,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R8,%RBX,8),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RSI,%RCX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 4efa66 <hypre_ParCSRRelaxThreads._omp_fn.1+0x126>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV (%R10,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R9,%RCX,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R11,%R13,8),%XMM4,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
JMP 4efbcd <hypre_ParCSRRelaxThreads._omp_fn.1+0x28d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x38(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4efb61 <hypre_ParCSRRelaxThreads._omp_fn.1+0x221>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4efb61 <hypre_ParCSRRelaxThreads._omp_fn.1+0x221>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_ParCSRRelaxThreads._omp_fn.1
Source file and lines	ams.c:3662-3682
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 153 paths individually, rerun with max-paths=153
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 25.17 to 3.15 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 14 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Type of elements and instruction set

18 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 31 FP arithmetical operations:

15: addition or subtraction (14 inside FMA instructions)
15: multiply (14 inside FMA instructions)
1: divide

The binary loop is loading 448 bytes (56 double precision FP elements). The binary loop is storing 48 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	135
nb uops	135
loop length	574
used x86 registers	15
used mmx registers	0
used xmm registers	11
used ymm registers	0
used zmm registers	0
nb stack references	4
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.17 cycles
front end	25.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.00	12.50	18.67	18.67	3.00	11.60	11.50	3.00	3.00	3.00	11.40	18.67
cycles	13.00	12.50	18.67	18.67	3.00	11.60	11.50	3.00	3.00	3.00	11.40	18.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	25.17
Dispatch	18.67
DIV/SQRT	4.00
Overall L1	25.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	12%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.17 cycles. At this rate:

9% of peak load performance is reached (17.80 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.91 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4ef9ec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efd24 <hypre_ParCSRRelaxThreads._omp_fn.1+0x3e4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R12,%RDX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RSI,%RCX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD %XMM1,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JE 4ef9e0 <hypre_ParCSRRelaxThreads._omp_fn.1+0xa0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x40(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R12,%RDX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%RBX,%RDX,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R13,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %R13,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4efb7f <hypre_ParCSRRelaxThreads._omp_fn.1+0x23f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOT %RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R13,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4efd90 <hypre_ParCSRRelaxThreads._omp_fn.1+0x450>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%RDI,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R8,%R13,8),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RSI,%RCX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP $0x1,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efd80 <hypre_ParCSRRelaxThreads._omp_fn.1+0x440>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efaae <hypre_ParCSRRelaxThreads._omp_fn.1+0x16e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efa9c <hypre_ParCSRRelaxThreads._omp_fn.1+0x15c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efa8a <hypre_ParCSRRelaxThreads._omp_fn.1+0x14a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efa78 <hypre_ParCSRRelaxThreads._omp_fn.1+0x138>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4efd48 <hypre_ParCSRRelaxThreads._omp_fn.1+0x408>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%RDI,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R8,%R13,8),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RSI,%RCX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RDI,%RCX,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R8,%RBX,8),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RSI,%RCX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RDI,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R8,%R13,8),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RSI,%RCX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RDI,%RCX,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R8,%RBX,8),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RSI,%RCX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RDI,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R8,%R13,8),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RSI,%RCX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x38(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4efb61 <hypre_ParCSRRelaxThreads._omp_fn.1+0x221>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R15,%RDX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R15,%RDX,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RBX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4efcff <hypre_ParCSRRelaxThreads._omp_fn.1+0x3bf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RBX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RCX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND $0x7,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4efc48 <hypre_ParCSRRelaxThreads._omp_fn.1+0x308>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efc2c <hypre_ParCSRRelaxThreads._omp_fn.1+0x2ec>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efc19 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2d9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efc06 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2c6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efbf3 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2b3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efbe0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x2a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4efd60 <hypre_ParCSRRelaxThreads._omp_fn.1+0x420>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%R10,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R9,%RCX,8),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R11,%R13,8),%XMM5,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R10,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R9,%RCX,8),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R11,%R13,8),%XMM6,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R10,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R9,%RCX,8),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R11,%R13,8),%XMM7,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R10,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R9,%RCX,8),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R11,%R13,8),%XMM8,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R10,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R9,%RCX,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R11,%R13,8),%XMM9,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
MOV (%R10,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R9,%RCX,8),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R11,%R13,8),%XMM10,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
CMP %RBX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4efcff <hypre_ParCSRRelaxThreads._omp_fn.1+0x3bf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R13,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD %XMM0,%XMM3,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x48(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VDIVSD (%RCX,%RDX,8),%XMM0,%XMM6	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4	scal (12.5%)
VADDSD (%R14,%RDX,8),%XMM6,%XMM7	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM7,(%R14,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4ef9ec <hypre_ParCSRRelaxThreads._omp_fn.1+0xac>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%RDI,%RCX,8),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R8,%RBX,8),%XMM1,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
VMOVSD (%RSI,%RCX,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 4efa66 <hypre_ParCSRRelaxThreads._omp_fn.1+0x126>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV (%R10,%RCX,8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R9,%RCX,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VFNMADD231SD (%R11,%R13,8),%XMM4,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
JMP 4efbcd <hypre_ParCSRRelaxThreads._omp_fn.1+0x28d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x38(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4efb61 <hypre_ParCSRRelaxThreads._omp_fn.1+0x221>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4efb61 <hypre_ParCSRRelaxThreads._omp_fn.1+0x221>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code