OV - exec - Loop 2024

	Loop Id: 2024	Module: exec	Source: ams.c:3382-3401 [...]	Coverage: 0.02%

0x4ed860 CMP	%RDI,%RAX

0x4ed863 JGE	4edbb4

0x4ed869 LEA	(%R13,%RDI,8),%RSI

0x4ed86e LEA	(%R13,%RAX,8),%R10

0x4ed873 MOV	%RSI,%RAX

0x4ed876 SUB	%R10,%RAX

0x4ed879 SUB	$0x8,%RAX

0x4ed87d SHR	$0x3,%RAX

0x4ed881 INC	%RAX

0x4ed884 VXORPD	%XMM0,%XMM0,%XMM0

0x4ed888 AND	$0x7,%EAX

0x4ed88b JE	4ed959

0x4ed891 CMP	$0x1,%RAX

0x4ed895 JE	4ed93a

0x4ed89b CMP	$0x2,%RAX

0x4ed89f JE	4ed925

0x4ed8a5 CMP	$0x3,%RAX

0x4ed8a9 JE	4ed90f

0x4ed8ab CMP	$0x4,%RAX

0x4ed8af JE	4ed8f9

0x4ed8b1 CMP	$0x5,%RAX

0x4ed8b5 JE	4ed8e4

0x4ed8b7 CMP	$0x6,%RAX

0x4ed8bb JE	4ed8ce

0x4ed8bd VMOVSD	(%R10),%XMM8

0x4ed8c2 ADD	$0x8,%R10

0x4ed8c6 VANDPD	%XMM6,%XMM8,%XMM0

0x4ed8ca VMOVSD	%XMM0,(%RCX)

0x4ed8ce VMOVSD	(%R10),%XMM9

0x4ed8d3 ADD	$0x8,%R10

0x4ed8d7 VANDPD	%XMM6,%XMM9,%XMM10

0x4ed8db VADDSD	%XMM10,%XMM0,%XMM0

0x4ed8e0 VMOVSD	%XMM0,(%RCX)

0x4ed8e4 VMOVSD	(%R10),%XMM2

0x4ed8e9 ADD	$0x8,%R10

0x4ed8ed VANDPD	%XMM6,%XMM2,%XMM1

0x4ed8f1 VADDSD	%XMM1,%XMM0,%XMM0

0x4ed8f5 VMOVSD	%XMM0,(%RCX)

0x4ed8f9 VMOVSD	(%R10),%XMM14

0x4ed8fe ADD	$0x8,%R10

0x4ed902 VANDPD	%XMM6,%XMM14,%XMM11

0x4ed906 VADDSD	%XMM11,%XMM0,%XMM0

0x4ed90b VMOVSD	%XMM0,(%RCX)

0x4ed90f VMOVSD	(%R10),%XMM13

0x4ed914 ADD	$0x8,%R10

0x4ed918 VANDPD	%XMM6,%XMM13,%XMM15

0x4ed91c VADDSD	%XMM15,%XMM0,%XMM0

0x4ed921 VMOVSD	%XMM0,(%RCX)

0x4ed925 VMOVSD	(%R10),%XMM5

0x4ed92a ADD	$0x8,%R10

0x4ed92e VANDPD	%XMM6,%XMM5,%XMM4

0x4ed932 VADDSD	%XMM4,%XMM0,%XMM0

0x4ed936 VMOVSD	%XMM0,(%RCX)

0x4ed93a VMOVSD	(%R10),%XMM8

0x4ed93f ADD	$0x8,%R10

0x4ed943 VANDPD	%XMM6,%XMM8,%XMM9

0x4ed947 VADDSD	%XMM9,%XMM0,%XMM0

0x4ed94c VMOVSD	%XMM0,(%RCX)

0x4ed950 CMP	%RSI,%R10

0x4ed953 JE	4ed9f9

  (2026) 0x4ed959 VMOVSD	(%R10),%XMM10

  (2026) 0x4ed95e ADD	$0x40,%R10

  (2026) 0x4ed962 VANDPD	%XMM6,%XMM10,%XMM2

  (2026) 0x4ed966 VADDSD	%XMM2,%XMM0,%XMM1

  (2026) 0x4ed96a VMOVSD	%XMM1,(%RCX)

  (2026) 0x4ed96e VMOVSD	-0x38(%R10),%XMM14

  (2026) 0x4ed974 VANDPD	%XMM6,%XMM14,%XMM11

  (2026) 0x4ed978 VADDSD	%XMM11,%XMM1,%XMM13

  (2026) 0x4ed97d VMOVSD	%XMM13,(%RCX)

  (2026) 0x4ed981 VMOVSD	-0x30(%R10),%XMM15

  (2026) 0x4ed987 VANDPD	%XMM6,%XMM15,%XMM5

  (2026) 0x4ed98b VADDSD	%XMM5,%XMM13,%XMM4

  (2026) 0x4ed98f VMOVSD	%XMM4,(%RCX)

  (2026) 0x4ed993 VMOVSD	-0x28(%R10),%XMM8

  (2026) 0x4ed999 VANDPD	%XMM6,%XMM8,%XMM9

  (2026) 0x4ed99d VADDSD	%XMM9,%XMM4,%XMM0

  (2026) 0x4ed9a2 VMOVSD	%XMM0,(%RCX)

  (2026) 0x4ed9a6 VMOVSD	-0x20(%R10),%XMM10

  (2026) 0x4ed9ac VANDPD	%XMM6,%XMM10,%XMM2

  (2026) 0x4ed9b0 VADDSD	%XMM2,%XMM0,%XMM1

  (2026) 0x4ed9b4 VMOVSD	%XMM1,(%RCX)

  (2026) 0x4ed9b8 VMOVSD	-0x18(%R10),%XMM14

  (2026) 0x4ed9be VANDPD	%XMM6,%XMM14,%XMM11

  (2026) 0x4ed9c2 VADDSD	%XMM11,%XMM1,%XMM13

  (2026) 0x4ed9c7 VMOVSD	%XMM13,(%RCX)

  (2026) 0x4ed9cb VMOVSD	-0x10(%R10),%XMM15

  (2026) 0x4ed9d1 VANDPD	%XMM6,%XMM15,%XMM5

  (2026) 0x4ed9d5 VADDSD	%XMM5,%XMM13,%XMM4

  (2026) 0x4ed9d9 VMOVSD	%XMM4,(%RCX)

  (2026) 0x4ed9dd VMOVSD	-0x8(%R10),%XMM8

  (2026) 0x4ed9e3 VANDPD	%XMM6,%XMM8,%XMM9

  (2026) 0x4ed9e7 VADDSD	%XMM9,%XMM4,%XMM0

  (2026) 0x4ed9ec VMOVSD	%XMM0,(%RCX)

  (2026) 0x4ed9f0 CMP	%RSI,%R10

  (2026) 0x4ed9f3 JNE	4ed959

0x4ed9f9 CMPQ	$0,-0x40(%RBP)

0x4ed9fe JNE	4eda28

0x4eda00 INC	%R8

0x4eda03 ADD	$0x8,%RCX

0x4eda07 CMP	%R9,%R8

0x4eda0a JE	4e94f3

0x4eda10 MOVQ	$0,(%RCX)

0x4eda17 MOV	(%R12,%R8,8),%RAX

0x4eda1b MOV	0x8(%R12,%R8,8),%RDI

0x4eda20 MOV	%R8,%RDX

0x4eda23 JMP	4ed860

0x4eda28 MOV	-0x90(%RBP),%RDI

0x4eda2f MOV	(%RDI,%RDX,8),%R10

0x4eda33 MOV	0x8(%RDI,%RDX,8),%RDX

0x4eda38 CMP	%RDX,%R10

0x4eda3b JGE	4eda00

0x4eda3d MOV	-0x60(%RBP),%RSI

0x4eda41 LEA	(%RSI,%RDX,8),%RDI

0x4eda45 LEA	(%RSI,%R10,8),%RAX

0x4eda49 MOV	%RDI,%R10

0x4eda4c SUB	%RAX,%R10

0x4eda4f SUB	$0x8,%R10

0x4eda53 SHR	$0x3,%R10

0x4eda57 INC	%R10

0x4eda5a AND	$0x7,%R10D

0x4eda5e JE	4edb15

0x4eda64 CMP	$0x1,%R10

0x4eda68 JE	4edaf8

0x4eda6e CMP	$0x2,%R10

0x4eda72 JE	4edae3

0x4eda74 CMP	$0x3,%R10

0x4eda78 JE	4edace

0x4eda7a CMP	$0x4,%R10

0x4eda7e JE	4edaba

0x4eda80 CMP	$0x5,%R10

0x4eda84 JE	4edaa5

0x4eda86 CMP	$0x6,%R10

0x4eda8a JNE	4ee027

0x4eda90 VMOVSD	(%RAX),%XMM1

0x4eda94 ADD	$0x8,%RAX

0x4eda98 VANDPD	%XMM7,%XMM1,%XMM14

0x4eda9c VADDSD	%XMM14,%XMM0,%XMM0

0x4edaa1 VMOVSD	%XMM0,(%RCX)

0x4edaa5 VMOVSD	(%RAX),%XMM11

0x4edaa9 ADD	$0x8,%RAX

0x4edaad VANDPD	%XMM7,%XMM11,%XMM13

0x4edab1 VADDSD	%XMM13,%XMM0,%XMM0

0x4edab6 VMOVSD	%XMM0,(%RCX)

0x4edaba VMOVSD	(%RAX),%XMM15

0x4edabe ADD	$0x8,%RAX

0x4edac2 VANDPD	%XMM7,%XMM15,%XMM5

0x4edac6 VADDSD	%XMM5,%XMM0,%XMM0

0x4edaca VMOVSD	%XMM0,(%RCX)

0x4edace VMOVSD	(%RAX),%XMM4

0x4edad2 ADD	$0x8,%RAX

0x4edad6 VANDPD	%XMM7,%XMM4,%XMM8

0x4edada VADDSD	%XMM8,%XMM0,%XMM0

0x4edadf VMOVSD	%XMM0,(%RCX)

0x4edae3 VMOVSD	(%RAX),%XMM9

0x4edae7 ADD	$0x8,%RAX

0x4edaeb VANDPD	%XMM7,%XMM9,%XMM10

0x4edaef VADDSD	%XMM10,%XMM0,%XMM0

0x4edaf4 VMOVSD	%XMM0,(%RCX)

0x4edaf8 VMOVSD	(%RAX),%XMM2

0x4edafc ADD	$0x8,%RAX

0x4edb00 VANDPD	%XMM7,%XMM2,%XMM1

0x4edb04 VADDSD	%XMM1,%XMM0,%XMM0

0x4edb08 VMOVSD	%XMM0,(%RCX)

0x4edb0c CMP	%RDI,%RAX

0x4edb0f JE	4eda00

  (2025) 0x4edb15 VMOVSD	(%RAX),%XMM14

  (2025) 0x4edb19 ADD	$0x40,%RAX

  (2025) 0x4edb1d VANDPD	%XMM7,%XMM14,%XMM11

  (2025) 0x4edb21 VADDSD	%XMM11,%XMM0,%XMM0

  (2025) 0x4edb26 VMOVSD	%XMM0,(%RCX)

  (2025) 0x4edb2a VMOVSD	-0x38(%RAX),%XMM13

  (2025) 0x4edb2f VANDPD	%XMM7,%XMM13,%XMM15

  (2025) 0x4edb33 VADDSD	%XMM15,%XMM0,%XMM5

  (2025) 0x4edb38 VMOVSD	%XMM5,(%RCX)

  (2025) 0x4edb3c VMOVSD	-0x30(%RAX),%XMM4

  (2025) 0x4edb41 VANDPD	%XMM7,%XMM4,%XMM8

  (2025) 0x4edb45 VADDSD	%XMM8,%XMM5,%XMM9

  (2025) 0x4edb4a VMOVSD	%XMM9,(%RCX)

  (2025) 0x4edb4e VMOVSD	-0x28(%RAX),%XMM10

  (2025) 0x4edb53 VANDPD	%XMM7,%XMM10,%XMM2

  (2025) 0x4edb57 VADDSD	%XMM2,%XMM9,%XMM1

  (2025) 0x4edb5b VMOVSD	%XMM1,(%RCX)

  (2025) 0x4edb5f VMOVSD	-0x20(%RAX),%XMM14

  (2025) 0x4edb64 VANDPD	%XMM7,%XMM14,%XMM11

  (2025) 0x4edb68 VADDSD	%XMM11,%XMM1,%XMM0

  (2025) 0x4edb6d VMOVSD	%XMM0,(%RCX)

  (2025) 0x4edb71 VMOVSD	-0x18(%RAX),%XMM13

  (2025) 0x4edb76 VANDPD	%XMM7,%XMM13,%XMM15

  (2025) 0x4edb7a VADDSD	%XMM15,%XMM0,%XMM5

  (2025) 0x4edb7f VMOVSD	%XMM5,(%RCX)

  (2025) 0x4edb83 VMOVSD	-0x10(%RAX),%XMM4

  (2025) 0x4edb88 VANDPD	%XMM7,%XMM4,%XMM8

  (2025) 0x4edb8c VADDSD	%XMM8,%XMM5,%XMM9

  (2025) 0x4edb91 VMOVSD	%XMM9,(%RCX)

  (2025) 0x4edb95 VMOVSD	-0x8(%RAX),%XMM10

  (2025) 0x4edb9a VANDPD	%XMM7,%XMM10,%XMM2

  (2025) 0x4edb9e VADDSD	%XMM2,%XMM9,%XMM0

  (2025) 0x4edba2 VMOVSD	%XMM0,(%RCX)

  (2025) 0x4edba6 CMP	%RDI,%RAX

  (2025) 0x4edba9 JNE	4edb15

0x4edbaf JMP	4eda00

0x4edbb4 VXORPD	%XMM0,%XMM0,%XMM0

0x4edbb8 JMP	4ed9f9

0x4ee027 VMOVSD	(%RAX),%XMM10

0x4ee02b ADD	$0x8,%RAX

0x4ee02f VANDPD	%XMM7,%XMM10,%XMM2

0x4ee033 VADDSD	%XMM2,%XMM0,%XMM0

0x4ee037 VMOVSD	%XMM0,(%RCX)

0x4ee03b JMP	4eda90

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3382 - 3401

--------------------------------------------------------------------------------

3382:          for (i = ns; i < ne; i++)

3383:          {

3384:             l1_norm[i] = 0.0;

3385:             if (cf_marker == NULL)

3386:             {

3387:                /* Add the l1 norm of the diag part of the ith row */

3388:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3389:                   l1_norm[i] += fabs(A_diag_data[j]);

3390:                /* Add the l1 norm of the offd part of the ith row */

3391:                if (num_cols_offd)

3392:                {

3393:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3394:                      l1_norm[i] += fabs(A_offd_data[j]);

[...]

3401:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

Coverage (%)	Name	Source Location	Module
○95.33	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○4.67	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.53
CQA speedup if FP arith vectorized	2.38
CQA speedup if fully vectorized	11.23
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.62
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source	ams.c:3382-3384,ams.c:3388-3394,ams.c:3401-3401
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	23.17
CQA cycles if no scalar integer	15.17
CQA cycles if FP arith vectorized	9.75
CQA cycles if fully vectorized	2.06
Front-end cycles	23.17
P0 cycles	14.27
P1 cycles	14.23
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	7.50
P5 cycles	14.10
P6 cycles	14.20
P7 cycles	7.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	14.20
P11 cycles	7.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	139.00
Nb uops	139.00
Nb loads	21.00
Nb stores	15.00
Nb stack references	3.00
FLOP/cycle	0.56
Nb FLOP add-sub	13.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.43
Bytes prefetched	0.00
Bytes loaded	168.00
Bytes stored	120.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	21.05
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	47.06
Vector-efficiency ratio all	15.05
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.08
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.38

Metric	Value
CQA speedup if no scalar integer	1.53
CQA speedup if FP arith vectorized	2.38
CQA speedup if fully vectorized	11.23
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.62
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source	ams.c:3382-3384,ams.c:3388-3394,ams.c:3401-3401
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	23.17
CQA cycles if no scalar integer	15.17
CQA cycles if FP arith vectorized	9.75
CQA cycles if fully vectorized	2.06
Front-end cycles	23.17
P0 cycles	14.27
P1 cycles	14.23
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	7.50
P5 cycles	14.10
P6 cycles	14.20
P7 cycles	7.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	14.20
P11 cycles	7.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	139.00
Nb uops	139.00
Nb loads	21.00
Nb stores	15.00
Nb stack references	3.00
FLOP/cycle	0.56
Nb FLOP add-sub	13.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.43
Bytes prefetched	0.00
Bytes loaded	168.00
Bytes stored	120.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	21.05
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	47.06
Vector-efficiency ratio all	15.05
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.08
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.38

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source file and lines	ams.c:3382-3401
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3382-3394,3401.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3382-3384,3388-3394,3401.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 272 paths individually, rerun with max-paths=272
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 272 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.17 to 15.17 cycles (1.53x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 23.17 to 2.06 cycles (11.23x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

13 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 13 FP arithmetical operations:

13: addition or subtraction

The binary loop is loading 168 bytes (21 double precision FP elements). The binary loop is storing 120 bytes (15 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	139
nb uops	139
loop length	572
used x86 registers	11
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.17 cycles
front end	23.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.27	14.23	7.00	7.00	7.50	14.10	14.20	7.50	7.50	7.50	14.20	7.00
cycles	14.27	14.23	7.00	7.00	7.50	14.10	14.20	7.50	7.50	7.50	14.20	7.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.17
Dispatch	14.27
Overall L1	23.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	28%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	21%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	47%

Vector efficiency ratios

INT

all	12%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	16%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.17 cycles. At this rate:

3% of peak load performance is reached (7.25 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.18 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 23.17 to 14.27 cycles (1.62x speedup).

ASM code

In the binary file, the address of the loop is: 4ed860

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
CMP %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4edbb4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4834>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R13,%RDI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R13,%RAX,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
AND $0x7,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4ed959 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x45d9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ed93a <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x45ba>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ed925 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x45a5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ed90f <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x458f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ed8f9 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4579>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ed8e4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4564>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ed8ce <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x454e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R10),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM6,%XMM8,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM6,%XMM9,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM10,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM6,%XMM2,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM6,%XMM14,%XMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM11,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM6,%XMM13,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM15,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM6,%XMM5,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM4,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM6,%XMM8,%XMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM9,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RSI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ed9f9 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4679>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPQ $0,-0x40(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 4eda28 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x46a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e94f3 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x173>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%R12,%R8,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R12,%R8,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4ed860 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x44e0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x90(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI,%RDX,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDI,%RDX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4eda00 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4680>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x60(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RDX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RSI,%R10,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4edb15 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4795>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edaf8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4778>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edae3 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4763>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edace <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x474e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edaba <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x473a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edaa5 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4725>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4ee027 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4ca7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RAX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM1,%XMM14	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM14,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM11,%XMM13	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM13,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM15,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM5,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM4,%XMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM8,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM9,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM10,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM2,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4eda00 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4680>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4eda00 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4680>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 4ed9f9 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4679>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVSD (%RAX),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM10,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM2,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 4eda90 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4710>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source file and lines	ams.c:3382-3401
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 272 paths individually, rerun with max-paths=272
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

13 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 13 FP arithmetical operations:

13: addition or subtraction

The binary loop is loading 168 bytes (21 double precision FP elements). The binary loop is storing 120 bytes (15 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	139
nb uops	139
loop length	572
used x86 registers	11
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.17 cycles
front end	23.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.27	14.23	7.00	7.00	7.50	14.10	14.20	7.50	7.50	7.50	14.20	7.00
cycles	14.27	14.23	7.00	7.00	7.50	14.10	14.20	7.50	7.50	7.50	14.20	7.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.17
Dispatch	14.27
Overall L1	23.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	28%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	21%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	47%

Vector efficiency ratios

INT

all	12%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	16%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.17 cycles. At this rate:

3% of peak load performance is reached (7.25 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.18 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4ed860

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
CMP %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4edbb4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4834>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R13,%RDI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R13,%RAX,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
AND $0x7,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4ed959 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x45d9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ed93a <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x45ba>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ed925 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x45a5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ed90f <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x458f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ed8f9 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4579>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ed8e4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4564>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ed8ce <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x454e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R10),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM6,%XMM8,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM6,%XMM9,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM10,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM6,%XMM2,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM6,%XMM14,%XMM11	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM11,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM6,%XMM13,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM15,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM6,%XMM5,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM4,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM6,%XMM8,%XMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM9,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RSI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ed9f9 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4679>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPQ $0,-0x40(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 4eda28 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x46a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e94f3 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x173>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%R12,%R8,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R12,%R8,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4ed860 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x44e0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x90(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI,%RDX,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDI,%RDX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4eda00 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4680>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x60(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RDX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RSI,%R10,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4edb15 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4795>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edaf8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4778>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edae3 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4763>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edace <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x474e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edaba <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x473a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edaa5 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4725>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4ee027 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4ca7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RAX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM1,%XMM14	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM14,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM11,%XMM13	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM13,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM15,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM5,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM4,%XMM8	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM8,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM9,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM10,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM2,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4eda00 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4680>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4eda00 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4680>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 4ed9f9 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4679>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVSD (%RAX),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM10,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM2,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 4eda90 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4710>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code