OV - exec - Loop 1996

	Loop Id: 1996	Module: exec	Source: ams.c:3382-3401 [...]	Coverage: 0.01%

0x4edbd0 CMP	%RAX,%RDI

0x4edbd3 JLE	4edf3e

0x4edbd9 LEA	(%R13,%RDI,8),%RSI

0x4edbde LEA	(%R13,%RAX,8),%R10

0x4edbe3 MOV	%RSI,%RAX

0x4edbe6 SUB	%R10,%RAX

0x4edbe9 SUB	$0x8,%RAX

0x4edbed SHR	$0x3,%RAX

0x4edbf1 INC	%RAX

0x4edbf4 VXORPD	%XMM0,%XMM0,%XMM0

0x4edbf8 AND	$0x7,%EAX

0x4edbfb JE	4edccf

0x4edc01 CMP	$0x1,%RAX

0x4edc05 JE	4edcaf

0x4edc0b CMP	$0x2,%RAX

0x4edc0f JE	4edc99

0x4edc15 CMP	$0x3,%RAX

0x4edc19 JE	4edc82

0x4edc1b CMP	$0x4,%RAX

0x4edc1f JE	4edc6b

0x4edc21 CMP	$0x5,%RAX

0x4edc25 JE	4edc55

0x4edc27 CMP	$0x6,%RAX

0x4edc2b JE	4edc3f

0x4edc2d VMOVSD	(%R10),%XMM13

0x4edc32 ADD	$0x8,%R10

0x4edc36 VANDPD	%XMM8,%XMM13,%XMM0

0x4edc3b VMOVSD	%XMM0,(%RCX)

0x4edc3f VMOVSD	(%R10),%XMM14

0x4edc44 ADD	$0x8,%R10

0x4edc48 VANDPD	%XMM8,%XMM14,%XMM5

0x4edc4d VADDSD	%XMM5,%XMM0,%XMM0

0x4edc51 VMOVSD	%XMM0,(%RCX)

0x4edc55 VMOVSD	(%R10),%XMM2

0x4edc5a ADD	$0x8,%R10

0x4edc5e VANDPD	%XMM8,%XMM2,%XMM6

0x4edc63 VADDSD	%XMM6,%XMM0,%XMM0

0x4edc67 VMOVSD	%XMM0,(%RCX)

0x4edc6b VMOVSD	(%R10),%XMM7

0x4edc70 ADD	$0x8,%R10

0x4edc74 VANDPD	%XMM8,%XMM7,%XMM9

0x4edc79 VADDSD	%XMM9,%XMM0,%XMM0

0x4edc7e VMOVSD	%XMM0,(%RCX)

0x4edc82 VMOVSD	(%R10),%XMM10

0x4edc87 ADD	$0x8,%R10

0x4edc8b VANDPD	%XMM8,%XMM10,%XMM15

0x4edc90 VADDSD	%XMM15,%XMM0,%XMM0

0x4edc95 VMOVSD	%XMM0,(%RCX)

0x4edc99 VMOVSD	(%R10),%XMM1

0x4edc9e ADD	$0x8,%R10

0x4edca2 VANDPD	%XMM8,%XMM1,%XMM4

0x4edca7 VADDSD	%XMM4,%XMM0,%XMM0

0x4edcab VMOVSD	%XMM0,(%RCX)

0x4edcaf VMOVSD	(%R10),%XMM13

0x4edcb4 ADD	$0x8,%R10

0x4edcb8 VANDPD	%XMM8,%XMM13,%XMM14

0x4edcbd VADDSD	%XMM14,%XMM0,%XMM0

0x4edcc2 VMOVSD	%XMM0,(%RCX)

0x4edcc6 CMP	%RSI,%R10

0x4edcc9 JE	4edd77

  (1998) 0x4edccf VMOVSD	(%R10),%XMM5

  (1998) 0x4edcd4 ADD	$0x40,%R10

  (1998) 0x4edcd8 VANDPD	%XMM8,%XMM5,%XMM2

  (1998) 0x4edcdd VADDSD	%XMM2,%XMM0,%XMM6

  (1998) 0x4edce1 VMOVSD	%XMM6,(%RCX)

  (1998) 0x4edce5 VMOVSD	-0x38(%R10),%XMM7

  (1998) 0x4edceb VANDPD	%XMM8,%XMM7,%XMM9

  (1998) 0x4edcf0 VADDSD	%XMM9,%XMM6,%XMM10

  (1998) 0x4edcf5 VMOVSD	%XMM10,(%RCX)

  (1998) 0x4edcf9 VMOVSD	-0x30(%R10),%XMM15

  (1998) 0x4edcff VANDPD	%XMM8,%XMM15,%XMM1

  (1998) 0x4edd04 VADDSD	%XMM1,%XMM10,%XMM4

  (1998) 0x4edd08 VMOVSD	%XMM4,(%RCX)

  (1998) 0x4edd0c VMOVSD	-0x28(%R10),%XMM13

  (1998) 0x4edd12 VANDPD	%XMM8,%XMM13,%XMM14

  (1998) 0x4edd17 VADDSD	%XMM14,%XMM4,%XMM0

  (1998) 0x4edd1c VMOVSD	%XMM0,(%RCX)

  (1998) 0x4edd20 VMOVSD	-0x20(%R10),%XMM5

  (1998) 0x4edd26 VANDPD	%XMM8,%XMM5,%XMM2

  (1998) 0x4edd2b VADDSD	%XMM2,%XMM0,%XMM6

  (1998) 0x4edd2f VMOVSD	%XMM6,(%RCX)

  (1998) 0x4edd33 VMOVSD	-0x18(%R10),%XMM7

  (1998) 0x4edd39 VANDPD	%XMM8,%XMM7,%XMM9

  (1998) 0x4edd3e VADDSD	%XMM9,%XMM6,%XMM10

  (1998) 0x4edd43 VMOVSD	%XMM10,(%RCX)

  (1998) 0x4edd47 VMOVSD	-0x10(%R10),%XMM15

  (1998) 0x4edd4d VANDPD	%XMM8,%XMM15,%XMM1

  (1998) 0x4edd52 VADDSD	%XMM1,%XMM10,%XMM4

  (1998) 0x4edd56 VMOVSD	%XMM4,(%RCX)

  (1998) 0x4edd5a VMOVSD	-0x8(%R10),%XMM13

  (1998) 0x4edd60 VANDPD	%XMM8,%XMM13,%XMM14

  (1998) 0x4edd65 VADDSD	%XMM14,%XMM4,%XMM0

  (1998) 0x4edd6a VMOVSD	%XMM0,(%RCX)

  (1998) 0x4edd6e CMP	%RSI,%R10

  (1998) 0x4edd71 JNE	4edccf

0x4edd77 CMPQ	$0,-0x40(%RBP)

0x4edd7c JNE	4edda6

0x4edd7e INC	%R8

0x4edd81 ADD	$0x8,%RCX

0x4edd85 CMP	%R9,%R8

0x4edd88 JE	4e9949

0x4edd8e MOVQ	$0,(%RCX)

0x4edd95 MOV	(%R14,%R8,8),%RAX

0x4edd99 MOV	0x8(%R14,%R8,8),%RDI

0x4edd9e MOV	%R8,%RDX

0x4edda1 JMP	4edbd0

0x4edda6 MOV	-0x90(%RBP),%RDI

0x4eddad MOV	(%RDI,%RDX,8),%R10

0x4eddb1 MOV	0x8(%RDI,%RDX,8),%RDX

0x4eddb6 CMP	%R10,%RDX

0x4eddb9 JLE	4edd7e

0x4eddbb MOV	-0x60(%RBP),%RSI

0x4eddbf LEA	(%RSI,%RDX,8),%RDI

0x4eddc3 LEA	(%RSI,%R10,8),%RAX

0x4eddc7 MOV	%RDI,%R10

0x4eddca SUB	%RAX,%R10

0x4eddcd SUB	$0x8,%R10

0x4eddd1 SHR	$0x3,%R10

0x4eddd5 INC	%R10

0x4eddd8 AND	$0x7,%R10D

0x4edddc JE	4ede97

0x4edde2 CMP	$0x1,%R10

0x4edde6 JE	4ede79

0x4eddec CMP	$0x2,%R10

0x4eddf0 JE	4ede64

0x4eddf2 CMP	$0x3,%R10

0x4eddf6 JE	4ede4e

0x4eddf8 CMP	$0x4,%R10

0x4eddfc JE	4ede39

0x4eddfe CMP	$0x5,%R10

0x4ede02 JE	4ede23

0x4ede04 CMP	$0x6,%R10

0x4ede08 JNE	4ee00d

0x4ede0e VMOVSD	(%RAX),%XMM6

0x4ede12 ADD	$0x8,%RAX

0x4ede16 VANDPD	%XMM11,%XMM6,%XMM7

0x4ede1b VADDSD	%XMM7,%XMM0,%XMM0

0x4ede1f VMOVSD	%XMM0,(%RCX)

0x4ede23 VMOVSD	(%RAX),%XMM9

0x4ede27 ADD	$0x8,%RAX

0x4ede2b VANDPD	%XMM11,%XMM9,%XMM10

0x4ede30 VADDSD	%XMM10,%XMM0,%XMM0

0x4ede35 VMOVSD	%XMM0,(%RCX)

0x4ede39 VMOVSD	(%RAX),%XMM15

0x4ede3d ADD	$0x8,%RAX

0x4ede41 VANDPD	%XMM11,%XMM15,%XMM1

0x4ede46 VADDSD	%XMM1,%XMM0,%XMM0

0x4ede4a VMOVSD	%XMM0,(%RCX)

0x4ede4e VMOVSD	(%RAX),%XMM4

0x4ede52 ADD	$0x8,%RAX

0x4ede56 VANDPD	%XMM11,%XMM4,%XMM13

0x4ede5b VADDSD	%XMM13,%XMM0,%XMM0

0x4ede60 VMOVSD	%XMM0,(%RCX)

0x4ede64 VMOVSD	(%RAX),%XMM14

0x4ede68 ADD	$0x8,%RAX

0x4ede6c VANDPD	%XMM11,%XMM14,%XMM5

0x4ede71 VADDSD	%XMM5,%XMM0,%XMM0

0x4ede75 VMOVSD	%XMM0,(%RCX)

0x4ede79 VMOVSD	(%RAX),%XMM2

0x4ede7d ADD	$0x8,%RAX

0x4ede81 VANDPD	%XMM11,%XMM2,%XMM6

0x4ede86 VADDSD	%XMM6,%XMM0,%XMM0

0x4ede8a VMOVSD	%XMM0,(%RCX)

0x4ede8e CMP	%RDI,%RAX

0x4ede91 JE	4edd7e

  (1997) 0x4ede97 VMOVSD	(%RAX),%XMM7

  (1997) 0x4ede9b ADD	$0x40,%RAX

  (1997) 0x4ede9f VANDPD	%XMM11,%XMM7,%XMM9

  (1997) 0x4edea4 VADDSD	%XMM9,%XMM0,%XMM0

  (1997) 0x4edea9 VMOVSD	%XMM0,(%RCX)

  (1997) 0x4edead VMOVSD	-0x38(%RAX),%XMM10

  (1997) 0x4edeb2 VANDPD	%XMM11,%XMM10,%XMM15

  (1997) 0x4edeb7 VADDSD	%XMM15,%XMM0,%XMM1

  (1997) 0x4edebc VMOVSD	%XMM1,(%RCX)

  (1997) 0x4edec0 VMOVSD	-0x30(%RAX),%XMM4

  (1997) 0x4edec5 VANDPD	%XMM11,%XMM4,%XMM13

  (1997) 0x4edeca VADDSD	%XMM13,%XMM1,%XMM14

  (1997) 0x4edecf VMOVSD	%XMM14,(%RCX)

  (1997) 0x4eded3 VMOVSD	-0x28(%RAX),%XMM5

  (1997) 0x4eded8 VANDPD	%XMM11,%XMM5,%XMM2

  (1997) 0x4ededd VADDSD	%XMM2,%XMM14,%XMM6

  (1997) 0x4edee1 VMOVSD	%XMM6,(%RCX)

  (1997) 0x4edee5 VMOVSD	-0x20(%RAX),%XMM7

  (1997) 0x4edeea VANDPD	%XMM11,%XMM7,%XMM9

  (1997) 0x4edeef VADDSD	%XMM9,%XMM6,%XMM0

  (1997) 0x4edef4 VMOVSD	%XMM0,(%RCX)

  (1997) 0x4edef8 VMOVSD	-0x18(%RAX),%XMM10

  (1997) 0x4edefd VANDPD	%XMM11,%XMM10,%XMM15

  (1997) 0x4edf02 VADDSD	%XMM15,%XMM0,%XMM1

  (1997) 0x4edf07 VMOVSD	%XMM1,(%RCX)

  (1997) 0x4edf0b VMOVSD	-0x10(%RAX),%XMM4

  (1997) 0x4edf10 VANDPD	%XMM11,%XMM4,%XMM13

  (1997) 0x4edf15 VADDSD	%XMM13,%XMM1,%XMM14

  (1997) 0x4edf1a VMOVSD	%XMM14,(%RCX)

  (1997) 0x4edf1e VMOVSD	-0x8(%RAX),%XMM5

  (1997) 0x4edf23 VANDPD	%XMM11,%XMM5,%XMM2

  (1997) 0x4edf28 VADDSD	%XMM2,%XMM14,%XMM0

  (1997) 0x4edf2c VMOVSD	%XMM0,(%RCX)

  (1997) 0x4edf30 CMP	%RDI,%RAX

  (1997) 0x4edf33 JNE	4ede97

0x4edf39 JMP	4edd7e

0x4edf3e VXORPD	%XMM0,%XMM0,%XMM0

0x4edf42 JMP	4edd77

0x4ee00d VMOVSD	(%RAX),%XMM5

0x4ee011 ADD	$0x8,%RAX

0x4ee015 VANDPD	%XMM11,%XMM5,%XMM2

0x4ee01a VADDSD	%XMM2,%XMM0,%XMM0

0x4ee01e VMOVSD	%XMM0,(%RCX)

0x4ee022 JMP	4ede0e

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3382 - 3401

--------------------------------------------------------------------------------

3382:          for (i = ns; i < ne; i++)

3383:          {

3384:             l1_norm[i] = 0.0;

3385:             if (cf_marker == NULL)

3386:             {

3387:                /* Add the l1 norm of the diag part of the ith row */

3388:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3389:                   l1_norm[i] += fabs(A_diag_data[j]);

3390:                /* Add the l1 norm of the offd part of the ith row */

3391:                if (num_cols_offd)

3392:                {

3393:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3394:                      l1_norm[i] += fabs(A_offd_data[j]);

[...]

3401:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

Coverage (%)	Name	Source Location	Module
○100.00	gomp_thread_start	team.c:130	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.53
CQA speedup if FP arith vectorized	2.38
CQA speedup if fully vectorized	11.23
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.62
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source	ams.c:3382-3384,ams.c:3388-3394,ams.c:3401-3401
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	23.17
CQA cycles if no scalar integer	15.17
CQA cycles if FP arith vectorized	9.75
CQA cycles if fully vectorized	2.06
Front-end cycles	23.17
P0 cycles	14.27
P1 cycles	14.23
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	7.50
P5 cycles	14.10
P6 cycles	14.20
P7 cycles	7.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	14.20
P11 cycles	7.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	139.00
Nb uops	139.00
Nb loads	21.00
Nb stores	15.00
Nb stack references	3.00
FLOP/cycle	0.56
Nb FLOP add-sub	13.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.43
Bytes prefetched	0.00
Bytes loaded	168.00
Bytes stored	120.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	21.05
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	47.06
Vector-efficiency ratio all	15.05
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.08
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.38

Metric	Value
CQA speedup if no scalar integer	1.53
CQA speedup if FP arith vectorized	2.38
CQA speedup if fully vectorized	11.23
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.62
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source	ams.c:3382-3384,ams.c:3388-3394,ams.c:3401-3401
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	23.17
CQA cycles if no scalar integer	15.17
CQA cycles if FP arith vectorized	9.75
CQA cycles if fully vectorized	2.06
Front-end cycles	23.17
P0 cycles	14.27
P1 cycles	14.23
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	7.50
P5 cycles	14.10
P6 cycles	14.20
P7 cycles	7.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	14.20
P11 cycles	7.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	139.00
Nb uops	139.00
Nb loads	21.00
Nb stores	15.00
Nb stack references	3.00
FLOP/cycle	0.56
Nb FLOP add-sub	13.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.43
Bytes prefetched	0.00
Bytes loaded	168.00
Bytes stored	120.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	21.05
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	47.06
Vector-efficiency ratio all	15.05
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.08
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.38

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source file and lines	ams.c:3382-3401
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3382-3394,3401.

Analyzed code is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3382-3384,3388-3394,3401.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 272 paths individually, rerun with max-paths=272
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 272 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.17 to 15.17 cycles (1.53x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 23.17 to 2.06 cycles (11.23x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

13 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 13 FP arithmetical operations:

13: addition or subtraction

The binary loop is loading 168 bytes (21 double precision FP elements). The binary loop is storing 120 bytes (15 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	139
nb uops	139
loop length	583
used x86 registers	11
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.17 cycles
front end	23.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.27	14.23	7.00	7.00	7.50	14.10	14.20	7.50	7.50	7.50	14.20	7.00
cycles	14.27	14.23	7.00	7.00	7.50	14.10	14.20	7.50	7.50	7.50	14.20	7.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.17
Dispatch	14.27
Overall L1	23.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	28%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	21%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	47%

Vector efficiency ratios

INT

all	12%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	16%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.17 cycles. At this rate:

3% of peak load performance is reached (7.25 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.18 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 23.17 to 14.27 cycles (1.62x speedup).

ASM code

In the binary file, the address of the loop is: 4edbd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
CMP %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 4edf3e <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4bbe>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R13,%RDI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R13,%RAX,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
AND $0x7,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4edccf <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x494f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edcaf <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x492f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edc99 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4919>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edc82 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4902>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edc6b <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x48eb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edc55 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x48d5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edc3f <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x48bf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R10),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM8,%XMM13,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM8,%XMM14,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM5,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM8,%XMM2,%XMM6	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM6,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM8,%XMM7,%XMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM9,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM8,%XMM10,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM15,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM8,%XMM1,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM4,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM8,%XMM13,%XMM14	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM14,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RSI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edd77 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x49f7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPQ $0,-0x40(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 4edda6 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4a26>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e9949 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x5c9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%R14,%R8,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R14,%R8,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4edbd0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4850>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x90(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI,%RDX,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDI,%RDX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R10,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 4edd7e <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x49fe>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x60(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RDX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RSI,%R10,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4ede97 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4b17>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ede79 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4af9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ede64 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4ae4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ede4e <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4ace>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ede39 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4ab9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ede23 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4aa3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4ee00d <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4c8d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RAX),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM6,%XMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM7,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM9,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM10,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM15,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM4,%XMM13	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM13,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM14,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM5,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM2,%XMM6	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM6,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edd7e <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x49fe>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4edd7e <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x49fe>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 4edd77 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x49f7>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVSD (%RAX),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM5,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM2,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 4ede0e <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4a8e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source file and lines	ams.c:3382-3401
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 272 paths individually, rerun with max-paths=272
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

13 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 13 FP arithmetical operations:

13: addition or subtraction

The binary loop is loading 168 bytes (21 double precision FP elements). The binary loop is storing 120 bytes (15 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	139
nb uops	139
loop length	583
used x86 registers	11
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.17 cycles
front end	23.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.27	14.23	7.00	7.00	7.50	14.10	14.20	7.50	7.50	7.50	14.20	7.00
cycles	14.27	14.23	7.00	7.00	7.50	14.10	14.20	7.50	7.50	7.50	14.20	7.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.17
Dispatch	14.27
Overall L1	23.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	28%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	21%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	47%

Vector efficiency ratios

INT

all	12%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	16%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.17 cycles. At this rate:

3% of peak load performance is reached (7.25 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.18 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4edbd0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
CMP %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 4edf3e <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4bbe>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R13,%RDI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R13,%RAX,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
AND $0x7,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4edccf <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x494f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edcaf <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x492f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edc99 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4919>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edc82 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4902>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edc6b <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x48eb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edc55 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x48d5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edc3f <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x48bf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R10),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM8,%XMM13,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM8,%XMM14,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM5,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM8,%XMM2,%XMM6	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM6,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM8,%XMM7,%XMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM9,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM8,%XMM10,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM15,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM8,%XMM1,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM4,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%R10),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM8,%XMM13,%XMM14	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM14,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RSI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edd77 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x49f7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPQ $0,-0x40(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 4edda6 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4a26>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4e9949 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x5c9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV (%R14,%R8,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R14,%R8,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4edbd0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4850>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0x90(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI,%RDX,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDI,%RDX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R10,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 4edd7e <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x49fe>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x60(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%RDX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RSI,%R10,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 4ede97 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4b17>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ede79 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4af9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ede64 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4ae4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ede4e <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4ace>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ede39 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4ab9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4ede23 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4aa3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4ee00d <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4c8d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%RAX),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM6,%XMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM7,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM9,%XMM10	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM10,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM15,%XMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM4,%XMM13	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM13,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM14,%XMM5	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM5,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM2,%XMM6	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM6,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 4edd7e <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x49fe>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4edd7e <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x49fe>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 4edd77 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x49f7>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVSD (%RAX),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM5,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VADDSD %XMM2,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JMP 4ede0e <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4a8e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code