OV - exec - Loop 1993

	Loop Id: 1993	Module: exec	Source: ams.c:3532-3534	Coverage: 0.04%

0x4e9a81 MOV	(%R14,%RAX,8),%R10    [3]

0x4e9a85 VCOMISD	(%R13,%R10,8),%XMM8    [2]

0x4e9a8c JBE	4e9a9e

0x4e9a8e VMOVSD	(%R15,%RAX,8),%XMM6    [1]

0x4e9a94 VXORPD	%XMM3,%XMM6,%XMM7

0x4e9a98 VMOVSD	%XMM7,(%R15,%RAX,8)    [1]

0x4e9a9e INC	%RAX

0x4e9aa1 MOV	(%R14,%RAX,8),%R8    [3]

0x4e9aa5 VCOMISD	(%R13,%R8,8),%XMM8    [2]

0x4e9aac JBE	4e9abe

0x4e9aae VMOVSD	(%R15,%RAX,8),%XMM9    [1]

0x4e9ab4 VXORPD	%XMM3,%XMM9,%XMM0

0x4e9ab8 VMOVSD	%XMM0,(%R15,%RAX,8)    [1]

0x4e9abe LEA	0x1(%RAX),%RDX

0x4e9ac2 MOV	(%R14,%RDX,8),%RCX    [3]

0x4e9ac6 VCOMISD	(%R13,%RCX,8),%XMM8    [2]

0x4e9acd JBE	4e9adf

0x4e9acf VMOVSD	(%R15,%RDX,8),%XMM10    [1]

0x4e9ad5 VXORPD	%XMM3,%XMM10,%XMM15

0x4e9ad9 VMOVSD	%XMM15,(%R15,%RDX,8)    [1]

0x4e9adf LEA	0x2(%RAX),%R10

0x4e9ae3 MOV	(%R14,%R10,8),%RSI    [3]

0x4e9ae7 VCOMISD	(%R13,%RSI,8),%XMM8    [2]

0x4e9aee JBE	4e9b00

0x4e9af0 VMOVSD	(%R15,%R10,8),%XMM1    [1]

0x4e9af6 VXORPD	%XMM3,%XMM1,%XMM4

0x4e9afa VMOVSD	%XMM4,(%R15,%R10,8)    [1]

0x4e9b00 LEA	0x3(%RAX),%R8

0x4e9b04 MOV	(%R14,%R8,8),%RDX    [3]

0x4e9b08 VCOMISD	(%R13,%RDX,8),%XMM8    [2]

0x4e9b0f JBE	4e9b21

0x4e9b11 VMOVSD	(%R15,%R8,8),%XMM13    [1]

0x4e9b17 VXORPD	%XMM3,%XMM13,%XMM14

0x4e9b1b VMOVSD	%XMM14,(%R15,%R8,8)    [1]

0x4e9b21 LEA	0x4(%RAX),%RCX

0x4e9b25 MOV	(%R14,%RCX,8),%R10    [3]

0x4e9b29 VCOMISD	(%R13,%R10,8),%XMM8    [2]

0x4e9b30 JBE	4e9b42

0x4e9b32 VMOVSD	(%R15,%RCX,8),%XMM5    [1]

0x4e9b38 VXORPD	%XMM3,%XMM5,%XMM2

0x4e9b3c VMOVSD	%XMM2,(%R15,%RCX,8)    [1]

0x4e9b42 LEA	0x5(%RAX),%R8

0x4e9b46 MOV	(%R14,%R8,8),%RSI    [3]

0x4e9b4a VCOMISD	(%R13,%RSI,8),%XMM8    [2]

0x4e9b51 JBE	4e9b63

0x4e9b53 VMOVSD	(%R15,%R8,8),%XMM11    [1]

0x4e9b59 VXORPD	%XMM3,%XMM11,%XMM6

0x4e9b5d VMOVSD	%XMM6,(%R15,%R8,8)    [1]

0x4e9b63 LEA	0x6(%RAX),%RDX

0x4e9b67 MOV	(%R14,%RDX,8),%RCX    [3]

0x4e9b6b VCOMISD	(%R13,%RCX,8),%XMM8    [2]

0x4e9b72 JBE	4e9b84

0x4e9b74 VMOVSD	(%R15,%RDX,8),%XMM7    [1]

0x4e9b7a VXORPD	%XMM3,%XMM7,%XMM9

0x4e9b7e VMOVSD	%XMM9,(%R15,%RDX,8)    [1]

0x4e9b84 ADD	$0x7,%RAX

0x4e9b88 CMP	%RAX,%R9

0x4e9b8b JNE	4e9a81

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3532 - 3534

--------------------------------------------------------------------------------

3532:       for (i = ns; i < ne; i++)

3533:          if (A_diag_data[A_diag_I[i]] < 0)

3534:             l1_norm[i] = -l1_norm[i];

Coverage (%)	Name	Source Location	Module
○100.00	gomp_thread_start	team.c:130	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.27
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.27
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source	ams.c:3532-3534
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.83
CQA cycles if no scalar integer	8.50
CQA cycles if FP arith vectorized	10.83
CQA cycles if fully vectorized	1.35
Front-end cycles	10.83
P0 cycles	8.50
P1 cycles	4.00
P2 cycles	8.00
P3 cycles	8.00
P4 cycles	4.00
P5 cycles	4.00
P6 cycles	8.50
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.00
P11 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	65.00
Nb loads	24.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.63
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	25.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	15.63
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	1.27
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.27
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source	ams.c:3532-3534
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.83
CQA cycles if no scalar integer	8.50
CQA cycles if FP arith vectorized	10.83
CQA cycles if fully vectorized	1.35
Front-end cycles	10.83
P0 cycles	8.50
P1 cycles	4.00
P2 cycles	8.00
P3 cycles	8.00
P4 cycles	4.00
P5 cycles	4.00
P6 cycles	8.50
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	0.00
P11 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	65.00
Nb loads	24.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.63
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	25.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	15.63
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source file and lines	ams.c:3532-3534
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3532-3534.

The related source loop is multi-versionned.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 256 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.83 to 8.50 cycles (1.27x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 10.83 to 1.35 cycles (8.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3533
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3533
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3533
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3533
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3533
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3533
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3533
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3533

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 192 bytes (24 double precision FP elements). The binary loop is storing 64 bytes (8 double precision FP elements).

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	58
nb uops	65
loop length	272
used x86 registers	10
used mmx registers	0
used xmm registers	15
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.83 cycles
front end	10.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.50	4.00	8.00	8.00	4.00	4.00	8.50	4.00	4.00	4.00	0.00	8.00
cycles	8.50	4.00	8.00	8.00	4.00	4.00	8.50	4.00	4.00	4.00	0.00	8.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.83
Dispatch	8.50
Overall L1	10.83

Vectorization ratios

all	25%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.83 cycles. At this rate:

9% of peak load performance is reached (17.72 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.91 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.83 to 8.50 cycles (1.27x speedup).

ASM code

In the binary file, the address of the loop is: 4e9a81

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%R14,%RAX,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VCOMISD (%R13,%R10,8),%XMM8	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JBE 4e9a9e <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x71e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%RAX,8),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPD %XMM3,%XMM6,%XMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD %XMM7,(%R15,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R14,%RAX,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VCOMISD (%R13,%R8,8),%XMM8	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JBE 4e9abe <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x73e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%RAX,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPD %XMM3,%XMM9,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD %XMM0,(%R15,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%RAX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R14,%RDX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VCOMISD (%R13,%RCX,8),%XMM8	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JBE 4e9adf <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x75f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%RDX,8),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPD %XMM3,%XMM10,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD %XMM15,(%R15,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x2(%RAX),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R14,%R10,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VCOMISD (%R13,%RSI,8),%XMM8	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JBE 4e9b00 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x780>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%R10,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPD %XMM3,%XMM1,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD %XMM4,(%R15,%R10,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x3(%RAX),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R14,%R8,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VCOMISD (%R13,%RDX,8),%XMM8	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JBE 4e9b21 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x7a1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%R8,8),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPD %XMM3,%XMM13,%XMM14	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD %XMM14,(%R15,%R8,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x4(%RAX),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R14,%RCX,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VCOMISD (%R13,%R10,8),%XMM8	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JBE 4e9b42 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x7c2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%RCX,8),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPD %XMM3,%XMM5,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD %XMM2,(%R15,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x5(%RAX),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R14,%R8,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VCOMISD (%R13,%RSI,8),%XMM8	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JBE 4e9b63 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x7e3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%R8,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPD %XMM3,%XMM11,%XMM6	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD %XMM6,(%R15,%R8,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x6(%RAX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R14,%RDX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VCOMISD (%R13,%RCX,8),%XMM8	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JBE 4e9b84 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x804>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%RDX,8),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPD %XMM3,%XMM7,%XMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD %XMM9,(%R15,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x7,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 4e9a81 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x701>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source file and lines	ams.c:3532-3534
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3532-3534.

The related source loop is multi-versionned.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.83 to 8.50 cycles (1.27x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 8 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3533
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3533
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3533
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3533
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3533
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3533
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3533
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3533

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	58
nb uops	65
loop length	272
used x86 registers	10
used mmx registers	0
used xmm registers	15
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.83 cycles
front end	10.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.50	4.00	8.00	8.00	4.00	4.00	8.50	4.00	4.00	4.00	0.00	8.00
cycles	8.50	4.00	8.00	8.00	4.00	4.00	8.50	4.00	4.00	4.00	0.00	8.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.83
Dispatch	8.50
Overall L1	10.83

Vectorization ratios

all	25%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.83 cycles. At this rate:

9% of peak load performance is reached (17.72 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.91 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4e9a81

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%R14,%RAX,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VCOMISD (%R13,%R10,8),%XMM8	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JBE 4e9a9e <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x71e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%RAX,8),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPD %XMM3,%XMM6,%XMM7	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD %XMM7,(%R15,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R14,%RAX,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VCOMISD (%R13,%R8,8),%XMM8	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JBE 4e9abe <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x73e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%RAX,8),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPD %XMM3,%XMM9,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD %XMM0,(%R15,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%RAX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R14,%RDX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VCOMISD (%R13,%RCX,8),%XMM8	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JBE 4e9adf <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x75f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%RDX,8),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPD %XMM3,%XMM10,%XMM15	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD %XMM15,(%R15,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x2(%RAX),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R14,%R10,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VCOMISD (%R13,%RSI,8),%XMM8	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JBE 4e9b00 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x780>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%R10,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPD %XMM3,%XMM1,%XMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD %XMM4,(%R15,%R10,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x3(%RAX),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R14,%R8,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VCOMISD (%R13,%RDX,8),%XMM8	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JBE 4e9b21 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x7a1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%R8,8),%XMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPD %XMM3,%XMM13,%XMM14	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD %XMM14,(%R15,%R8,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x4(%RAX),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R14,%RCX,8),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VCOMISD (%R13,%R10,8),%XMM8	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JBE 4e9b42 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x7c2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%RCX,8),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPD %XMM3,%XMM5,%XMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD %XMM2,(%R15,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x5(%RAX),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R14,%R8,8),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VCOMISD (%R13,%RSI,8),%XMM8	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JBE 4e9b63 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x7e3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%R8,8),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPD %XMM3,%XMM11,%XMM6	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD %XMM6,(%R15,%R8,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x6(%RAX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R14,%RDX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VCOMISD (%R13,%RCX,8),%XMM8	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JBE 4e9b84 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x804>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R15,%RDX,8),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VXORPD %XMM3,%XMM7,%XMM9	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVSD %XMM9,(%R15,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x7,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 4e9a81 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x701>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code