OV - exec - Loop 1838

	Loop Id: 1838	Module: exec	Source: par_strength.c:1261-1263	Coverage: 0.01%

0x4d7e45 CMPQ	$0,(%R10)    [1]

0x4d7e49 JLE	4d7e53

0x4d7e4b INC	%RDX

0x4d7e4e MOV	$0x1,%ESI

0x4d7e53 CMPQ	$0,0x8(%R10)    [1]

0x4d7e58 LEA	0x8(%R10),%R9

0x4d7e5c JLE	4d7e66

0x4d7e5e INC	%RDX

0x4d7e61 MOV	$0x1,%ESI

0x4d7e66 CMPQ	$0,0x8(%R9)    [2]

0x4d7e6b JLE	4d7e75

0x4d7e6d INC	%RDX

0x4d7e70 MOV	$0x1,%ESI

0x4d7e75 CMPQ	$0,0x10(%R9)    [2]

0x4d7e7a JLE	4d7e84

0x4d7e7c INC	%RDX

0x4d7e7f MOV	$0x1,%ESI

0x4d7e84 CMPQ	$0,0x18(%R9)    [2]

0x4d7e89 JLE	4d7e93

0x4d7e8b INC	%RDX

0x4d7e8e MOV	$0x1,%ESI

0x4d7e93 CMPQ	$0,0x20(%R9)    [2]

0x4d7e98 JLE	4d7ea2

0x4d7e9a INC	%RDX

0x4d7e9d MOV	$0x1,%ESI

0x4d7ea2 CMPQ	$0,0x28(%R9)    [2]

0x4d7ea7 JLE	4d7eb1

0x4d7ea9 INC	%RDX

0x4d7eac MOV	$0x1,%ESI

0x4d7eb1 CMPQ	$0,0x30(%R9)    [2]

0x4d7eb6 JLE	4d7ec0

0x4d7eb8 INC	%RDX

0x4d7ebb MOV	$0x1,%ESI

0x4d7ec0 LEA	0x38(%R9),%R10

0x4d7ec4 CMP	%R10,%RDI

0x4d7ec7 JNE	4d7e45

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1261 - 1263

--------------------------------------------------------------------------------

1261:       for (i = i_begin; i < i_end; i++)

1262:       {

1263:          if (CF_marker[i] > 0) num_coarse_private++;

Coverage (%)	Name	Source Location	Module
○98.96	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.04	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	11.08
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGCreate2ndS._omp_fn.0
Source	par_strength.c:1261-1263
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.83
CQA cycles if no scalar integer	5.83
CQA cycles if FP arith vectorized	5.83
CQA cycles if fully vectorized	0.53
Front-end cycles	5.83
P0 cycles	5.10
P1 cycles	5.00
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	0.00
P5 cycles	5.00
P6 cycles	4.90
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	5.00
P11 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	35.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.97
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.42
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.38

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	11.08
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGCreate2ndS._omp_fn.0
Source	par_strength.c:1261-1263
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.83
CQA cycles if no scalar integer	5.83
CQA cycles if FP arith vectorized	5.83
CQA cycles if fully vectorized	0.53
Front-end cycles	5.83
P0 cycles	5.10
P1 cycles	5.00
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	0.00
P5 cycles	5.00
P6 cycles	4.90
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	5.00
P11 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	35.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.97
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.42
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.38

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCreate2ndS._omp_fn.0
Source file and lines	par_strength.c:1261-1263
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1261-1263.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 256 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.83 to 0.53 cycles (11.08x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	36
nb uops	35
loop length	136
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.83 cycles
front end	5.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.10	5.00	2.67	2.67	0.00	5.00	4.90	0.00	0.00	0.00	5.00	2.67
cycles	5.10	5.00	2.67	2.67	0.00	5.00	4.90	0.00	0.00	0.00	5.00	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.83
Dispatch	5.10
Overall L1	5.83

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.83 cycles. At this rate:

5% of peak load performance is reached (10.97 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.83 to 5.10 cycles (1.14x speedup).

ASM code

In the binary file, the address of the loop is: 4d7e45

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
CMPQ $0,(%R10)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 4d7e53 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x133>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
CMPQ $0,0x8(%R10)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x8(%R10),%R9	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JLE 4d7e66 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x146>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
CMPQ $0,0x8(%R9)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 4d7e75 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x155>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
CMPQ $0,0x10(%R9)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 4d7e84 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x164>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
CMPQ $0,0x18(%R9)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 4d7e93 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x173>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
CMPQ $0,0x20(%R9)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 4d7ea2 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x182>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
CMPQ $0,0x28(%R9)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 4d7eb1 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x191>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
CMPQ $0,0x30(%R9)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 4d7ec0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x1a0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
LEA 0x38(%R9),%R10	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R10,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 4d7e45 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x125>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	hypre_BoomerAMGCreate2ndS._omp_fn.0
Source file and lines	par_strength.c:1261-1263
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	36
nb uops	35
loop length	136
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.83 cycles
front end	5.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.10	5.00	2.67	2.67	0.00	5.00	4.90	0.00	0.00	0.00	5.00	2.67
cycles	5.10	5.00	2.67	2.67	0.00	5.00	4.90	0.00	0.00	0.00	5.00	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.83
Dispatch	5.10
Overall L1	5.83

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.83 cycles. At this rate:

5% of peak load performance is reached (10.97 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4d7e45

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
CMPQ $0,(%R10)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 4d7e53 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x133>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
CMPQ $0,0x8(%R10)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
LEA 0x8(%R10),%R9	1	0	0	0	0	0	0	0	0	0	0.17	N/A
JLE 4d7e66 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x146>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
CMPQ $0,0x8(%R9)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 4d7e75 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x155>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
CMPQ $0,0x10(%R9)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 4d7e84 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x164>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
CMPQ $0,0x18(%R9)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 4d7e93 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x173>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
CMPQ $0,0x20(%R9)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 4d7ea2 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x182>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
CMPQ $0,0x28(%R9)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 4d7eb1 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x191>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
CMPQ $0,0x30(%R9)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	scal (12.5%)
JLE 4d7ec0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x1a0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $0x1,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
LEA 0x38(%R9),%R10	1	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R10,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 4d7e45 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x125>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code