OV - exec - Loop 1774

0x4d38b6 VMOVSD	(%RSI),%XMM15    [1]

0x4d38ba VMOVSD	0x8(%RSI),%XMM2    [1]

0x4d38bf VMINSD	%XMM15,%XMM13,%XMM0

0x4d38c4 VADDSD	%XMM15,%XMM14,%XMM1

0x4d38c9 VMOVSD	0x10(%RSI),%XMM10    [1]

0x4d38ce VMINSD	%XMM2,%XMM0,%XMM8

0x4d38d2 VADDSD	%XMM2,%XMM1,%XMM9

0x4d38d6 VMOVSD	0x18(%RSI),%XMM13    [1]

0x4d38db VMINSD	%XMM10,%XMM8,%XMM11

0x4d38e0 VADDSD	%XMM10,%XMM9,%XMM12

0x4d38e5 VMOVSD	0x20(%RSI),%XMM1    [1]

0x4d38ea VMINSD	%XMM13,%XMM11,%XMM14

0x4d38ef VADDSD	%XMM13,%XMM12,%XMM15

0x4d38f4 VMOVSD	0x28(%RSI),%XMM2    [1]

0x4d38f9 VMINSD	%XMM1,%XMM14,%XMM0

0x4d38fd VADDSD	%XMM1,%XMM15,%XMM8

0x4d3901 VMOVSD	0x30(%RSI),%XMM11    [1]

0x4d3906 VMINSD	%XMM2,%XMM0,%XMM9

0x4d390a VADDSD	%XMM2,%XMM8,%XMM10

0x4d390e VMOVSD	0x38(%RSI),%XMM15    [1]

0x4d3913 VMINSD	%XMM11,%XMM9,%XMM12

0x4d3918 VADDSD	%XMM11,%XMM10,%XMM14

0x4d391d ADD	$0x40,%RSI

0x4d3921 VMINSD	%XMM15,%XMM12,%XMM13

0x4d3926 VADDSD	%XMM15,%XMM14,%XMM14

0x4d392b CMP	%RSI,%RAX

0x4d392e JNE	4d38b6

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 324 - 327

--------------------------------------------------------------------------------

324:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

325:             {

326:                row_scale = hypre_min(row_scale, A_diag_data[jA]);

327:                row_sum += A_diag_data[jA];

Coverage (%)	Name	Source Location	Module
○97.96	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.04	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.55
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	5.82
Bottlenecks
Function	hypre_BoomerAMGCreateS._omp_fn.1
Source	par_strength.c:324-327
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.00
CQA cycles if no scalar integer	32.00
CQA cycles if FP arith vectorized	20.59
CQA cycles if fully vectorized	4.00
Front-end cycles	4.33
P0 cycles	5.50
P1 cycles	5.50
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	0.00
P5 cycles	5.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	32
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	26.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.25
Nb FLOP add-sub	8.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.55
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	5.82
Bottlenecks
Function	hypre_BoomerAMGCreateS._omp_fn.1
Source	par_strength.c:324-327
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.00
CQA cycles if no scalar integer	32.00
CQA cycles if FP arith vectorized	20.59
CQA cycles if fully vectorized	4.00
Front-end cycles	4.33
P0 cycles	5.50
P1 cycles	5.50
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	0.00
P5 cycles	5.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	32
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	26.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.25
Nb FLOP add-sub	8.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCreateS._omp_fn.1
Source file and lines	par_strength.c:324-327
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:324-327.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 32.00 to 4.00 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

16 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

8: addition or subtraction

The binary loop is loading 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	27
nb uops	26
loop length	122
used x86 registers	2
used mmx registers	0
used xmm registers	11
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.33 cycles
front end	4.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.50	5.50	2.67	2.67	0.00	5.00	1.00	0.00	0.00	0.00	0.00	2.67
cycles	5.50	5.50	2.67	2.67	0.00	5.00	1.00	0.00	0.00	0.00	0.00	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	32.00

Cycles summary

Front-end	4.33
Dispatch	5.50
Data deps.	32.00
Overall L1	32.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.00 cycles. At this rate:

1% of peak load performance is reached (2.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4d38b6

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
VMOVSD (%RSI),%XMM15	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x8(%RSI),%XMM2	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMINSD %XMM15,%XMM13,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM15,%XMM14,%XMM1	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVSD 0x10(%RSI),%XMM10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMINSD %XMM2,%XMM0,%XMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM2,%XMM1,%XMM9	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVSD 0x18(%RSI),%XMM13	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMINSD %XMM10,%XMM8,%XMM11	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM10,%XMM9,%XMM12	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVSD 0x20(%RSI),%XMM1	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMINSD %XMM13,%XMM11,%XMM14	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM13,%XMM12,%XMM15	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVSD 0x28(%RSI),%XMM2	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMINSD %XMM1,%XMM14,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM1,%XMM15,%XMM8	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVSD 0x30(%RSI),%XMM11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMINSD %XMM2,%XMM0,%XMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM2,%XMM8,%XMM10	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVSD 0x38(%RSI),%XMM15	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMINSD %XMM11,%XMM9,%XMM12	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM11,%XMM10,%XMM14	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
ADD $0x40,%RSI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
VMINSD %XMM15,%XMM12,%XMM13	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM15,%XMM14,%XMM14	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
CMP %RSI,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 4d38b6 <hypre_BoomerAMGCreateS._omp_fn.1+0x9e6>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	hypre_BoomerAMGCreateS._omp_fn.1
Source file and lines	par_strength.c:324-327
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:324-327.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 32.00 to 4.00 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

16 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

8: addition or subtraction

The binary loop is loading 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	27
nb uops	26
loop length	122
used x86 registers	2
used mmx registers	0
used xmm registers	11
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.33 cycles
front end	4.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.50	5.50	2.67	2.67	0.00	5.00	1.00	0.00	0.00	0.00	0.00	2.67
cycles	5.50	5.50	2.67	2.67	0.00	5.00	1.00	0.00	0.00	0.00	0.00	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	32.00

Cycles summary

Front-end	4.33
Dispatch	5.50
Data deps.	32.00
Overall L1	32.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.00 cycles. At this rate:

1% of peak load performance is reached (2.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4d38b6

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
VMOVSD (%RSI),%XMM15	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x8(%RSI),%XMM2	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMINSD %XMM15,%XMM13,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM15,%XMM14,%XMM1	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVSD 0x10(%RSI),%XMM10	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMINSD %XMM2,%XMM0,%XMM8	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM2,%XMM1,%XMM9	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVSD 0x18(%RSI),%XMM13	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMINSD %XMM10,%XMM8,%XMM11	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM10,%XMM9,%XMM12	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVSD 0x20(%RSI),%XMM1	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMINSD %XMM13,%XMM11,%XMM14	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM13,%XMM12,%XMM15	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVSD 0x28(%RSI),%XMM2	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMINSD %XMM1,%XMM14,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM1,%XMM15,%XMM8	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVSD 0x30(%RSI),%XMM11	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMINSD %XMM2,%XMM0,%XMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM2,%XMM8,%XMM10	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VMOVSD 0x38(%RSI),%XMM15	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (12.5%)
VMINSD %XMM11,%XMM9,%XMM12	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM11,%XMM10,%XMM14	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
ADD $0x40,%RSI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
VMINSD %XMM15,%XMM12,%XMM13	1	0.50	0.50	0	0	0	0	0	0	4	0.50	scal (12.5%)
VADDSD %XMM15,%XMM14,%XMM14	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
CMP %RSI,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JNE 4d38b6 <hypre_BoomerAMGCreateS._omp_fn.1+0x9e6>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code