OV - exec - Loop 104

	Loop Id: 104	Module: exec	Source: par_coarsen.c:2528-2540	Coverage: 0.07%

0x42e843 MOV	(%RAX),%RDX    [12]

0x42e846 CMPQ	$0,(%R12,%RDX,8)    [13]

0x42e84b JNE	42efa0

0x42e851 LEA	0x8(%RAX),%RDX

0x42e855 MOV	0x8(%RAX),%RAX    [12]

0x42e859 INC	%RSI

0x42e85c CMPQ	$0,(%R12,%RAX,8)    [13]

0x42e861 MOV	$0x1,%R9D

0x42e867 JE	42efbb

0x42e86d MOVQ	$0,(%R8,%RAX,8)    [1]

0x42e875 MOV	0x8(%RDX),%RAX    [3]

0x42e879 CMPQ	$0,(%R12,%RAX,8)    [13]

0x42e87e JE	42efd3

0x42e884 MOVQ	$0,(%R8,%RAX,8)    [1]

0x42e88c MOV	0x10(%RDX),%RAX    [5]

0x42e890 CMPQ	$0,(%R12,%RAX,8)    [13]

0x42e895 JE	42efeb

0x42e89b MOVQ	$0,(%R8,%RAX,8)    [1]

0x42e8a3 MOV	0x18(%RDX),%RAX    [7]

0x42e8a7 CMPQ	$0,(%R12,%RAX,8)    [13]

0x42e8ac JE	42f003

0x42e8b2 MOVQ	$0,(%R8,%RAX,8)    [1]

0x42e8ba MOV	0x20(%RDX),%RAX    [9]

0x42e8be CMPQ	$0,(%R12,%RAX,8)    [13]

0x42e8c3 JE	42f01b

0x42e8c9 MOVQ	$0,(%R8,%RAX,8)    [1]

0x42e8d1 MOV	0x28(%RDX),%RAX    [11]

0x42e8d5 CMPQ	$0,(%R12,%RAX,8)    [13]

0x42e8da JE	42f033

0x42e8e0 MOVQ	$0,(%R8,%RAX,8)    [1]

0x42e8e8 MOV	0x30(%RDX),%RAX    [15]

0x42e8ec CMPQ	$0,(%R12,%RAX,8)    [13]

0x42e8f1 JE	42f04b

0x42e8f7 MOVQ	$0,(%R8,%RAX,8)    [1]

0x42e8ff LEA	0x38(%RDX),%RAX

0x42e903 CMP	%RAX,%RDI

0x42e906 JNE	42e843

0x42efa0 MOVQ	$0,(%R8,%RDX,8)    [1]

0x42efa8 LEA	0x8(%RAX),%RDX

0x42efac MOV	0x8(%RAX),%RAX    [12]

0x42efb0 CMPQ	$0,(%R12,%RAX,8)    [13]

0x42efb5 JNE	42e86d

0x42efbb MOV	0x8(%RDX),%RAX    [2]

0x42efbf INC	%RSI

0x42efc2 CMPQ	$0,(%R12,%RAX,8)    [13]

0x42efc7 MOV	$0x1,%R9D

0x42efcd JNE	42e884

0x42efd3 MOV	0x10(%RDX),%RAX    [4]

0x42efd7 INC	%RSI

0x42efda CMPQ	$0,(%R12,%RAX,8)    [13]

0x42efdf MOV	$0x1,%R9D

0x42efe5 JNE	42e89b

0x42efeb MOV	0x18(%RDX),%RAX    [6]

0x42efef INC	%RSI

0x42eff2 CMPQ	$0,(%R12,%RAX,8)    [13]

0x42eff7 MOV	$0x1,%R9D

0x42effd JNE	42e8b2

0x42f003 MOV	0x20(%RDX),%RAX    [8]

0x42f007 INC	%RSI

0x42f00a CMPQ	$0,(%R12,%RAX,8)    [13]

0x42f00f MOV	$0x1,%R9D

0x42f015 JNE	42e8c9

0x42f01b MOV	0x28(%RDX),%RAX    [10]

0x42f01f INC	%RSI

0x42f022 CMPQ	$0,(%R12,%RAX,8)    [13]

0x42f027 MOV	$0x1,%R9D

0x42f02d JNE	42e8e0

0x42f033 MOV	0x30(%RDX),%RAX    [14]

0x42f037 INC	%RSI

0x42f03a CMPQ	$0,(%R12,%RAX,8)    [13]

0x42f03f MOV	$0x1,%R9D

0x42f045 JNE	42e8f7

0x42f04b INC	%RSI

0x42f04e MOV	$0x1,%R9D

0x42f054 JMP	42e8ff

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2528 - 2540

--------------------------------------------------------------------------------

2528:         for (ig = ig_begin; ig < ig_end; ig++)

2529:         {

2530:            i = graph_array[ig];

2531:

2532:            if (CF_marker[i]!=0) /* C or F point */

2533:            {

2534:               /* the independent set subroutine needs measure 0 for

2535:                  removed nodes */

2536:               measure_array[i] = 0;

2537:            }

2538:            else

2539:            {

2540:               private_graph_size_cnt++;

Coverage (%)	Name	Source Location	Module
○97.93	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.07	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.19
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.8
Source	par_coarsen.c:2528-2540
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.50
CQA cycles if no scalar integer	12.50
CQA cycles if FP arith vectorized	12.50
CQA cycles if fully vectorized	0.95
Front-end cycles	12.50
P0 cycles	8.00
P1 cycles	8.00
P2 cycles	10.00
P3 cycles	10.00
P4 cycles	4.00
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	8.00
P11 cycles	10.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	75.00
Nb uops	75.00
Nb loads	30.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.32
Bytes prefetched	0.00
Bytes loaded	240.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.38
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.42

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.19
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.8
Source	par_coarsen.c:2528-2540
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.50
CQA cycles if no scalar integer	12.50
CQA cycles if FP arith vectorized	12.50
CQA cycles if fully vectorized	0.95
Front-end cycles	12.50
P0 cycles	8.00
P1 cycles	8.00
P2 cycles	10.00
P3 cycles	10.00
P4 cycles	4.00
P5 cycles	8.00
P6 cycles	8.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	8.00
P11 cycles	10.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	75.00
Nb uops	75.00
Nb loads	30.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.32
Bytes prefetched	0.00
Bytes loaded	240.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.38
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.42

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.8
Source file and lines	par_coarsen.c:2528-2540
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2528-2540.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 256 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 12.50 to 0.95 cycles (13.19x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 240 bytes. The binary loop is storing 64 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	75
nb uops	75
loop length	386
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.50 cycles
front end	12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.00	8.00	10.00	10.00	4.00	8.00	8.00	4.00	4.00	4.00	8.00	10.00
cycles	8.00	8.00	10.00	10.00	4.00	8.00	8.00	4.00	4.00	4.00	8.00	10.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.50
Dispatch	10.00
Overall L1	12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles. At this rate:

10% of peak load performance is reached (19.20 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.50 to 10.00 cycles (1.25x speedup).

ASM code

In the binary file, the address of the loop is: 42e843

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%RAX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,(%R12,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 42efa0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x940>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x8(%RAX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x8(%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 42efbb <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x95b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x8(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 42efd3 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x973>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x10(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 42efeb <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x98b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x18(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 42f003 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x9a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x20(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 42f01b <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x9bb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x28(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 42f033 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x9d3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x30(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 42f04b <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x9eb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x38(%RDX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 42e843 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x1e3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%R8,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x8(%RAX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x8(%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 42e86d <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x20d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x8(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 42e884 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x224>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x10(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 42e89b <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x23b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 42e8b2 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x252>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x20(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 42e8c9 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x269>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x28(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 42e8e0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x280>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x30(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 42e8f7 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x297>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JMP 42e8ff <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x29f>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	hypre_BoomerAMGCoarsenPMIS._omp_fn.8
Source file and lines	par_coarsen.c:2528-2540
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 256 paths individually, rerun with max-paths=256
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 240 bytes. The binary loop is storing 64 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	75
nb uops	75
loop length	386
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.50 cycles
front end	12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.00	8.00	10.00	10.00	4.00	8.00	8.00	4.00	4.00	4.00	8.00	10.00
cycles	8.00	8.00	10.00	10.00	4.00	8.00	8.00	4.00	4.00	4.00	8.00	10.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.50
Dispatch	10.00
Overall L1	12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles. At this rate:

10% of peak load performance is reached (19.20 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 42e843

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV (%RAX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,(%R12,%RDX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 42efa0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x940>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x8(%RAX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x8(%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 42efbb <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x95b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x8(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 42efd3 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x973>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x10(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 42efeb <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x98b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x18(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 42f003 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x9a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x20(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 42f01b <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x9bb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x28(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 42f033 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x9d3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x30(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 42f04b <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x9eb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%R8,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x38(%RDX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 42e843 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x1e3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,(%R8,%RDX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x8(%RAX),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x8(%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 42e86d <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x20d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x8(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 42e884 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x224>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x10(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 42e89b <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x23b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x18(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 42e8b2 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x252>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x20(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 42e8c9 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x269>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x28(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 42e8e0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x280>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x30(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMPQ $0,(%R12,%RAX,8)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JNE 42e8f7 <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x297>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JMP 42e8ff <hypre_BoomerAMGCoarsenPMIS._omp_fn.8+0x29f>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code