OV - exec - Function hypre_CSRMatrixMatvecT._omp

	Function: hypre_CSRMatrixMatvecT._omp_fn.3	Module: exec	Source: csr_matvec.c:554-579 [...]	Coverage (incl. loops): 1.26% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 554 - 579

--------------------------------------------------------------------------------

554: #pragma omp parallel private(i,jj,j,my_thread_num,offset)

555: #endif

556:          {

557:             my_thread_num = hypre_GetThreadNum();

558:             offset =  y_size*my_thread_num;

[...]

564:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

565:                {

566:                   j = A_j[jj];

567:                   y_data_expand[offset + j] += A_data[jj] * x_data[i];

[...]

577:                for (j = 0; j < num_threads; j++)

578:                {

579:                   y_data[i] += y_data_expand[j*y_size + i];

0x546410 PUSH	%RBP

0x546411 MOV	%RSP,%RBP

0x546414 PUSH	%R15

0x546416 PUSH	%R14

0x546418 PUSH	%R13

0x54641a PUSH	%R12

0x54641c PUSH	%RBX

0x54641d SUB	$0x38,%RSP

0x546421 MOV	0x28(%RDI),%RDX

0x546425 MOV	0x10(%RDI),%RSI

0x546429 MOV	0x20(%RDI),%R10

0x54642d MOV	0x30(%RDI),%RAX

0x546431 MOV	0x18(%RDI),%R15

0x546435 MOV	0x40(%RDI),%R13

0x546439 MOV	0x38(%RDI),%RBX

0x54643d MOV	0x8(%RDI),%R14

0x546441 MOV	(%RDI),%RDI

0x546444 MOV	%RDX,-0x60(%RBP)

0x546448 MOV	%RSI,-0x50(%RBP)

0x54644c MOV	%R10,-0x58(%RBP)

0x546450 MOV	%RDI,-0x48(%RBP)

0x546454 MOV	%RAX,-0x40(%RBP)

0x546458 CALL	555090 <hypre_GetThreadNum>

0x54645d MOV	%RAX,%R12

0x546460 CALL	4110b0 <omp_get_num_threads@plt>

0x546465 CLTQ

0x546467 MOV	%RAX,-0x38(%RBP)

0x54646b CALL	4111f0 <omp_get_thread_num@plt>

0x546470 MOVSXD	%EAX,%R9

0x546473 MOV	%R15,%RAX

0x546476 CQTO

0x546478 IDIVQ	-0x38(%RBP)

0x54647c MOV	-0x48(%RBP),%R11

0x546480 MOV	-0x50(%RBP),%RSI

0x546484 MOV	-0x58(%RBP),%R8

0x546488 CMP	%RDX,%R9

0x54648b MOV	%RAX,%RCX

0x54648e JL	5468d0

0x546494 MOV	%RCX,%R10

0x546497 IMUL	%R9,%R10

0x54649b ADD	%R10,%RDX

0x54649e ADD	%RDX,%RCX

0x5464a1 CMP	%RCX,%RDX

0x5464a4 JGE	54672f

0x5464aa MOV	-0x40(%RBP),%R15

0x5464ae SAL	$0x3,%RDX

0x5464b2 IMUL	%R15,%R12

0x5464b6 ADD	%RDX,%R14

0x5464b9 LEA	(%R8,%RCX,8),%RDI

0x5464bd ADD	%R8,%RDX

(2945) 0x5464c0 MOV	(%R14),%RAX

(2945) 0x5464c3 MOV	0x8(%R14),%R8

(2945) 0x5464c7 CMP	%R8,%RAX

(2945) 0x5464ca JGE	54671e

(2945) 0x5464d0 MOV	%R8,%RCX

(2945) 0x5464d3 SUB	%RAX,%RCX

(2945) 0x5464d6 AND	$0x7,%ECX

(2945) 0x5464d9 JE	546609

(2945) 0x5464df CMP	$0x1,%RCX

(2945) 0x5464e3 JE	5465dd

(2945) 0x5464e9 CMP	$0x2,%RCX

(2945) 0x5464ed JE	5465bc

(2945) 0x5464f3 CMP	$0x3,%RCX

(2945) 0x5464f7 JE	546599

(2945) 0x5464fd CMP	$0x4,%RCX

(2945) 0x546501 JE	546576

(2945) 0x546503 CMP	$0x5,%RCX

(2945) 0x546507 JE	546555

(2945) 0x546509 CMP	$0x6,%RCX

(2945) 0x54650d JE	546532

(2945) 0x54650f MOV	(%RSI,%RAX,8),%R10

(2945) 0x546513 VMOVSD	(%R11,%RAX,8),%XMM0

(2945) 0x546519 ADD	%R12,%R10

(2945) 0x54651c LEA	(%RBX,%R10,8),%R15

(2945) 0x546520 VMOVSD	(%R15),%XMM7

(2945) 0x546525 INC	%RAX

(2945) 0x546528 VFMADD132SD	(%RDX),%XMM7,%XMM0

(2945) 0x54652d VMOVSD	%XMM0,(%R15)

(2945) 0x546532 MOV	(%RSI,%RAX,8),%RCX

(2945) 0x546536 VMOVSD	(%R11,%RAX,8),%XMM1

(2945) 0x54653c ADD	%R12,%RCX

(2945) 0x54653f LEA	(%RBX,%RCX,8),%R10

(2945) 0x546543 VMOVSD	(%R10),%XMM2

(2945) 0x546548 INC	%RAX

(2945) 0x54654b VFMADD132SD	(%RDX),%XMM2,%XMM1

(2945) 0x546550 VMOVSD	%XMM1,(%R10)

(2945) 0x546555 MOV	(%RSI,%RAX,8),%R15

(2945) 0x546559 VMOVSD	(%R11,%RAX,8),%XMM3

(2945) 0x54655f ADD	%R12,%R15

(2945) 0x546562 LEA	(%RBX,%R15,8),%RCX

(2945) 0x546566 VMOVSD	(%RCX),%XMM6

(2945) 0x54656a INC	%RAX

(2945) 0x54656d VFMADD132SD	(%RDX),%XMM6,%XMM3

(2945) 0x546572 VMOVSD	%XMM3,(%RCX)

(2945) 0x546576 MOV	(%RSI,%RAX,8),%R10

(2945) 0x54657a VMOVSD	(%R11,%RAX,8),%XMM4

(2945) 0x546580 ADD	%R12,%R10

(2945) 0x546583 LEA	(%RBX,%R10,8),%R15

(2945) 0x546587 VMOVSD	(%R15),%XMM5

(2945) 0x54658c INC	%RAX

(2945) 0x54658f VFMADD132SD	(%RDX),%XMM5,%XMM4

(2945) 0x546594 VMOVSD	%XMM4,(%R15)

(2945) 0x546599 MOV	(%RSI,%RAX,8),%RCX

(2945) 0x54659d VMOVSD	(%R11,%RAX,8),%XMM8

(2945) 0x5465a3 ADD	%R12,%RCX

(2945) 0x5465a6 LEA	(%RBX,%RCX,8),%R10

(2945) 0x5465aa VMOVSD	(%R10),%XMM9

(2945) 0x5465af INC	%RAX

(2945) 0x5465b2 VFMADD132SD	(%RDX),%XMM9,%XMM8

(2945) 0x5465b7 VMOVSD	%XMM8,(%R10)

(2945) 0x5465bc MOV	(%RSI,%RAX,8),%R15

(2945) 0x5465c0 VMOVSD	(%R11,%RAX,8),%XMM10

(2945) 0x5465c6 ADD	%R12,%R15

(2945) 0x5465c9 LEA	(%RBX,%R15,8),%RCX

(2945) 0x5465cd VMOVSD	(%RCX),%XMM11

(2945) 0x5465d1 INC	%RAX

(2945) 0x5465d4 VFMADD132SD	(%RDX),%XMM11,%XMM10

(2945) 0x5465d9 VMOVSD	%XMM10,(%RCX)

(2945) 0x5465dd MOV	(%RSI,%RAX,8),%R10

(2945) 0x5465e1 VMOVSD	(%R11,%RAX,8),%XMM12

(2945) 0x5465e7 ADD	%R12,%R10

(2945) 0x5465ea LEA	(%RBX,%R10,8),%R15

(2945) 0x5465ee VMOVSD	(%R15),%XMM13

(2945) 0x5465f3 INC	%RAX

(2945) 0x5465f6 VFMADD132SD	(%RDX),%XMM13,%XMM12

(2945) 0x5465fb VMOVSD	%XMM12,(%R15)

(2945) 0x546600 CMP	%R8,%RAX

(2945) 0x546603 JE	54671e

  (2946) 0x546609 MOV	(%RSI,%RAX,8),%RCX

  (2946) 0x54660d VMOVSD	(%R11,%RAX,8),%XMM14

  (2946) 0x546613 ADD	%R12,%RCX

  (2946) 0x546616 LEA	(%RBX,%RCX,8),%R10

  (2946) 0x54661a VMOVSD	(%R10),%XMM15

  (2946) 0x54661f MOV	0x8(%RSI,%RAX,8),%R15

  (2946) 0x546624 VFMADD132SD	(%RDX),%XMM15,%XMM14

  (2946) 0x546629 ADD	%R12,%R15

  (2946) 0x54662c LEA	(%RBX,%R15,8),%RCX

  (2946) 0x546630 VMOVSD	%XMM14,(%R10)

  (2946) 0x546635 VMOVSD	0x8(%R11,%RAX,8),%XMM0

  (2946) 0x54663c VMOVSD	(%RCX),%XMM7

  (2946) 0x546640 MOV	0x10(%RSI,%RAX,8),%R10

  (2946) 0x546645 VFMADD132SD	(%RDX),%XMM7,%XMM0

  (2946) 0x54664a ADD	%R12,%R10

  (2946) 0x54664d LEA	(%RBX,%R10,8),%R15

  (2946) 0x546651 VMOVSD	%XMM0,(%RCX)

  (2946) 0x546655 VMOVSD	0x10(%R11,%RAX,8),%XMM1

  (2946) 0x54665c VMOVSD	(%R15),%XMM2

  (2946) 0x546661 MOV	0x18(%RSI,%RAX,8),%RCX

  (2946) 0x546666 VFMADD132SD	(%RDX),%XMM2,%XMM1

  (2946) 0x54666b ADD	%R12,%RCX

  (2946) 0x54666e LEA	(%RBX,%RCX,8),%R10

  (2946) 0x546672 VMOVSD	%XMM1,(%R15)

  (2946) 0x546677 VMOVSD	0x18(%R11,%RAX,8),%XMM3

  (2946) 0x54667e VMOVSD	(%R10),%XMM6

  (2946) 0x546683 MOV	0x20(%RSI,%RAX,8),%R15

  (2946) 0x546688 VFMADD132SD	(%RDX),%XMM6,%XMM3

  (2946) 0x54668d ADD	%R12,%R15

  (2946) 0x546690 LEA	(%RBX,%R15,8),%RCX

  (2946) 0x546694 VMOVSD	%XMM3,(%R10)

  (2946) 0x546699 VMOVSD	0x20(%R11,%RAX,8),%XMM4

  (2946) 0x5466a0 VMOVSD	(%RCX),%XMM5

  (2946) 0x5466a4 MOV	0x28(%RSI,%RAX,8),%R10

  (2946) 0x5466a9 VFMADD132SD	(%RDX),%XMM5,%XMM4

  (2946) 0x5466ae ADD	%R12,%R10

  (2946) 0x5466b1 LEA	(%RBX,%R10,8),%R15

  (2946) 0x5466b5 VMOVSD	%XMM4,(%RCX)

  (2946) 0x5466b9 VMOVSD	0x28(%R11,%RAX,8),%XMM8

  (2946) 0x5466c0 VMOVSD	(%R15),%XMM9

  (2946) 0x5466c5 MOV	0x30(%RSI,%RAX,8),%RCX

  (2946) 0x5466ca VFMADD132SD	(%RDX),%XMM9,%XMM8

  (2946) 0x5466cf ADD	%R12,%RCX

  (2946) 0x5466d2 LEA	(%RBX,%RCX,8),%R10

  (2946) 0x5466d6 VMOVSD	%XMM8,(%R15)

  (2946) 0x5466db VMOVSD	0x30(%R11,%RAX,8),%XMM10

  (2946) 0x5466e2 VMOVSD	(%R10),%XMM11

  (2946) 0x5466e7 MOV	0x38(%RSI,%RAX,8),%R15

  (2946) 0x5466ec VFMADD132SD	(%RDX),%XMM11,%XMM10

  (2946) 0x5466f1 ADD	%R12,%R15

  (2946) 0x5466f4 LEA	(%RBX,%R15,8),%RCX

  (2946) 0x5466f8 VMOVSD	%XMM10,(%R10)

  (2946) 0x5466fd VMOVSD	0x38(%R11,%RAX,8),%XMM12

  (2946) 0x546704 VMOVSD	(%RCX),%XMM13

  (2946) 0x546708 ADD	$0x8,%RAX

  (2946) 0x54670c VFMADD132SD	(%RDX),%XMM13,%XMM12

  (2946) 0x546711 VMOVSD	%XMM12,(%RCX)

  (2946) 0x546715 CMP	%R8,%RAX

  (2946) 0x546718 JNE	546609

(2945) 0x54671e ADD	$0x8,%RDX

(2945) 0x546722 ADD	$0x8,%R14

(2945) 0x546726 CMP	%RDX,%RDI

(2945) 0x546729 JNE	5464c0

0x54672f MOV	%R9,-0x48(%RBP)

0x546733 CALL	411290 <GOMP_barrier@plt>

0x546738 MOV	-0x40(%RBP),%RAX

0x54673c MOV	-0x48(%RBP),%R14

0x546740 CQTO

0x546742 IDIVQ	-0x38(%RBP)

0x546746 CMP	%RDX,%R14

0x546749 JL	5468c6

0x54674f IMUL	%RAX,%R14

0x546753 ADD	%R14,%RDX

0x546756 ADD	%RDX,%RAX

0x546759 CMP	%RAX,%RDX

0x54675c JGE	5468b3

0x546762 TEST	%R13,%R13

0x546765 JLE	5468b3

0x54676b MOV	-0x60(%RBP),%R11

0x54676f LEA	(,%RDX,8),%R12

0x546777 ADD	%R12,%R11

0x54677a ADD	%RBX,%R12

0x54677d MOV	-0x40(%RBP),%RBX

0x546781 SAL	$0x3,%RBX

0x546785 NOPL	(%RAX)

(2944) 0x546788 MOV	%R13,%R9

(2944) 0x54678b VMOVSD	(%R11),%XMM14

(2944) 0x546790 MOV	%R12,%RDI

(2944) 0x546793 XOR	%ESI,%ESI

(2944) 0x546795 AND	$0x7,%R9D

(2944) 0x546799 JE	546836

(2944) 0x54679f CMP	$0x1,%R9

(2944) 0x5467a3 JE	546822

(2944) 0x5467a5 CMP	$0x2,%R9

(2944) 0x5467a9 JE	546813

(2944) 0x5467ab CMP	$0x3,%R9

(2944) 0x5467af JE	546804

(2944) 0x5467b1 CMP	$0x4,%R9

(2944) 0x5467b5 JE	5467f5

(2944) 0x5467b7 CMP	$0x5,%R9

(2944) 0x5467bb JE	5467e6

(2944) 0x5467bd CMP	$0x6,%R9

(2944) 0x5467c1 JE	5467d7

(2944) 0x5467c3 VADDSD	(%R12),%XMM14,%XMM14

(2944) 0x5467c9 MOV	$0x1,%ESI

(2944) 0x5467ce LEA	(%R12,%RBX,1),%RDI

(2944) 0x5467d2 VMOVSD	%XMM14,(%R11)

(2944) 0x5467d7 VADDSD	(%RDI),%XMM14,%XMM14

(2944) 0x5467db INC	%RSI

(2944) 0x5467de ADD	%RBX,%RDI

(2944) 0x5467e1 VMOVSD	%XMM14,(%R11)

(2944) 0x5467e6 VADDSD	(%RDI),%XMM14,%XMM14

(2944) 0x5467ea INC	%RSI

(2944) 0x5467ed ADD	%RBX,%RDI

(2944) 0x5467f0 VMOVSD	%XMM14,(%R11)

(2944) 0x5467f5 VADDSD	(%RDI),%XMM14,%XMM14

(2944) 0x5467f9 INC	%RSI

(2944) 0x5467fc ADD	%RBX,%RDI

(2944) 0x5467ff VMOVSD	%XMM14,(%R11)

(2944) 0x546804 VADDSD	(%RDI),%XMM14,%XMM14

(2944) 0x546808 INC	%RSI

(2944) 0x54680b ADD	%RBX,%RDI

(2944) 0x54680e VMOVSD	%XMM14,(%R11)

(2944) 0x546813 VADDSD	(%RDI),%XMM14,%XMM14

(2944) 0x546817 INC	%RSI

(2944) 0x54681a ADD	%RBX,%RDI

(2944) 0x54681d VMOVSD	%XMM14,(%R11)

(2944) 0x546822 VADDSD	(%RDI),%XMM14,%XMM14

(2944) 0x546826 INC	%RSI

(2944) 0x546829 ADD	%RBX,%RDI

(2944) 0x54682c VMOVSD	%XMM14,(%R11)

(2944) 0x546831 CMP	%RSI,%R13

(2944) 0x546834 JE	54689f

  (2943) 0x546836 VADDSD	(%RDI),%XMM14,%XMM15

  (2943) 0x54683a ADD	%RBX,%RDI

  (2943) 0x54683d ADD	$0x8,%RSI

  (2943) 0x546841 VMOVSD	%XMM15,(%R11)

  (2943) 0x546846 VADDSD	(%RDI),%XMM15,%XMM0

  (2943) 0x54684a ADD	%RBX,%RDI

  (2943) 0x54684d VMOVSD	%XMM0,(%R11)

  (2943) 0x546852 VADDSD	(%RDI),%XMM0,%XMM7

  (2943) 0x546856 ADD	%RBX,%RDI

  (2943) 0x546859 VMOVSD	%XMM7,(%R11)

  (2943) 0x54685e VADDSD	(%RDI),%XMM7,%XMM1

  (2943) 0x546862 ADD	%RBX,%RDI

  (2943) 0x546865 VMOVSD	%XMM1,(%R11)

  (2943) 0x54686a VADDSD	(%RDI),%XMM1,%XMM2

  (2943) 0x54686e ADD	%RBX,%RDI

  (2943) 0x546871 VMOVSD	%XMM2,(%R11)

  (2943) 0x546876 VADDSD	(%RDI),%XMM2,%XMM3

  (2943) 0x54687a ADD	%RBX,%RDI

  (2943) 0x54687d VMOVSD	%XMM3,(%R11)

  (2943) 0x546882 VADDSD	(%RDI),%XMM3,%XMM6

  (2943) 0x546886 ADD	%RBX,%RDI

  (2943) 0x546889 VMOVSD	%XMM6,(%R11)

  (2943) 0x54688e VADDSD	(%RDI),%XMM6,%XMM14

  (2943) 0x546892 ADD	%RBX,%RDI

  (2943) 0x546895 VMOVSD	%XMM14,(%R11)

  (2943) 0x54689a CMP	%RSI,%R13

  (2943) 0x54689d JNE	546836

(2944) 0x54689f INC	%RDX

(2944) 0x5468a2 ADD	$0x8,%R11

(2944) 0x5468a6 ADD	$0x8,%R12

(2944) 0x5468aa CMP	%RDX,%RAX

(2944) 0x5468ad JNE	546788

0x5468b3 ADD	$0x38,%RSP

0x5468b7 POP	%RBX

0x5468b8 POP	%R12

0x5468ba POP	%R13

0x5468bc POP	%R14

0x5468be POP	%R15

0x5468c0 POP	%RBP

0x5468c1 JMP	411290

0x5468c6 INC	%RAX

0x5468c9 XOR	%EDX,%EDX

0x5468cb JMP	54674f

0x5468d0 INC	%RCX

0x5468d3 XOR	%EDX,%EDX

0x5468d5 JMP	546494

0x5468da NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○97.69	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.31	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	csr_matvec.c:554-579
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554-558,564-567,577-579.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 20.00 to 16.50 cycles (1.21x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 15.17 cycles (1.32x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

GOMP_barrier@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:557
omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
CQTO: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 152 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	87
nb uops	99
loop length	310
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.50 cycles
front end	16.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.10	9.00	8.33	8.33	8.50	6.00	5.90	8.50	8.50	8.50	6.00	8.33
cycles	6.10	12.43	8.33	8.33	8.50	6.00	5.90	8.50	8.50	8.50	6.00	8.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

20.00

Cycles summary

Front-end	16.50
Dispatch	12.43
DIV/SQRT	20.00
Overall L1	20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

3% of peak load performance is reached (7.60 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.80 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 546410

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x28(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RDI),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RDI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x40(%RDI),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%RDI),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RDI),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RDI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 555090 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4110b0 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4111f0 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOVSXD %EAX,%R9	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIVQ -0x38(%RBP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	10	scal (12.5%)
MOV -0x48(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x58(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JL 5468d0 <hypre_CSRMatrixMatvecT._omp_fn.3+0x4c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R9,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %R10,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 54672f <hypre_CSRMatrixMatvecT._omp_fn.3+0x31f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x40(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
IMUL %R15,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
LEA (%R8,%RCX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIVQ -0x38(%RBP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	10	scal (12.5%)
CMP %RDX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 5468c6 <hypre_CSRMatrixMatvecT._omp_fn.3+0x4b6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %RAX,%R14	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %R14,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 5468b3 <hypre_CSRMatrixMatvecT._omp_fn.3+0x4a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %R13,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 5468b3 <hypre_CSRMatrixMatvecT._omp_fn.3+0x4a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x60(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (,%RDX,8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R12,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
ADD %RBX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x40(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
SAL $0x3,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 411290 <GOMP_barrier@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 54674f <hypre_CSRMatrixMatvecT._omp_fn.3+0x33f>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 546494 <hypre_CSRMatrixMatvecT._omp_fn.3+0x84>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	csr_matvec.c:554-579
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554-558,564-567,577-579.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 15.17 cycles (1.32x speedup).

CALL instructions

Detected function call instructions.

Details

GOMP_barrier@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:557
omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
CQTO: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 152 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	87
nb uops	99
loop length	310
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.50 cycles
front end	16.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.10	9.00	8.33	8.33	8.50	6.00	5.90	8.50	8.50	8.50	6.00	8.33
cycles	6.10	12.43	8.33	8.33	8.50	6.00	5.90	8.50	8.50	8.50	6.00	8.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

20.00

Cycles summary

Front-end	16.50
Dispatch	12.43
DIV/SQRT	20.00
Overall L1	20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

3% of peak load performance is reached (7.60 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.80 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 546410

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x28(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RDI),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RDI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x40(%RDI),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%RDI),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RDI),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RDI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 555090 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4110b0 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4111f0 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOVSXD %EAX,%R9	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIVQ -0x38(%RBP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	10	scal (12.5%)
MOV -0x48(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x58(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JL 5468d0 <hypre_CSRMatrixMatvecT._omp_fn.3+0x4c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R9,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %R10,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 54672f <hypre_CSRMatrixMatvecT._omp_fn.3+0x31f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x40(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
IMUL %R15,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
LEA (%R8,%RCX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIVQ -0x38(%RBP)	5	0	3	0.33	0.33	0	0	0	0	0	0	0	0.33	11-16	10	scal (12.5%)
CMP %RDX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 5468c6 <hypre_CSRMatrixMatvecT._omp_fn.3+0x4b6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %RAX,%R14	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %R14,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 5468b3 <hypre_CSRMatrixMatvecT._omp_fn.3+0x4a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %R13,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 5468b3 <hypre_CSRMatrixMatvecT._omp_fn.3+0x4a3>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x60(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (,%RDX,8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R12,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
ADD %RBX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x40(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
SAL $0x3,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 411290 <GOMP_barrier@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 54674f <hypre_CSRMatrixMatvecT._omp_fn.3+0x33f>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
INC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 546494 <hypre_CSRMatrixMatvecT._omp_fn.3+0x84>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecT._omp_fn.3–	1.26	0.54
▼Loop 2945 - csr_matvec.c:564-567 - exec–	1.19	0.45
○Loop 2946 - csr_matvec.c:564-567 - exec	0.02	0.01
▼Loop 2944 - csr_matvec.c:577-579 - exec–	0.00	0.01
○Loop 2943 - csr_matvec.c:577-579 - exec	0.04	0.02

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code