OV - exec - Function hypre_CSRMatrixMatvecOutOfPlace._omp

	Function: hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6	Module: exec	Source: csr_matvec.c:243-404 [...]	Coverage (incl. loops): 24.02% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 243 - 404

--------------------------------------------------------------------------------

243: #pragma omp parallel private(i,jj,tempx)

244: #endif

245:       {

246:       HYPRE_Int iBegin = hypre_CSRMatrixGetLoadBalancedPartitionBegin(A);

247:       HYPRE_Int iEnd = hypre_CSRMatrixGetLoadBalancedPartitionEnd(A);

248:       hypre_assert(iBegin <= iEnd);

249:       hypre_assert(iBegin >= 0 && iBegin <= num_rows);

250:       hypre_assert(iEnd >= 0 && iEnd <= num_rows);

251:

252:       if (0 == temp)

253:       {

254:          if (1 == alpha) // JSP: a common path

255:          {

256:             for (i = iBegin; i < iEnd; i++)

257:             {

258:                tempx = 0.0;

259:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

260:                {

261:                   tempx += A_data[jj] * x_data[A_j[jj]];

262:                }

263:                y_data[i] = tempx;

264:             }

265:          } // y = A*x

266:          else if (-1 == alpha)

267:          {

268:             for (i = iBegin; i < iEnd; i++)

269:             {

270:                tempx = 0.0;

271:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

272:                {

273:                   tempx -= A_data[jj] * x_data[A_j[jj]];

274:                }

275:                y_data[i] = tempx;

276:             }

277:          } // y = -A*x

278:          else

279:          {

280:             for (i = iBegin; i < iEnd; i++)

281:             {

282:                tempx = 0.0;

283:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

284:                {

285:                   tempx += A_data[jj] * x_data[A_j[jj]];

286:                }

287:                y_data[i] = alpha*tempx;

288:             }

289:          } // y = alpha*A*x

290:       } // temp == 0

291:       else if (-1 == temp) // beta == -alpha

292:       {

293:          if (1 == alpha) // JSP: a common path

294:          {

295:             for (i = iBegin; i < iEnd; i++)

296:             {

297:                tempx = -b_data[i];

298:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

299:                {

300:                   tempx += A_data[jj] * x_data[A_j[jj]];

301:                }

302:                y_data[i] = tempx;

303:             }

304:          } // y = A*x - y

305:          else if (-1 == alpha) // JSP: a common path

306:          {

307:             for (i = iBegin; i < iEnd; i++)

308:             {

309:                tempx = b_data[i];

310:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

311:                {

312:                   tempx -= A_data[jj] * x_data[A_j[jj]];

313:                }

314:                y_data[i] = tempx;

315:             }

316:          } // y = -A*x + y

317:          else

318:          {

319:             for (i = iBegin; i < iEnd; i++)

320:             {

321:                tempx = -b_data[i];

322:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

323:                {

324:                   tempx += A_data[jj] * x_data[A_j[jj]];

325:                }

326:                y_data[i] = alpha*tempx;

327:             }

328:          } // y = alpha*(A*x - y)

329:       } // temp == -1

330:       else if (1 == temp)

331:       {

332:          if (1 == alpha) // JSP: a common path

333:          {

334:             for (i = iBegin; i < iEnd; i++)

335:             {

336:                tempx = b_data[i];

337:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

338:                {

339:                   tempx += A_data[jj] * x_data[A_j[jj]];

340:                }

341:                y_data[i] = tempx;

342:             }

343:          } // y = A*x + y

344:          else if (-1 == alpha)

345:          {

346:             for (i = iBegin; i < iEnd; i++)

347:             {

348:                tempx = -b_data[i];

349:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

350:                {

351:                   tempx -= A_data[jj] * x_data[A_j[jj]];

352:                }

353:                y_data[i] = tempx;

354:             }

355:          } // y = -A*x - y

356:          else

357:          {

358:             for (i = iBegin; i < iEnd; i++)

359:             {

360:                tempx = b_data[i];

361:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

362:                {

363:                   tempx += A_data[jj] * x_data[A_j[jj]];

364:                }

365:                y_data[i] = alpha*tempx;

[...]

371:          if (1 == alpha) // JSP: a common path

372:          {

373:             for (i = iBegin; i < iEnd; i++)

374:             {

375:                tempx = b_data[i]*temp;

376:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

377:                {

378:                   tempx += A_data[jj] * x_data[A_j[jj]];

379:                }

380:                y_data[i] = tempx;

381:             }

382:          } // y = A*x + temp*y

383:          else if (-1 == alpha)

384:          {

385:             for (i = iBegin; i < iEnd; i++)

386:             {

387:                tempx = -b_data[i]*temp;

388:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

389:                {

390:                   tempx -= A_data[jj] * x_data[A_j[jj]];

391:                }

392:                y_data[i] = tempx;

393:             }

394:          } // y = -A*x - temp*y

395:          else

396:          {

397:             for (i = iBegin; i < iEnd; i++)

398:             {

399:                tempx = b_data[i]*temp;

400:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

401:                {

402:                   tempx += A_data[jj] * x_data[A_j[jj]];

403:                }

404:                y_data[i] = alpha*tempx;

0x5447b0 PUSH	%RBP

0x5447b1 MOV	%RSP,%RBP

0x5447b4 PUSH	%R15

0x5447b6 PUSH	%R14

0x5447b8 PUSH	%R13

0x5447ba PUSH	%R12

0x5447bc PUSH	%RBX

0x5447bd SUB	$0x38,%RSP

0x5447c1 MOV	0x8(%RDI),%RDX

0x5447c5 VMOVSD	0x48(%RDI),%XMM1

0x5447ca MOV	0x38(%RDI),%R11

0x5447ce MOV	0x18(%RDI),%R8

0x5447d2 VMOVSD	(%RDI),%XMM7

0x5447d6 MOV	0x28(%RDI),%RAX

0x5447da MOV	0x40(%RDI),%R15

0x5447de MOV	0x30(%RDI),%RBX

0x5447e2 MOV	0x20(%RDI),%R12

0x5447e6 MOV	0x10(%RDI),%R13

0x5447ea MOV	%RDX,%RDI

0x5447ed MOV	%R11,-0x50(%RBP)

0x5447f1 MOV	%R8,-0x48(%RBP)

0x5447f5 MOV	%RDX,-0x40(%RBP)

0x5447f9 VMOVSD	%XMM1,-0x58(%RBP)

0x5447fe VMOVSD	%XMM7,-0x60(%RBP)

0x544803 MOV	%RAX,-0x38(%RBP)

0x544807 CALL	543310 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>

0x54480c MOV	-0x40(%RBP),%RDI

0x544810 MOV	%RAX,%R14

0x544813 CALL	5433a0 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>

0x544818 CMP	%RAX,%R14

0x54481b MOV	-0x48(%RBP),%R10

0x54481f MOV	-0x50(%RBP),%RDI

0x544823 VMOVSD	-0x58(%RBP),%XMM8

0x544828 MOV	%RAX,%R9

0x54482b JG	5450c0

0x544831 TEST	%R14,%R14

0x544834 JS	545068

0x54483a CMP	%R14,-0x38(%RBP)

0x54483e JL	545068

0x544844 TEST	%R9,%R9

0x544847 JS	545010

0x54484d CMP	%R9,-0x38(%RBP)

0x544851 JL	545010

0x544857 VXORPD	%XMM0,%XMM0,%XMM0

0x54485b VCOMISD	%XMM0,%XMM8

0x54485f JE	544a70

0x544865 VMOVSD	0x15e9b(%RIP),%XMM3

0x54486d VCOMISD	%XMM3,%XMM8

0x544871 JNE	544e18

0x544877 VMOVSD	-0x60(%RBP),%XMM8

0x54487c VCOMISD	0x15e94(%RIP),%XMM8

0x544884 JE	545115

0x54488a VCOMISD	%XMM3,%XMM8

0x54488e JE	54569a

0x544894 CMP	%R9,%R14

0x544897 JGE	544a58

0x54489d VMOVQ	0x162cb(%RIP),%XMM2

0x5448a5 NOPL	(%RAX)

(2938) 0x5448a8 VMOVSD	(%RDI,%R14,8),%XMM0

(2938) 0x5448ae MOV	(%R10,%R14,8),%R11

(2938) 0x5448b2 MOV	0x8(%R10,%R14,8),%RAX

(2938) 0x5448b7 VXORPD	%XMM2,%XMM0,%XMM10

(2938) 0x5448bb CMP	%RAX,%R11

(2938) 0x5448be JGE	544a41

(2938) 0x5448c4 MOV	%RAX,%RCX

(2938) 0x5448c7 SUB	%R11,%RCX

(2938) 0x5448ca AND	$0x7,%ECX

(2938) 0x5448cd JE	544990

(2938) 0x5448d3 CMP	$0x1,%RCX

(2938) 0x5448d7 JE	544973

(2938) 0x5448dd CMP	$0x2,%RCX

(2938) 0x5448e1 JE	54495f

(2938) 0x5448e3 CMP	$0x3,%RCX

(2938) 0x5448e7 JE	54494b

(2938) 0x5448e9 CMP	$0x4,%RCX

(2938) 0x5448ed JE	544937

(2938) 0x5448ef CMP	$0x5,%RCX

(2938) 0x5448f3 JE	544923

(2938) 0x5448f5 CMP	$0x6,%RCX

(2938) 0x5448f9 JE	54490f

(2938) 0x5448fb MOV	(%R12,%R11,8),%RSI

(2938) 0x5448ff VMOVSD	(%R13,%R11,8),%XMM3

(2938) 0x544906 INC	%R11

(2938) 0x544909 VFMADD231SD	(%RBX,%RSI,8),%XMM3,%XMM10

(2938) 0x54490f MOV	(%R12,%R11,8),%R8

(2938) 0x544913 VMOVSD	(%R13,%R11,8),%XMM4

(2938) 0x54491a INC	%R11

(2938) 0x54491d VFMADD231SD	(%RBX,%R8,8),%XMM4,%XMM10

(2938) 0x544923 MOV	(%R12,%R11,8),%RDX

(2938) 0x544927 VMOVSD	(%R13,%R11,8),%XMM5

(2938) 0x54492e INC	%R11

(2938) 0x544931 VFMADD231SD	(%RBX,%RDX,8),%XMM5,%XMM10

(2938) 0x544937 MOV	(%R12,%R11,8),%RCX

(2938) 0x54493b VMOVSD	(%R13,%R11,8),%XMM6

(2938) 0x544942 INC	%R11

(2938) 0x544945 VFMADD231SD	(%RBX,%RCX,8),%XMM6,%XMM10

(2938) 0x54494b MOV	(%R12,%R11,8),%RSI

(2938) 0x54494f VMOVSD	(%R13,%R11,8),%XMM11

(2938) 0x544956 INC	%R11

(2938) 0x544959 VFMADD231SD	(%RBX,%RSI,8),%XMM11,%XMM10

(2938) 0x54495f MOV	(%R12,%R11,8),%R8

(2938) 0x544963 VMOVSD	(%R13,%R11,8),%XMM13

(2938) 0x54496a INC	%R11

(2938) 0x54496d VFMADD231SD	(%RBX,%R8,8),%XMM13,%XMM10

(2938) 0x544973 MOV	(%R12,%R11,8),%RDX

(2938) 0x544977 VMOVSD	(%R13,%R11,8),%XMM14

(2938) 0x54497e INC	%R11

(2938) 0x544981 VFMADD231SD	(%RBX,%RDX,8),%XMM14,%XMM10

(2938) 0x544987 CMP	%RAX,%R11

(2938) 0x54498a JE	544a41

  (2939) 0x544990 MOV	(%R12,%R11,8),%RCX

  (2939) 0x544994 VMOVSD	(%R13,%R11,8),%XMM12

  (2939) 0x54499b LEA	0x1(%R11),%R8

  (2939) 0x54499f VFMADD231SD	(%RBX,%RCX,8),%XMM12,%XMM10

  (2939) 0x5449a5 MOV	(%R12,%R8,8),%RSI

  (2939) 0x5449a9 VMOVSD	(%R13,%R8,8),%XMM15

  (2939) 0x5449b0 LEA	0x2(%R11),%RDX

  (2939) 0x5449b4 MOV	(%R12,%RDX,8),%RCX

  (2939) 0x5449b8 VFMADD231SD	(%RBX,%RSI,8),%XMM15,%XMM10

  (2939) 0x5449be VMOVSD	(%R13,%RDX,8),%XMM9

  (2939) 0x5449c5 LEA	0x3(%R11),%R8

  (2939) 0x5449c9 MOV	(%R12,%R8,8),%RSI

  (2939) 0x5449cd VMOVSD	(%R13,%R8,8),%XMM1

  (2939) 0x5449d4 VFMADD231SD	(%RBX,%RCX,8),%XMM9,%XMM10

  (2939) 0x5449da LEA	0x4(%R11),%RDX

  (2939) 0x5449de MOV	(%R12,%RDX,8),%RCX

  (2939) 0x5449e2 VMOVSD	(%R13,%RDX,8),%XMM7

  (2939) 0x5449e9 LEA	0x5(%R11),%R8

  (2939) 0x5449ed VFMADD231SD	(%RBX,%RSI,8),%XMM1,%XMM10

  (2939) 0x5449f3 VMOVSD	(%R13,%R8,8),%XMM0

  (2939) 0x5449fa MOV	(%R12,%R8,8),%RSI

  (2939) 0x5449fe LEA	0x6(%R11),%RDX

  (2939) 0x544a02 VMOVSD	(%R13,%RDX,8),%XMM3

  (2939) 0x544a09 VFMADD231SD	(%RBX,%RCX,8),%XMM7,%XMM10

  (2939) 0x544a0f MOV	(%R12,%RDX,8),%RCX

  (2939) 0x544a13 LEA	0x7(%R11),%R8

  (2939) 0x544a17 VMOVSD	(%R13,%R8,8),%XMM4

  (2939) 0x544a1e ADD	$0x8,%R11

  (2939) 0x544a22 VFMADD231SD	(%RBX,%RSI,8),%XMM0,%XMM10

  (2939) 0x544a28 MOV	(%R12,%R8,8),%RSI

  (2939) 0x544a2c VFMADD231SD	(%RBX,%RCX,8),%XMM3,%XMM10

  (2939) 0x544a32 VFMADD231SD	(%RBX,%RSI,8),%XMM4,%XMM10

  (2939) 0x544a38 CMP	%RAX,%R11

  (2939) 0x544a3b JNE	544990

(2938) 0x544a41 VMULSD	%XMM10,%XMM8,%XMM10

(2938) 0x544a46 VMOVSD	%XMM10,(%R15,%R14,8)

(2938) 0x544a4c INC	%R14

(2938) 0x544a4f CMP	%R14,%R9

(2938) 0x544a52 JNE	5448a8

0x544a58 ADD	$0x38,%RSP

0x544a5c POP	%RBX

0x544a5d POP	%R12

0x544a5f POP	%R13

0x544a61 POP	%R14

0x544a63 POP	%R15

0x544a65 POP	%RBP

0x544a66 RET

0x544a67 NOPW	(%RAX,%RAX,1)

0x544a70 VMOVSD	-0x60(%RBP),%XMM11

0x544a75 VCOMISD	0x15c9b(%RIP),%XMM11

0x544a7d JNE	544c48

0x544a83 CMP	%R9,%R14

0x544a86 JGE	544a58

0x544a88 NOPL	(%RAX,%RAX,1)

(2920) 0x544a90 MOV	(%R10,%R14,8),%RDI

(2920) 0x544a94 MOV	0x8(%R10,%R14,8),%R11

(2920) 0x544a99 VMOVAPD	%XMM8,%XMM11

(2920) 0x544a9e CMP	%R11,%RDI

(2920) 0x544aa1 JGE	544c24

(2920) 0x544aa7 MOV	%R11,%RDX

(2920) 0x544aaa SUB	%RDI,%RDX

(2920) 0x544aad AND	$0x7,%EDX

(2920) 0x544ab0 JE	544b73

(2920) 0x544ab6 CMP	$0x1,%RDX

(2920) 0x544aba JE	544b56

(2920) 0x544ac0 CMP	$0x2,%RDX

(2920) 0x544ac4 JE	544b42

(2920) 0x544ac6 CMP	$0x3,%RDX

(2920) 0x544aca JE	544b2e

(2920) 0x544acc CMP	$0x4,%RDX

(2920) 0x544ad0 JE	544b1a

(2920) 0x544ad2 CMP	$0x5,%RDX

(2920) 0x544ad6 JE	544b06

(2920) 0x544ad8 CMP	$0x6,%RDX

(2920) 0x544adc JE	544af2

(2920) 0x544ade MOV	(%R12,%RDI,8),%RCX

(2920) 0x544ae2 VMOVSD	(%R13,%RDI,8),%XMM11

(2920) 0x544ae9 INC	%RDI

(2920) 0x544aec VFMADD132SD	(%RBX,%RCX,8),%XMM8,%XMM11

(2920) 0x544af2 MOV	(%R12,%RDI,8),%RAX

(2920) 0x544af6 VMOVSD	(%R13,%RDI,8),%XMM14

(2920) 0x544afd INC	%RDI

(2920) 0x544b00 VFMADD231SD	(%RBX,%RAX,8),%XMM14,%XMM11

(2920) 0x544b06 MOV	(%R12,%RDI,8),%R8

(2920) 0x544b0a VMOVSD	(%R13,%RDI,8),%XMM12

(2920) 0x544b11 INC	%RDI

(2920) 0x544b14 VFMADD231SD	(%RBX,%R8,8),%XMM12,%XMM11

(2920) 0x544b1a MOV	(%R12,%RDI,8),%RSI

(2920) 0x544b1e VMOVSD	(%R13,%RDI,8),%XMM15

(2920) 0x544b25 INC	%RDI

(2920) 0x544b28 VFMADD231SD	(%RBX,%RSI,8),%XMM15,%XMM11

(2920) 0x544b2e MOV	(%R12,%RDI,8),%RDX

(2920) 0x544b32 VMOVSD	(%R13,%RDI,8),%XMM9

(2920) 0x544b39 INC	%RDI

(2920) 0x544b3c VFMADD231SD	(%RBX,%RDX,8),%XMM9,%XMM11

(2920) 0x544b42 MOV	(%R12,%RDI,8),%RCX

(2920) 0x544b46 VMOVSD	(%R13,%RDI,8),%XMM1

(2920) 0x544b4d INC	%RDI

(2920) 0x544b50 VFMADD231SD	(%RBX,%RCX,8),%XMM1,%XMM11

(2920) 0x544b56 MOV	(%R12,%RDI,8),%RAX

(2920) 0x544b5a VMOVSD	(%R13,%RDI,8),%XMM7

(2920) 0x544b61 INC	%RDI

(2920) 0x544b64 VFMADD231SD	(%RBX,%RAX,8),%XMM7,%XMM11

(2920) 0x544b6a CMP	%R11,%RDI

(2920) 0x544b6d JE	544c24

  (2921) 0x544b73 MOV	(%R12,%RDI,8),%R8

  (2921) 0x544b77 VMOVSD	(%R13,%RDI,8),%XMM0

  (2921) 0x544b7e LEA	0x1(%RDI),%RDX

  (2921) 0x544b82 VFMADD231SD	(%RBX,%R8,8),%XMM0,%XMM11

  (2921) 0x544b88 MOV	(%R12,%RDX,8),%RSI

  (2921) 0x544b8c VMOVSD	(%R13,%RDX,8),%XMM3

  (2921) 0x544b93 LEA	0x2(%RDI),%RCX

  (2921) 0x544b97 MOV	(%R12,%RCX,8),%RAX

  (2921) 0x544b9b VFMADD231SD	(%RBX,%RSI,8),%XMM3,%XMM11

  (2921) 0x544ba1 VMOVSD	(%R13,%RCX,8),%XMM4

  (2921) 0x544ba8 LEA	0x3(%RDI),%R8

  (2921) 0x544bac MOV	(%R12,%R8,8),%RDX

  (2921) 0x544bb0 VMOVSD	(%R13,%R8,8),%XMM10

  (2921) 0x544bb7 VFMADD231SD	(%RBX,%RAX,8),%XMM4,%XMM11

  (2921) 0x544bbd LEA	0x4(%RDI),%RCX

  (2921) 0x544bc1 MOV	(%R12,%RCX,8),%RSI

  (2921) 0x544bc5 VMOVSD	(%R13,%RCX,8),%XMM2

  (2921) 0x544bcc LEA	0x5(%RDI),%RAX

  (2921) 0x544bd0 VFMADD231SD	(%RBX,%RDX,8),%XMM10,%XMM11

  (2921) 0x544bd6 MOV	(%R12,%RAX,8),%R8

  (2921) 0x544bda VMOVSD	(%R13,%RAX,8),%XMM5

  (2921) 0x544be1 LEA	0x6(%RDI),%RDX

  (2921) 0x544be5 MOV	(%R12,%RDX,8),%RCX

  (2921) 0x544be9 VFMADD231SD	(%RBX,%RSI,8),%XMM2,%XMM11

  (2921) 0x544bef VMOVSD	(%R13,%RDX,8),%XMM6

  (2921) 0x544bf6 LEA	0x7(%RDI),%RAX

  (2921) 0x544bfa MOV	(%R12,%RAX,8),%RSI

  (2921) 0x544bfe VMOVSD	(%R13,%RAX,8),%XMM13

  (2921) 0x544c05 VFMADD231SD	(%RBX,%R8,8),%XMM5,%XMM11

  (2921) 0x544c0b ADD	$0x8,%RDI

  (2921) 0x544c0f VFMADD231SD	(%RBX,%RCX,8),%XMM6,%XMM11

  (2921) 0x544c15 VFMADD231SD	(%RBX,%RSI,8),%XMM13,%XMM11

  (2921) 0x544c1b CMP	%R11,%RDI

  (2921) 0x544c1e JNE	544b73

(2920) 0x544c24 VMOVSD	%XMM11,(%R15,%R14,8)

(2920) 0x544c2a INC	%R14

(2920) 0x544c2d CMP	%R14,%R9

(2920) 0x544c30 JNE	544a90

0x544c36 ADD	$0x38,%RSP

0x544c3a POP	%RBX

0x544c3b POP	%R12

0x544c3d POP	%R13

0x544c3f POP	%R14

0x544c41 POP	%R15

0x544c43 POP	%RBP

0x544c44 RET

0x544c45 NOPL	(%RAX)

0x544c48 VCOMISD	0x15ab8(%RIP),%XMM11

0x544c50 JNE	5454d1

0x544c56 CMP	%R9,%R14

0x544c59 JGE	544a58

0x544c5f NOP

(2918) 0x544c60 MOV	(%R10,%R14,8),%RDI

(2918) 0x544c64 MOV	0x8(%R10,%R14,8),%R11

(2918) 0x544c69 VMOVAPD	%XMM8,%XMM11

(2918) 0x544c6e CMP	%R11,%RDI

(2918) 0x544c71 JGE	544df4

(2918) 0x544c77 MOV	%R11,%RCX

(2918) 0x544c7a SUB	%RDI,%RCX

(2918) 0x544c7d AND	$0x7,%ECX

(2918) 0x544c80 JE	544d43

(2918) 0x544c86 CMP	$0x1,%RCX

(2918) 0x544c8a JE	544d26

(2918) 0x544c90 CMP	$0x2,%RCX

(2918) 0x544c94 JE	544d12

(2918) 0x544c96 CMP	$0x3,%RCX

(2918) 0x544c9a JE	544cfe

(2918) 0x544c9c CMP	$0x4,%RCX

(2918) 0x544ca0 JE	544cea

(2918) 0x544ca2 CMP	$0x5,%RCX

(2918) 0x544ca6 JE	544cd6

(2918) 0x544ca8 CMP	$0x6,%RCX

(2918) 0x544cac JE	544cc2

(2918) 0x544cae MOV	(%R12,%RDI,8),%RAX

(2918) 0x544cb2 VMOVSD	(%R13,%RDI,8),%XMM11

(2918) 0x544cb9 INC	%RDI

(2918) 0x544cbc VFNMADD132SD	(%RBX,%RAX,8),%XMM8,%XMM11

(2918) 0x544cc2 MOV	(%R12,%RDI,8),%R8

(2918) 0x544cc6 VMOVSD	(%R13,%RDI,8),%XMM14

(2918) 0x544ccd INC	%RDI

(2918) 0x544cd0 VFNMADD231SD	(%RBX,%R8,8),%XMM14,%XMM11

(2918) 0x544cd6 MOV	(%R12,%RDI,8),%RDX

(2918) 0x544cda VMOVSD	(%R13,%RDI,8),%XMM12

(2918) 0x544ce1 INC	%RDI

(2918) 0x544ce4 VFNMADD231SD	(%RBX,%RDX,8),%XMM12,%XMM11

(2918) 0x544cea MOV	(%R12,%RDI,8),%RSI

(2918) 0x544cee VMOVSD	(%R13,%RDI,8),%XMM15

(2918) 0x544cf5 INC	%RDI

(2918) 0x544cf8 VFNMADD231SD	(%RBX,%RSI,8),%XMM15,%XMM11

(2918) 0x544cfe MOV	(%R12,%RDI,8),%RCX

(2918) 0x544d02 VMOVSD	(%R13,%RDI,8),%XMM9

(2918) 0x544d09 INC	%RDI

(2918) 0x544d0c VFNMADD231SD	(%RBX,%RCX,8),%XMM9,%XMM11

(2918) 0x544d12 MOV	(%R12,%RDI,8),%RAX

(2918) 0x544d16 VMOVSD	(%R13,%RDI,8),%XMM1

(2918) 0x544d1d INC	%RDI

(2918) 0x544d20 VFNMADD231SD	(%RBX,%RAX,8),%XMM1,%XMM11

(2918) 0x544d26 MOV	(%R12,%RDI,8),%R8

(2918) 0x544d2a VMOVSD	(%R13,%RDI,8),%XMM7

(2918) 0x544d31 INC	%RDI

(2918) 0x544d34 VFNMADD231SD	(%RBX,%R8,8),%XMM7,%XMM11

(2918) 0x544d3a CMP	%R11,%RDI

(2918) 0x544d3d JE	544df4

  (2919) 0x544d43 MOV	(%R12,%RDI,8),%RDX

  (2919) 0x544d47 VMOVSD	(%R13,%RDI,8),%XMM0

  (2919) 0x544d4e LEA	0x1(%RDI),%RCX

  (2919) 0x544d52 VFNMADD231SD	(%RBX,%RDX,8),%XMM0,%XMM11

  (2919) 0x544d58 MOV	(%R12,%RCX,8),%RSI

  (2919) 0x544d5c VMOVSD	(%R13,%RCX,8),%XMM3

  (2919) 0x544d63 LEA	0x2(%RDI),%RAX

  (2919) 0x544d67 MOV	(%R12,%RAX,8),%R8

  (2919) 0x544d6b VFNMADD231SD	(%RBX,%RSI,8),%XMM3,%XMM11

  (2919) 0x544d71 VMOVSD	(%R13,%RAX,8),%XMM4

  (2919) 0x544d78 LEA	0x3(%RDI),%RDX

  (2919) 0x544d7c MOV	(%R12,%RDX,8),%RCX

  (2919) 0x544d80 VMOVSD	(%R13,%RDX,8),%XMM10

  (2919) 0x544d87 VFNMADD231SD	(%RBX,%R8,8),%XMM4,%XMM11

  (2919) 0x544d8d LEA	0x4(%RDI),%RAX

  (2919) 0x544d91 MOV	(%R12,%RAX,8),%RSI

  (2919) 0x544d95 VMOVSD	(%R13,%RAX,8),%XMM2

  (2919) 0x544d9c LEA	0x5(%RDI),%R8

  (2919) 0x544da0 VFNMADD231SD	(%RBX,%RCX,8),%XMM10,%XMM11

  (2919) 0x544da6 MOV	(%R12,%R8,8),%RDX

  (2919) 0x544daa VMOVSD	(%R13,%R8,8),%XMM5

  (2919) 0x544db1 LEA	0x6(%RDI),%RCX

  (2919) 0x544db5 MOV	(%R12,%RCX,8),%RAX

  (2919) 0x544db9 VFNMADD231SD	(%RBX,%RSI,8),%XMM2,%XMM11

  (2919) 0x544dbf VMOVSD	(%R13,%RCX,8),%XMM6

  (2919) 0x544dc6 LEA	0x7(%RDI),%R8

  (2919) 0x544dca MOV	(%R12,%R8,8),%RSI

  (2919) 0x544dce VMOVSD	(%R13,%R8,8),%XMM13

  (2919) 0x544dd5 VFNMADD231SD	(%RBX,%RDX,8),%XMM5,%XMM11

  (2919) 0x544ddb ADD	$0x8,%RDI

  (2919) 0x544ddf VFNMADD231SD	(%RBX,%RAX,8),%XMM6,%XMM11

  (2919) 0x544de5 VFNMADD231SD	(%RBX,%RSI,8),%XMM13,%XMM11

  (2919) 0x544deb CMP	%R11,%RDI

  (2919) 0x544dee JNE	544d43

(2918) 0x544df4 VMOVSD	%XMM11,(%R15,%R14,8)

(2918) 0x544dfa INC	%R14

(2918) 0x544dfd CMP	%R14,%R9

(2918) 0x544e00 JNE	544c60

0x544e06 ADD	$0x38,%RSP

0x544e0a POP	%RBX

0x544e0b POP	%R12

0x544e0d POP	%R13

0x544e0f POP	%R14

0x544e11 POP	%R15

0x544e13 POP	%RBP

0x544e14 RET

0x544e15 NOPL	(%RAX)

0x544e18 VMOVSD	0x158f8(%RIP),%XMM2

0x544e20 VCOMISD	%XMM2,%XMM8

0x544e24 JNE	5452eb

0x544e2a VMOVSD	-0x60(%RBP),%XMM8

0x544e2f VCOMISD	%XMM2,%XMM8

0x544e33 JE	545a0c

0x544e39 VCOMISD	%XMM3,%XMM8

0x544e3d JNE	545bc4

0x544e43 CMP	%R9,%R14

0x544e46 JGE	544a58

0x544e4c VMOVQ	0x15d1c(%RIP),%XMM8

0x544e54 NOPL	(%RAX)

(2932) 0x544e58 VMOVSD	(%RDI,%R14,8),%XMM1

(2932) 0x544e5e MOV	(%R10,%R14,8),%R11

(2932) 0x544e62 MOV	0x8(%R10,%R14,8),%RAX

(2932) 0x544e67 VXORPD	%XMM8,%XMM1,%XMM0

(2932) 0x544e6c CMP	%RAX,%R11

(2932) 0x544e6f JGE	544ff3

(2932) 0x544e75 MOV	%RAX,%R8

(2932) 0x544e78 SUB	%R11,%R8

(2932) 0x544e7b AND	$0x7,%R8D

(2932) 0x544e7f JE	544f42

(2932) 0x544e85 CMP	$0x1,%R8

(2932) 0x544e89 JE	544f25

(2932) 0x544e8f CMP	$0x2,%R8

(2932) 0x544e93 JE	544f11

(2932) 0x544e95 CMP	$0x3,%R8

(2932) 0x544e99 JE	544efd

(2932) 0x544e9b CMP	$0x4,%R8

(2932) 0x544e9f JE	544ee9

(2932) 0x544ea1 CMP	$0x5,%R8

(2932) 0x544ea5 JE	544ed5

(2932) 0x544ea7 CMP	$0x6,%R8

(2932) 0x544eab JE	544ec1

(2932) 0x544ead MOV	(%R12,%R11,8),%RSI

(2932) 0x544eb1 VMOVSD	(%R13,%R11,8),%XMM7

(2932) 0x544eb8 INC	%R11

(2932) 0x544ebb VFNMADD231SD	(%RBX,%RSI,8),%XMM7,%XMM0

(2932) 0x544ec1 MOV	(%R12,%R11,8),%RDX

(2932) 0x544ec5 VMOVSD	(%R13,%R11,8),%XMM3

(2932) 0x544ecc INC	%R11

(2932) 0x544ecf VFNMADD231SD	(%RBX,%RDX,8),%XMM3,%XMM0

(2932) 0x544ed5 MOV	(%R12,%R11,8),%RCX

(2932) 0x544ed9 VMOVSD	(%R13,%R11,8),%XMM2

(2932) 0x544ee0 INC	%R11

(2932) 0x544ee3 VFNMADD231SD	(%RBX,%RCX,8),%XMM2,%XMM0

(2932) 0x544ee9 MOV	(%R12,%R11,8),%R8

(2932) 0x544eed VMOVSD	(%R13,%R11,8),%XMM4

(2932) 0x544ef4 INC	%R11

(2932) 0x544ef7 VFNMADD231SD	(%RBX,%R8,8),%XMM4,%XMM0

(2932) 0x544efd MOV	(%R12,%R11,8),%RSI

(2932) 0x544f01 VMOVSD	(%R13,%R11,8),%XMM5

(2932) 0x544f08 INC	%R11

(2932) 0x544f0b VFNMADD231SD	(%RBX,%RSI,8),%XMM5,%XMM0

(2932) 0x544f11 MOV	(%R12,%R11,8),%RDX

(2932) 0x544f15 VMOVSD	(%R13,%R11,8),%XMM6

(2932) 0x544f1c INC	%R11

(2932) 0x544f1f VFNMADD231SD	(%RBX,%RDX,8),%XMM6,%XMM0

(2932) 0x544f25 MOV	(%R12,%R11,8),%RCX

(2932) 0x544f29 VMOVSD	(%R13,%R11,8),%XMM10

(2932) 0x544f30 INC	%R11

(2932) 0x544f33 VFNMADD231SD	(%RBX,%RCX,8),%XMM10,%XMM0

(2932) 0x544f39 CMP	%RAX,%R11

(2932) 0x544f3c JE	544ff3

  (2933) 0x544f42 MOV	(%R12,%R11,8),%R8

  (2933) 0x544f46 VMOVSD	(%R13,%R11,8),%XMM11

  (2933) 0x544f4d LEA	0x1(%R11),%RDX

  (2933) 0x544f51 VFNMADD231SD	(%RBX,%R8,8),%XMM11,%XMM0

  (2933) 0x544f57 MOV	(%R12,%RDX,8),%RSI

  (2933) 0x544f5b VMOVSD	(%R13,%RDX,8),%XMM13

  (2933) 0x544f62 LEA	0x2(%R11),%RCX

  (2933) 0x544f66 MOV	(%R12,%RCX,8),%R8

  (2933) 0x544f6a VFNMADD231SD	(%RBX,%RSI,8),%XMM13,%XMM0

  (2933) 0x544f70 VMOVSD	(%R13,%RCX,8),%XMM14

  (2933) 0x544f77 LEA	0x3(%R11),%RDX

  (2933) 0x544f7b MOV	(%R12,%RDX,8),%RSI

  (2933) 0x544f7f VMOVSD	(%R13,%RDX,8),%XMM12

  (2933) 0x544f86 VFNMADD231SD	(%RBX,%R8,8),%XMM14,%XMM0

  (2933) 0x544f8c LEA	0x4(%R11),%RCX

  (2933) 0x544f90 MOV	(%R12,%RCX,8),%R8

  (2933) 0x544f94 VMOVSD	(%R13,%RCX,8),%XMM15

  (2933) 0x544f9b LEA	0x5(%R11),%RDX

  (2933) 0x544f9f VFNMADD231SD	(%RBX,%RSI,8),%XMM12,%XMM0

  (2933) 0x544fa5 VMOVSD	(%R13,%RDX,8),%XMM9

  (2933) 0x544fac MOV	(%R12,%RDX,8),%RSI

  (2933) 0x544fb0 LEA	0x6(%R11),%RCX

  (2933) 0x544fb4 VMOVSD	(%R13,%RCX,8),%XMM1

  (2933) 0x544fbb VFNMADD231SD	(%RBX,%R8,8),%XMM15,%XMM0

  (2933) 0x544fc1 MOV	(%R12,%RCX,8),%R8

  (2933) 0x544fc5 LEA	0x7(%R11),%RDX

  (2933) 0x544fc9 VMOVSD	(%R13,%RDX,8),%XMM7

  (2933) 0x544fd0 ADD	$0x8,%R11

  (2933) 0x544fd4 VFNMADD231SD	(%RBX,%RSI,8),%XMM9,%XMM0

  (2933) 0x544fda MOV	(%R12,%RDX,8),%RSI

  (2933) 0x544fde VFNMADD231SD	(%RBX,%R8,8),%XMM1,%XMM0

  (2933) 0x544fe4 VFNMADD231SD	(%RBX,%RSI,8),%XMM7,%XMM0

  (2933) 0x544fea CMP	%RAX,%R11

  (2933) 0x544fed JNE	544f42

(2932) 0x544ff3 VMOVSD	%XMM0,(%R15,%R14,8)

(2932) 0x544ff9 INC	%R14

(2932) 0x544ffc CMP	%R14,%R9

(2932) 0x544fff JNE	544e58

0x545005 JMP	544a58

0x54500a NOPW	(%RAX,%RAX,1)

0x545010 MOV	%RDI,-0x40(%RBP)

0x545014 MOV	0x272e5(%RIP),%RDI

0x54501b MOV	$0x55d7bd,%EDX

0x545020 MOV	$0x55cc4c,%ESI

0x545025 XOR	%EAX,%EAX

0x545027 MOV	%R9,-0x50(%RBP)

0x54502b MOV	%R10,-0x48(%RBP)

0x54502f VMOVSD	%XMM8,-0x38(%RBP)

0x545034 CALL	552680 <hypre_fprintf>

0x545039 MOV	$0x55d7e0,%EDI

0x54503e XOR	%ECX,%ECX

0x545040 MOV	$0x1,%EDX

0x545045 MOV	$0xfa,%ESI

0x54504a CALL	5561b0 <hypre_error_handler>

0x54504f VMOVSD	-0x38(%RBP),%XMM8

0x545054 MOV	-0x40(%RBP),%RDI

0x545058 MOV	-0x48(%RBP),%R10

0x54505c MOV	-0x50(%RBP),%R9

0x545060 JMP	544857

0x545065 NOPL	(%RAX)

0x545068 MOV	%RDI,-0x48(%RBP)

0x54506c MOV	0x2728d(%RIP),%RDI

0x545073 MOV	$0x55d838,%EDX

0x545078 MOV	$0x55cc4c,%ESI

0x54507d XOR	%EAX,%EAX

0x54507f MOV	%R9,-0x58(%RBP)

0x545083 MOV	%R10,-0x50(%RBP)

0x545087 VMOVSD	%XMM8,-0x40(%RBP)

0x54508c CALL	552680 <hypre_fprintf>

0x545091 MOV	$0x55d7e0,%EDI

0x545096 XOR	%ECX,%ECX

0x545098 MOV	$0x1,%EDX

0x54509d MOV	$0xf9,%ESI

0x5450a2 CALL	5561b0 <hypre_error_handler>

0x5450a7 VMOVSD	-0x40(%RBP),%XMM8

0x5450ac MOV	-0x48(%RBP),%RDI

0x5450b0 MOV	-0x50(%RBP),%R10

0x5450b4 MOV	-0x58(%RBP),%R9

0x5450b8 JMP	544844

0x5450bd NOPL	(%RAX)

0x5450c0 MOV	%RDI,-0x48(%RBP)

0x5450c4 MOV	0x27235(%RIP),%RDI

0x5450cb MOV	%RAX,-0x58(%RBP)

0x5450cf MOV	$0x55d66a,%EDX

0x5450d4 MOV	$0x55cc4c,%ESI

0x5450d9 XOR	%EAX,%EAX

0x5450db MOV	%R10,-0x50(%RBP)

0x5450df VMOVSD	%XMM8,-0x40(%RBP)

0x5450e4 CALL	552680 <hypre_fprintf>

0x5450e9 MOV	$0x55d7e0,%EDI

0x5450ee XOR	%ECX,%ECX

0x5450f0 MOV	$0x1,%EDX

0x5450f5 MOV	$0xf8,%ESI

0x5450fa CALL	5561b0 <hypre_error_handler>

0x5450ff VMOVSD	-0x40(%RBP),%XMM8

0x545104 MOV	-0x48(%RBP),%RDI

0x545108 MOV	-0x50(%RBP),%R10

0x54510c MOV	-0x58(%RBP),%R9

0x545110 JMP	544831

0x545115 CMP	%R9,%R14

0x545118 JGE	544a58

0x54511e VMOVQ	0x15a4a(%RIP),%XMM8

0x545126 NOPW	%CS:(%RAX,%RAX,1)

(2934) 0x545130 VMOVSD	(%RDI,%R14,8),%XMM2

(2934) 0x545136 MOV	(%R10,%R14,8),%R11

(2934) 0x54513a MOV	0x8(%R10,%R14,8),%RAX

(2934) 0x54513f VXORPD	%XMM8,%XMM2,%XMM11

(2934) 0x545144 CMP	%RAX,%R11

(2934) 0x545147 JGE	5452ca

(2934) 0x54514d MOV	%RAX,%RDX

(2934) 0x545150 SUB	%R11,%RDX

(2934) 0x545153 AND	$0x7,%EDX

(2934) 0x545156 JE	545219

(2934) 0x54515c CMP	$0x1,%RDX

(2934) 0x545160 JE	5451fc

(2934) 0x545166 CMP	$0x2,%RDX

(2934) 0x54516a JE	5451e8

(2934) 0x54516c CMP	$0x3,%RDX

(2934) 0x545170 JE	5451d4

(2934) 0x545172 CMP	$0x4,%RDX

(2934) 0x545176 JE	5451c0

(2934) 0x545178 CMP	$0x5,%RDX

(2934) 0x54517c JE	5451ac

(2934) 0x54517e CMP	$0x6,%RDX

(2934) 0x545182 JE	545198

(2934) 0x545184 MOV	(%R12,%R11,8),%RSI

(2934) 0x545188 VMOVSD	(%R13,%R11,8),%XMM5

(2934) 0x54518f INC	%R11

(2934) 0x545192 VFMADD231SD	(%RBX,%RSI,8),%XMM5,%XMM11

(2934) 0x545198 MOV	(%R12,%R11,8),%RCX

(2934) 0x54519c VMOVSD	(%R13,%R11,8),%XMM6

(2934) 0x5451a3 INC	%R11

(2934) 0x5451a6 VFMADD231SD	(%RBX,%RCX,8),%XMM6,%XMM11

(2934) 0x5451ac MOV	(%R12,%R11,8),%R8

(2934) 0x5451b0 VMOVSD	(%R13,%R11,8),%XMM13

(2934) 0x5451b7 INC	%R11

(2934) 0x5451ba VFMADD231SD	(%RBX,%R8,8),%XMM13,%XMM11

(2934) 0x5451c0 MOV	(%R12,%R11,8),%RDX

(2934) 0x5451c4 VMOVSD	(%R13,%R11,8),%XMM14

(2934) 0x5451cb INC	%R11

(2934) 0x5451ce VFMADD231SD	(%RBX,%RDX,8),%XMM14,%XMM11

(2934) 0x5451d4 MOV	(%R12,%R11,8),%RSI

(2934) 0x5451d8 VMOVSD	(%R13,%R11,8),%XMM12

(2934) 0x5451df INC	%R11

(2934) 0x5451e2 VFMADD231SD	(%RBX,%RSI,8),%XMM12,%XMM11

(2934) 0x5451e8 MOV	(%R12,%R11,8),%RCX

(2934) 0x5451ec VMOVSD	(%R13,%R11,8),%XMM15

(2934) 0x5451f3 INC	%R11

(2934) 0x5451f6 VFMADD231SD	(%RBX,%RCX,8),%XMM15,%XMM11

(2934) 0x5451fc MOV	(%R12,%R11,8),%R8

(2934) 0x545200 VMOVSD	(%R13,%R11,8),%XMM9

(2934) 0x545207 INC	%R11

(2934) 0x54520a VFMADD231SD	(%RBX,%R8,8),%XMM9,%XMM11

(2934) 0x545210 CMP	%RAX,%R11

(2934) 0x545213 JE	5452ca

  (2935) 0x545219 MOV	(%R12,%R11,8),%RDX

  (2935) 0x54521d VMOVSD	(%R13,%R11,8),%XMM1

  (2935) 0x545224 LEA	0x1(%R11),%RCX

  (2935) 0x545228 VFMADD231SD	(%RBX,%RDX,8),%XMM1,%XMM11

  (2935) 0x54522e MOV	(%R12,%RCX,8),%RSI

  (2935) 0x545232 VMOVSD	(%R13,%RCX,8),%XMM7

  (2935) 0x545239 LEA	0x2(%R11),%R8

  (2935) 0x54523d MOV	(%R12,%R8,8),%RDX

  (2935) 0x545241 VFMADD231SD	(%RBX,%RSI,8),%XMM7,%XMM11

  (2935) 0x545247 VMOVSD	(%R13,%R8,8),%XMM0

  (2935) 0x54524e LEA	0x3(%R11),%RCX

  (2935) 0x545252 MOV	(%R12,%RCX,8),%RSI

  (2935) 0x545256 VMOVSD	(%R13,%RCX,8),%XMM3

  (2935) 0x54525d VFMADD231SD	(%RBX,%RDX,8),%XMM0,%XMM11

  (2935) 0x545263 LEA	0x4(%R11),%R8

  (2935) 0x545267 MOV	(%R12,%R8,8),%RDX

  (2935) 0x54526b VMOVSD	(%R13,%R8,8),%XMM4

  (2935) 0x545272 LEA	0x5(%R11),%RCX

  (2935) 0x545276 VFMADD231SD	(%RBX,%RSI,8),%XMM3,%XMM11

  (2935) 0x54527c VMOVSD	(%R13,%RCX,8),%XMM10

  (2935) 0x545283 MOV	(%R12,%RCX,8),%RSI

  (2935) 0x545287 LEA	0x6(%R11),%R8

  (2935) 0x54528b VMOVSD	(%R13,%R8,8),%XMM2

  (2935) 0x545292 VFMADD231SD	(%RBX,%RDX,8),%XMM4,%XMM11

  (2935) 0x545298 MOV	(%R12,%R8,8),%RDX

  (2935) 0x54529c LEA	0x7(%R11),%RCX

  (2935) 0x5452a0 VMOVSD	(%R13,%RCX,8),%XMM5

  (2935) 0x5452a7 ADD	$0x8,%R11

  (2935) 0x5452ab VFMADD231SD	(%RBX,%RSI,8),%XMM10,%XMM11

  (2935) 0x5452b1 MOV	(%R12,%RCX,8),%RSI

  (2935) 0x5452b5 VFMADD231SD	(%RBX,%RDX,8),%XMM2,%XMM11

  (2935) 0x5452bb VFMADD231SD	(%RBX,%RSI,8),%XMM5,%XMM11

  (2935) 0x5452c1 CMP	%RAX,%R11

  (2935) 0x5452c4 JNE	545219

(2934) 0x5452ca VMOVSD	%XMM11,(%R15,%R14,8)

(2934) 0x5452d0 INC	%R14

(2934) 0x5452d3 CMP	%R14,%R9

(2934) 0x5452d6 JNE	545130

0x5452dc ADD	$0x38,%RSP

0x5452e0 POP	%RBX

0x5452e1 POP	%R12

0x5452e3 POP	%R13

0x5452e5 POP	%R14

0x5452e7 POP	%R15

0x5452e9 POP	%RBP

0x5452ea RET

0x5452eb VMOVSD	-0x60(%RBP),%XMM4

0x5452f0 VCOMISD	%XMM2,%XMM4

0x5452f4 JE	545854

0x5452fa VCOMISD	%XMM3,%XMM4

0x5452fe VMOVAPD	%XMM4,%XMM9

0x545302 JNE	545d82

0x545308 CMP	%R9,%R14

0x54530b JGE	544a58

0x545311 VMOVQ	0x15857(%RIP),%XMM9

0x545319 NOPL	(%RAX)

(2926) 0x545320 VMULSD	(%RDI,%R14,8),%XMM8,%XMM11

(2926) 0x545326 MOV	(%R10,%R14,8),%R11

(2926) 0x54532a MOV	0x8(%R10,%R14,8),%RAX

(2926) 0x54532f VXORPD	%XMM9,%XMM11,%XMM12

(2926) 0x545334 CMP	%RAX,%R11

(2926) 0x545337 JGE	5454ba

(2926) 0x54533d MOV	%RAX,%RDX

(2926) 0x545340 SUB	%R11,%RDX

(2926) 0x545343 AND	$0x7,%EDX

(2926) 0x545346 JE	545409

(2926) 0x54534c CMP	$0x1,%RDX

(2926) 0x545350 JE	5453ec

(2926) 0x545356 CMP	$0x2,%RDX

(2926) 0x54535a JE	5453d8

(2926) 0x54535c CMP	$0x3,%RDX

(2926) 0x545360 JE	5453c4

(2926) 0x545362 CMP	$0x4,%RDX

(2926) 0x545366 JE	5453b0

(2926) 0x545368 CMP	$0x5,%RDX

(2926) 0x54536c JE	54539c

(2926) 0x54536e CMP	$0x6,%RDX

(2926) 0x545372 JE	545388

(2926) 0x545374 MOV	(%R12,%R11,8),%RCX

(2926) 0x545378 VMOVSD	(%R13,%R11,8),%XMM13

(2926) 0x54537f INC	%R11

(2926) 0x545382 VFNMADD231SD	(%RBX,%RCX,8),%XMM13,%XMM12

(2926) 0x545388 MOV	(%R12,%R11,8),%R8

(2926) 0x54538c VMOVSD	(%R13,%R11,8),%XMM14

(2926) 0x545393 INC	%R11

(2926) 0x545396 VFNMADD231SD	(%RBX,%R8,8),%XMM14,%XMM12

(2926) 0x54539c MOV	(%R12,%R11,8),%RSI

(2926) 0x5453a0 VMOVSD	(%R13,%R11,8),%XMM15

(2926) 0x5453a7 INC	%R11

(2926) 0x5453aa VFNMADD231SD	(%RBX,%RSI,8),%XMM15,%XMM12

(2926) 0x5453b0 MOV	(%R12,%R11,8),%RDX

(2926) 0x5453b4 VMOVSD	(%R13,%R11,8),%XMM1

(2926) 0x5453bb INC	%R11

(2926) 0x5453be VFNMADD231SD	(%RBX,%RDX,8),%XMM1,%XMM12

(2926) 0x5453c4 MOV	(%R12,%R11,8),%RCX

(2926) 0x5453c8 VMOVSD	(%R13,%R11,8),%XMM7

(2926) 0x5453cf INC	%R11

(2926) 0x5453d2 VFNMADD231SD	(%RBX,%RCX,8),%XMM7,%XMM12

(2926) 0x5453d8 MOV	(%R12,%R11,8),%R8

(2926) 0x5453dc VMOVSD	(%R13,%R11,8),%XMM0

(2926) 0x5453e3 INC	%R11

(2926) 0x5453e6 VFNMADD231SD	(%RBX,%R8,8),%XMM0,%XMM12

(2926) 0x5453ec MOV	(%R12,%R11,8),%RSI

(2926) 0x5453f0 VMOVSD	(%R13,%R11,8),%XMM3

(2926) 0x5453f7 INC	%R11

(2926) 0x5453fa VFNMADD231SD	(%RBX,%RSI,8),%XMM3,%XMM12

(2926) 0x545400 CMP	%RAX,%R11

(2926) 0x545403 JE	5454ba

  (2927) 0x545409 MOV	(%R12,%R11,8),%RDX

  (2927) 0x54540d VMOVSD	(%R13,%R11,8),%XMM2

  (2927) 0x545414 LEA	0x1(%R11),%RCX

  (2927) 0x545418 VFNMADD231SD	(%RBX,%RDX,8),%XMM2,%XMM12

  (2927) 0x54541e MOV	(%R12,%RCX,8),%R8

  (2927) 0x545422 VMOVSD	(%R13,%RCX,8),%XMM4

  (2927) 0x545429 LEA	0x2(%R11),%RDX

  (2927) 0x54542d MOV	(%R12,%RDX,8),%RSI

  (2927) 0x545431 VFNMADD231SD	(%RBX,%R8,8),%XMM4,%XMM12

  (2927) 0x545437 VMOVSD	(%R13,%RDX,8),%XMM5

  (2927) 0x54543e LEA	0x3(%R11),%RCX

  (2927) 0x545442 MOV	(%R12,%RCX,8),%R8

  (2927) 0x545446 VMOVSD	(%R13,%RCX,8),%XMM6

  (2927) 0x54544d VFNMADD231SD	(%RBX,%RSI,8),%XMM5,%XMM12

  (2927) 0x545453 LEA	0x4(%R11),%RDX

  (2927) 0x545457 MOV	(%R12,%RDX,8),%RSI

  (2927) 0x54545b VMOVSD	(%R13,%RDX,8),%XMM10

  (2927) 0x545462 LEA	0x5(%R11),%RCX

  (2927) 0x545466 VFNMADD231SD	(%RBX,%R8,8),%XMM6,%XMM12

  (2927) 0x54546c VMOVSD	(%R13,%RCX,8),%XMM11

  (2927) 0x545473 MOV	(%R12,%RCX,8),%R8

  (2927) 0x545477 LEA	0x6(%R11),%RDX

  (2927) 0x54547b VMOVSD	(%R13,%RDX,8),%XMM13

  (2927) 0x545482 VFNMADD231SD	(%RBX,%RSI,8),%XMM10,%XMM12

  (2927) 0x545488 MOV	(%R12,%RDX,8),%RSI

  (2927) 0x54548c LEA	0x7(%R11),%RCX

  (2927) 0x545490 VMOVSD	(%R13,%RCX,8),%XMM14

  (2927) 0x545497 ADD	$0x8,%R11

  (2927) 0x54549b VFNMADD231SD	(%RBX,%R8,8),%XMM11,%XMM12

  (2927) 0x5454a1 MOV	(%R12,%RCX,8),%R8

  (2927) 0x5454a5 VFNMADD231SD	(%RBX,%RSI,8),%XMM13,%XMM12

  (2927) 0x5454ab VFNMADD231SD	(%RBX,%R8,8),%XMM14,%XMM12

  (2927) 0x5454b1 CMP	%RAX,%R11

  (2927) 0x5454b4 JNE	545409

(2926) 0x5454ba VMOVSD	%XMM12,(%R15,%R14,8)

(2926) 0x5454c0 INC	%R14

(2926) 0x5454c3 CMP	%R14,%R9

(2926) 0x5454c6 JNE	545320

0x5454cc JMP	544a58

0x5454d1 CMP	%R9,%R14

0x5454d4 JGE	544a58

0x5454da NOPW	(%RAX,%RAX,1)

(2916) 0x5454e0 MOV	(%R10,%R14,8),%RDI

(2916) 0x5454e4 MOV	0x8(%R10,%R14,8),%R11

(2916) 0x5454e9 VMOVAPD	%XMM8,%XMM13

(2916) 0x5454ee CMP	%R11,%RDI

(2916) 0x5454f1 JGE	545679

(2916) 0x5454f7 MOV	%R11,%RAX

(2916) 0x5454fa SUB	%RDI,%RAX

(2916) 0x5454fd AND	$0x7,%EAX

(2916) 0x545500 JE	5455c3

(2916) 0x545506 CMP	$0x1,%RAX

(2916) 0x54550a JE	5455a6

(2916) 0x545510 CMP	$0x2,%RAX

(2916) 0x545514 JE	545592

(2916) 0x545516 CMP	$0x3,%RAX

(2916) 0x54551a JE	54557e

(2916) 0x54551c CMP	$0x4,%RAX

(2916) 0x545520 JE	54556a

(2916) 0x545522 CMP	$0x5,%RAX

(2916) 0x545526 JE	545556

(2916) 0x545528 CMP	$0x6,%RAX

(2916) 0x54552c JE	545542

(2916) 0x54552e MOV	(%R12,%RDI,8),%R8

(2916) 0x545532 VMOVSD	(%R13,%RDI,8),%XMM13

(2916) 0x545539 INC	%RDI

(2916) 0x54553c VFMADD132SD	(%RBX,%R8,8),%XMM8,%XMM13

(2916) 0x545542 MOV	(%R12,%RDI,8),%RDX

(2916) 0x545546 VMOVSD	(%R13,%RDI,8),%XMM6

(2916) 0x54554d INC	%RDI

(2916) 0x545550 VFMADD231SD	(%RBX,%RDX,8),%XMM6,%XMM13

(2916) 0x545556 MOV	(%R12,%RDI,8),%RCX

(2916) 0x54555a VMOVSD	(%R13,%RDI,8),%XMM14

(2916) 0x545561 INC	%RDI

(2916) 0x545564 VFMADD231SD	(%RBX,%RCX,8),%XMM14,%XMM13

(2916) 0x54556a MOV	(%R12,%RDI,8),%RSI

(2916) 0x54556e VMOVSD	(%R13,%RDI,8),%XMM12

(2916) 0x545575 INC	%RDI

(2916) 0x545578 VFMADD231SD	(%RBX,%RSI,8),%XMM12,%XMM13

(2916) 0x54557e MOV	(%R12,%RDI,8),%RAX

(2916) 0x545582 VMOVSD	(%R13,%RDI,8),%XMM15

(2916) 0x545589 INC	%RDI

(2916) 0x54558c VFMADD231SD	(%RBX,%RAX,8),%XMM15,%XMM13

(2916) 0x545592 MOV	(%R12,%RDI,8),%R8

(2916) 0x545596 VMOVSD	(%R13,%RDI,8),%XMM9

(2916) 0x54559d INC	%RDI

(2916) 0x5455a0 VFMADD231SD	(%RBX,%R8,8),%XMM9,%XMM13

(2916) 0x5455a6 MOV	(%R12,%RDI,8),%RDX

(2916) 0x5455aa VMOVSD	(%R13,%RDI,8),%XMM1

(2916) 0x5455b1 INC	%RDI

(2916) 0x5455b4 VFMADD231SD	(%RBX,%RDX,8),%XMM1,%XMM13

(2916) 0x5455ba CMP	%R11,%RDI

(2916) 0x5455bd JE	545674

  (2917) 0x5455c3 MOV	(%R12,%RDI,8),%RCX

  (2917) 0x5455c7 VMOVSD	(%R13,%RDI,8),%XMM7

  (2917) 0x5455ce LEA	0x1(%RDI),%RAX

  (2917) 0x5455d2 VFMADD231SD	(%RBX,%RCX,8),%XMM7,%XMM13

  (2917) 0x5455d8 MOV	(%R12,%RAX,8),%RSI

  (2917) 0x5455dc VMOVSD	(%R13,%RAX,8),%XMM0

  (2917) 0x5455e3 LEA	0x2(%RDI),%R8

  (2917) 0x5455e7 MOV	(%R12,%R8,8),%RDX

  (2917) 0x5455eb VFMADD231SD	(%RBX,%RSI,8),%XMM0,%XMM13

  (2917) 0x5455f1 VMOVSD	(%R13,%R8,8),%XMM3

  (2917) 0x5455f8 LEA	0x3(%RDI),%RCX

  (2917) 0x5455fc MOV	(%R12,%RCX,8),%RAX

  (2917) 0x545600 VMOVSD	(%R13,%RCX,8),%XMM4

  (2917) 0x545607 VFMADD231SD	(%RBX,%RDX,8),%XMM3,%XMM13

  (2917) 0x54560d LEA	0x4(%RDI),%R8

  (2917) 0x545611 MOV	(%R12,%R8,8),%RSI

  (2917) 0x545615 VMOVSD	(%R13,%R8,8),%XMM10

  (2917) 0x54561c LEA	0x5(%RDI),%RDX

  (2917) 0x545620 VFMADD231SD	(%RBX,%RAX,8),%XMM4,%XMM13

  (2917) 0x545626 MOV	(%R12,%RDX,8),%RCX

  (2917) 0x54562a VMOVSD	(%R13,%RDX,8),%XMM2

  (2917) 0x545631 LEA	0x6(%RDI),%RAX

  (2917) 0x545635 MOV	(%R12,%RAX,8),%R8

  (2917) 0x545639 VFMADD231SD	(%RBX,%RSI,8),%XMM10,%XMM13

  (2917) 0x54563f VMOVSD	(%R13,%RAX,8),%XMM5

  (2917) 0x545646 LEA	0x7(%RDI),%RDX

  (2917) 0x54564a MOV	(%R12,%RDX,8),%RSI

  (2917) 0x54564e VMOVSD	(%R13,%RDX,8),%XMM6

  (2917) 0x545655 VFMADD231SD	(%RBX,%RCX,8),%XMM2,%XMM13

  (2917) 0x54565b ADD	$0x8,%RDI

  (2917) 0x54565f VFMADD231SD	(%RBX,%R8,8),%XMM5,%XMM13

  (2917) 0x545665 VFMADD231SD	(%RBX,%RSI,8),%XMM6,%XMM13

  (2917) 0x54566b CMP	%R11,%RDI

  (2917) 0x54566e JNE	5455c3

(2916) 0x545674 VMULSD	%XMM13,%XMM11,%XMM13

(2916) 0x545679 VMOVSD	%XMM13,(%R15,%R14,8)

(2916) 0x54567f INC	%R14

(2916) 0x545682 CMP	%R14,%R9

(2916) 0x545685 JNE	5454e0

0x54568b ADD	$0x38,%RSP

0x54568f POP	%RBX

0x545690 POP	%R12

0x545692 POP	%R13

0x545694 POP	%R14

0x545696 POP	%R15

0x545698 POP	%RBP

0x545699 RET

0x54569a CMP	%R9,%R14

0x54569d JGE	544a58

0x5456a3 NOPL	(%RAX,%RAX,1)

(2936) 0x5456a8 MOV	(%R10,%R14,8),%R11

(2936) 0x5456ac MOV	0x8(%R10,%R14,8),%RAX

(2936) 0x5456b1 VMOVSD	(%RDI,%R14,8),%XMM8

(2936) 0x5456b7 CMP	%RAX,%R11

(2936) 0x5456ba JGE	54583d

(2936) 0x5456c0 MOV	%RAX,%RDX

(2936) 0x5456c3 SUB	%R11,%RDX

(2936) 0x5456c6 AND	$0x7,%EDX

(2936) 0x5456c9 JE	54578c

(2936) 0x5456cf CMP	$0x1,%RDX

(2936) 0x5456d3 JE	54576f

(2936) 0x5456d9 CMP	$0x2,%RDX

(2936) 0x5456dd JE	54575b

(2936) 0x5456df CMP	$0x3,%RDX

(2936) 0x5456e3 JE	545747

(2936) 0x5456e5 CMP	$0x4,%RDX

(2936) 0x5456e9 JE	545733

(2936) 0x5456eb CMP	$0x5,%RDX

(2936) 0x5456ef JE	54571f

(2936) 0x5456f1 CMP	$0x6,%RDX

(2936) 0x5456f5 JE	54570b

(2936) 0x5456f7 MOV	(%R12,%R11,8),%RCX

(2936) 0x5456fb VMOVSD	(%R13,%R11,8),%XMM2

(2936) 0x545702 INC	%R11

(2936) 0x545705 VFNMADD231SD	(%RBX,%RCX,8),%XMM2,%XMM8

(2936) 0x54570b MOV	(%R12,%R11,8),%R8

(2936) 0x54570f VMOVSD	(%R13,%R11,8),%XMM5

(2936) 0x545716 INC	%R11

(2936) 0x545719 VFNMADD231SD	(%RBX,%R8,8),%XMM5,%XMM8

(2936) 0x54571f MOV	(%R12,%R11,8),%RSI

(2936) 0x545723 VMOVSD	(%R13,%R11,8),%XMM6

(2936) 0x54572a INC	%R11

(2936) 0x54572d VFNMADD231SD	(%RBX,%RSI,8),%XMM6,%XMM8

(2936) 0x545733 MOV	(%R12,%R11,8),%RDX

(2936) 0x545737 VMOVSD	(%R13,%R11,8),%XMM11

(2936) 0x54573e INC	%R11

(2936) 0x545741 VFNMADD231SD	(%RBX,%RDX,8),%XMM11,%XMM8

(2936) 0x545747 MOV	(%R12,%R11,8),%RCX

(2936) 0x54574b VMOVSD	(%R13,%R11,8),%XMM13

(2936) 0x545752 INC	%R11

(2936) 0x545755 VFNMADD231SD	(%RBX,%RCX,8),%XMM13,%XMM8

(2936) 0x54575b MOV	(%R12,%R11,8),%R8

(2936) 0x54575f VMOVSD	(%R13,%R11,8),%XMM14

(2936) 0x545766 INC	%R11

(2936) 0x545769 VFNMADD231SD	(%RBX,%R8,8),%XMM14,%XMM8

(2936) 0x54576f MOV	(%R12,%R11,8),%RSI

(2936) 0x545773 VMOVSD	(%R13,%R11,8),%XMM12

(2936) 0x54577a INC	%R11

(2936) 0x54577d VFNMADD231SD	(%RBX,%RSI,8),%XMM12,%XMM8

(2936) 0x545783 CMP	%RAX,%R11

(2936) 0x545786 JE	54583d

  (2937) 0x54578c MOV	(%R12,%R11,8),%RDX

  (2937) 0x545790 VMOVSD	(%R13,%R11,8),%XMM15

  (2937) 0x545797 LEA	0x1(%R11),%RCX

  (2937) 0x54579b VFNMADD231SD	(%RBX,%RDX,8),%XMM15,%XMM8

  (2937) 0x5457a1 MOV	(%R12,%RCX,8),%R8

  (2937) 0x5457a5 VMOVSD	(%R13,%RCX,8),%XMM9

  (2937) 0x5457ac LEA	0x2(%R11),%RDX

  (2937) 0x5457b0 MOV	(%R12,%RDX,8),%RSI

  (2937) 0x5457b4 VFNMADD231SD	(%RBX,%R8,8),%XMM9,%XMM8

  (2937) 0x5457ba VMOVSD	(%R13,%RDX,8),%XMM1

  (2937) 0x5457c1 LEA	0x3(%R11),%RCX

  (2937) 0x5457c5 MOV	(%R12,%RCX,8),%R8

  (2937) 0x5457c9 VMOVSD	(%R13,%RCX,8),%XMM7

  (2937) 0x5457d0 VFNMADD231SD	(%RBX,%RSI,8),%XMM1,%XMM8

  (2937) 0x5457d6 LEA	0x4(%R11),%RDX

  (2937) 0x5457da MOV	(%R12,%RDX,8),%RSI

  (2937) 0x5457de VMOVSD	(%R13,%RDX,8),%XMM0

  (2937) 0x5457e5 LEA	0x5(%R11),%RCX

  (2937) 0x5457e9 VFNMADD231SD	(%RBX,%R8,8),%XMM7,%XMM8

  (2937) 0x5457ef VMOVSD	(%R13,%RCX,8),%XMM3

  (2937) 0x5457f6 MOV	(%R12,%RCX,8),%R8

  (2937) 0x5457fa LEA	0x6(%R11),%RDX

  (2937) 0x5457fe VMOVSD	(%R13,%RDX,8),%XMM4

  (2937) 0x545805 VFNMADD231SD	(%RBX,%RSI,8),%XMM0,%XMM8

  (2937) 0x54580b MOV	(%R12,%RDX,8),%RSI

  (2937) 0x54580f LEA	0x7(%R11),%RCX

  (2937) 0x545813 VMOVSD	(%R13,%RCX,8),%XMM10

  (2937) 0x54581a ADD	$0x8,%R11

  (2937) 0x54581e VFNMADD231SD	(%RBX,%R8,8),%XMM3,%XMM8

  (2937) 0x545824 MOV	(%R12,%RCX,8),%R8

  (2937) 0x545828 VFNMADD231SD	(%RBX,%RSI,8),%XMM4,%XMM8

  (2937) 0x54582e VFNMADD231SD	(%RBX,%R8,8),%XMM10,%XMM8

  (2937) 0x545834 CMP	%RAX,%R11

  (2937) 0x545837 JNE	54578c

(2936) 0x54583d VMOVSD	%XMM8,(%R15,%R14,8)

(2936) 0x545843 INC	%R14

(2936) 0x545846 CMP	%R14,%R9

(2936) 0x545849 JNE	5456a8

0x54584f JMP	544a58

0x545854 CMP	%R9,%R14

0x545857 JGE	544a58

0x54585d NOPL	(%RAX)

(2922) 0x545860 MOV	(%R10,%R14,8),%R11

(2922) 0x545864 MOV	0x8(%R10,%R14,8),%RAX

(2922) 0x545869 VMULSD	(%RDI,%R14,8),%XMM8,%XMM9

(2922) 0x54586f CMP	%RAX,%R11

(2922) 0x545872 JGE	5459f5

(2922) 0x545878 MOV	%RAX,%RDX

(2922) 0x54587b SUB	%R11,%RDX

(2922) 0x54587e AND	$0x7,%EDX

(2922) 0x545881 JE	545944

(2922) 0x545887 CMP	$0x1,%RDX

(2922) 0x54588b JE	545927

(2922) 0x545891 CMP	$0x2,%RDX

(2922) 0x545895 JE	545913

(2922) 0x545897 CMP	$0x3,%RDX

(2922) 0x54589b JE	5458ff

(2922) 0x54589d CMP	$0x4,%RDX

(2922) 0x5458a1 JE	5458eb

(2922) 0x5458a3 CMP	$0x5,%RDX

(2922) 0x5458a7 JE	5458d7

(2922) 0x5458a9 CMP	$0x6,%RDX

(2922) 0x5458ad JE	5458c3

(2922) 0x5458af MOV	(%R12,%R11,8),%RSI

(2922) 0x5458b3 VMOVSD	(%R13,%R11,8),%XMM12

(2922) 0x5458ba INC	%R11

(2922) 0x5458bd VFMADD231SD	(%RBX,%RSI,8),%XMM12,%XMM9

(2922) 0x5458c3 MOV	(%R12,%R11,8),%RCX

(2922) 0x5458c7 VMOVSD	(%R13,%R11,8),%XMM15

(2922) 0x5458ce INC	%R11

(2922) 0x5458d1 VFMADD231SD	(%RBX,%RCX,8),%XMM15,%XMM9

(2922) 0x5458d7 MOV	(%R12,%R11,8),%R8

(2922) 0x5458db VMOVSD	(%R13,%R11,8),%XMM1

(2922) 0x5458e2 INC	%R11

(2922) 0x5458e5 VFMADD231SD	(%RBX,%R8,8),%XMM1,%XMM9

(2922) 0x5458eb MOV	(%R12,%R11,8),%RDX

(2922) 0x5458ef VMOVSD	(%R13,%R11,8),%XMM7

(2922) 0x5458f6 INC	%R11

(2922) 0x5458f9 VFMADD231SD	(%RBX,%RDX,8),%XMM7,%XMM9

(2922) 0x5458ff MOV	(%R12,%R11,8),%RSI

(2922) 0x545903 VMOVSD	(%R13,%R11,8),%XMM0

(2922) 0x54590a INC	%R11

(2922) 0x54590d VFMADD231SD	(%RBX,%RSI,8),%XMM0,%XMM9

(2922) 0x545913 MOV	(%R12,%R11,8),%RCX

(2922) 0x545917 VMOVSD	(%R13,%R11,8),%XMM3

(2922) 0x54591e INC	%R11

(2922) 0x545921 VFMADD231SD	(%RBX,%RCX,8),%XMM3,%XMM9

(2922) 0x545927 MOV	(%R12,%R11,8),%R8

(2922) 0x54592b VMOVSD	(%R13,%R11,8),%XMM2

(2922) 0x545932 INC	%R11

(2922) 0x545935 VFMADD231SD	(%RBX,%R8,8),%XMM2,%XMM9

(2922) 0x54593b CMP	%RAX,%R11

(2922) 0x54593e JE	5459f5

  (2923) 0x545944 MOV	(%R12,%R11,8),%RDX

  (2923) 0x545948 VMOVSD	(%R13,%R11,8),%XMM4

  (2923) 0x54594f LEA	0x1(%R11),%RCX

  (2923) 0x545953 VFMADD231SD	(%RBX,%RDX,8),%XMM4,%XMM9

  (2923) 0x545959 MOV	(%R12,%RCX,8),%RSI

  (2923) 0x54595d VMOVSD	(%R13,%RCX,8),%XMM5

  (2923) 0x545964 LEA	0x2(%R11),%R8

  (2923) 0x545968 MOV	(%R12,%R8,8),%RDX

  (2923) 0x54596c VFMADD231SD	(%RBX,%RSI,8),%XMM5,%XMM9

  (2923) 0x545972 VMOVSD	(%R13,%R8,8),%XMM6

  (2923) 0x545979 LEA	0x3(%R11),%RCX

  (2923) 0x54597d MOV	(%R12,%RCX,8),%RSI

  (2923) 0x545981 VMOVSD	(%R13,%RCX,8),%XMM10

  (2923) 0x545988 VFMADD231SD	(%RBX,%RDX,8),%XMM6,%XMM9

  (2923) 0x54598e LEA	0x4(%R11),%R8

  (2923) 0x545992 MOV	(%R12,%R8,8),%RDX

  (2923) 0x545996 VMOVSD	(%R13,%R8,8),%XMM11

  (2923) 0x54599d LEA	0x5(%R11),%RCX

  (2923) 0x5459a1 VFMADD231SD	(%RBX,%RSI,8),%XMM10,%XMM9

  (2923) 0x5459a7 VMOVSD	(%R13,%RCX,8),%XMM13

  (2923) 0x5459ae MOV	(%R12,%RCX,8),%RSI

  (2923) 0x5459b2 LEA	0x6(%R11),%R8

  (2923) 0x5459b6 VMOVSD	(%R13,%R8,8),%XMM14

  (2923) 0x5459bd VFMADD231SD	(%RBX,%RDX,8),%XMM11,%XMM9

  (2923) 0x5459c3 MOV	(%R12,%R8,8),%RDX

  (2923) 0x5459c7 LEA	0x7(%R11),%RCX

  (2923) 0x5459cb VMOVSD	(%R13,%RCX,8),%XMM12

  (2923) 0x5459d2 ADD	$0x8,%R11

  (2923) 0x5459d6 VFMADD231SD	(%RBX,%RSI,8),%XMM13,%XMM9

  (2923) 0x5459dc MOV	(%R12,%RCX,8),%RSI

  (2923) 0x5459e0 VFMADD231SD	(%RBX,%RDX,8),%XMM14,%XMM9

  (2923) 0x5459e6 VFMADD231SD	(%RBX,%RSI,8),%XMM12,%XMM9

  (2923) 0x5459ec CMP	%RAX,%R11

  (2923) 0x5459ef JNE	545944

(2922) 0x5459f5 VMOVSD	%XMM9,(%R15,%R14,8)

(2922) 0x5459fb INC	%R14

(2922) 0x5459fe CMP	%R14,%R9

(2922) 0x545a01 JNE	545860

0x545a07 JMP	544a58

0x545a0c CMP	%R9,%R14

0x545a0f JGE	544a58

0x545a15 NOPL	(%RAX)

(2928) 0x545a18 MOV	(%R10,%R14,8),%R11

(2928) 0x545a1c MOV	0x8(%R10,%R14,8),%RAX

(2928) 0x545a21 VMOVSD	(%RDI,%R14,8),%XMM8

(2928) 0x545a27 CMP	%RAX,%R11

(2928) 0x545a2a JGE	545bad

(2928) 0x545a30 MOV	%RAX,%RCX

(2928) 0x545a33 SUB	%R11,%RCX

(2928) 0x545a36 AND	$0x7,%ECX

(2928) 0x545a39 JE	545afc

(2928) 0x545a3f CMP	$0x1,%RCX

(2928) 0x545a43 JE	545adf

(2928) 0x545a49 CMP	$0x2,%RCX

(2928) 0x545a4d JE	545acb

(2928) 0x545a4f CMP	$0x3,%RCX

(2928) 0x545a53 JE	545ab7

(2928) 0x545a55 CMP	$0x4,%RCX

(2928) 0x545a59 JE	545aa3

(2928) 0x545a5b CMP	$0x5,%RCX

(2928) 0x545a5f JE	545a8f

(2928) 0x545a61 CMP	$0x6,%RCX

(2928) 0x545a65 JE	545a7b

(2928) 0x545a67 MOV	(%R12,%R11,8),%R8

(2928) 0x545a6b VMOVSD	(%R13,%R11,8),%XMM0

(2928) 0x545a72 INC	%R11

(2928) 0x545a75 VFMADD231SD	(%RBX,%R8,8),%XMM0,%XMM8

(2928) 0x545a7b MOV	(%R12,%R11,8),%RDX

(2928) 0x545a7f VMOVSD	(%R13,%R11,8),%XMM3

(2928) 0x545a86 INC	%R11

(2928) 0x545a89 VFMADD231SD	(%RBX,%RDX,8),%XMM3,%XMM8

(2928) 0x545a8f MOV	(%R12,%R11,8),%RSI

(2928) 0x545a93 VMOVSD	(%R13,%R11,8),%XMM2

(2928) 0x545a9a INC	%R11

(2928) 0x545a9d VFMADD231SD	(%RBX,%RSI,8),%XMM2,%XMM8

(2928) 0x545aa3 MOV	(%R12,%R11,8),%RCX

(2928) 0x545aa7 VMOVSD	(%R13,%R11,8),%XMM4

(2928) 0x545aae INC	%R11

(2928) 0x545ab1 VFMADD231SD	(%RBX,%RCX,8),%XMM4,%XMM8

(2928) 0x545ab7 MOV	(%R12,%R11,8),%R8

(2928) 0x545abb VMOVSD	(%R13,%R11,8),%XMM5

(2928) 0x545ac2 INC	%R11

(2928) 0x545ac5 VFMADD231SD	(%RBX,%R8,8),%XMM5,%XMM8

(2928) 0x545acb MOV	(%R12,%R11,8),%RDX

(2928) 0x545acf VMOVSD	(%R13,%R11,8),%XMM6

(2928) 0x545ad6 INC	%R11

(2928) 0x545ad9 VFMADD231SD	(%RBX,%RDX,8),%XMM6,%XMM8

(2928) 0x545adf MOV	(%R12,%R11,8),%RSI

(2928) 0x545ae3 VMOVSD	(%R13,%R11,8),%XMM10

(2928) 0x545aea INC	%R11

(2928) 0x545aed VFMADD231SD	(%RBX,%RSI,8),%XMM10,%XMM8

(2928) 0x545af3 CMP	%RAX,%R11

(2928) 0x545af6 JE	545bad

  (2929) 0x545afc MOV	(%R12,%R11,8),%RCX

  (2929) 0x545b00 VMOVSD	(%R13,%R11,8),%XMM11

  (2929) 0x545b07 LEA	0x1(%R11),%R8

  (2929) 0x545b0b VFMADD231SD	(%RBX,%RCX,8),%XMM11,%XMM8

  (2929) 0x545b11 MOV	(%R12,%R8,8),%RDX

  (2929) 0x545b15 VMOVSD	(%R13,%R8,8),%XMM13

  (2929) 0x545b1c LEA	0x2(%R11),%RCX

  (2929) 0x545b20 MOV	(%R12,%RCX,8),%RSI

  (2929) 0x545b24 VFMADD231SD	(%RBX,%RDX,8),%XMM13,%XMM8

  (2929) 0x545b2a VMOVSD	(%R13,%RCX,8),%XMM14

  (2929) 0x545b31 LEA	0x3(%R11),%R8

  (2929) 0x545b35 MOV	(%R12,%R8,8),%RDX

  (2929) 0x545b39 VMOVSD	(%R13,%R8,8),%XMM12

  (2929) 0x545b40 VFMADD231SD	(%RBX,%RSI,8),%XMM14,%XMM8

  (2929) 0x545b46 LEA	0x4(%R11),%RCX

  (2929) 0x545b4a MOV	(%R12,%RCX,8),%RSI

  (2929) 0x545b4e VMOVSD	(%R13,%RCX,8),%XMM15

  (2929) 0x545b55 LEA	0x5(%R11),%R8

  (2929) 0x545b59 VFMADD231SD	(%RBX,%RDX,8),%XMM12,%XMM8

  (2929) 0x545b5f VMOVSD	(%R13,%R8,8),%XMM9

  (2929) 0x545b66 MOV	(%R12,%R8,8),%RDX

  (2929) 0x545b6a LEA	0x6(%R11),%RCX

  (2929) 0x545b6e VMOVSD	(%R13,%RCX,8),%XMM1

  (2929) 0x545b75 VFMADD231SD	(%RBX,%RSI,8),%XMM15,%XMM8

  (2929) 0x545b7b MOV	(%R12,%RCX,8),%RSI

  (2929) 0x545b7f LEA	0x7(%R11),%R8

  (2929) 0x545b83 VMOVSD	(%R13,%R8,8),%XMM7

  (2929) 0x545b8a ADD	$0x8,%R11

  (2929) 0x545b8e VFMADD231SD	(%RBX,%RDX,8),%XMM9,%XMM8

  (2929) 0x545b94 MOV	(%R12,%R8,8),%RDX

  (2929) 0x545b98 VFMADD231SD	(%RBX,%RSI,8),%XMM1,%XMM8

  (2929) 0x545b9e VFMADD231SD	(%RBX,%RDX,8),%XMM7,%XMM8

  (2929) 0x545ba4 CMP	%RAX,%R11

  (2929) 0x545ba7 JNE	545afc

(2928) 0x545bad VMOVSD	%XMM8,(%R15,%R14,8)

(2928) 0x545bb3 INC	%R14

(2928) 0x545bb6 CMP	%R14,%R9

(2928) 0x545bb9 JNE	545a18

0x545bbf JMP	544a58

0x545bc4 CMP	%R9,%R14

0x545bc7 JGE	544a58

0x545bcd NOPL	(%RAX)

(2930) 0x545bd0 MOV	(%R10,%R14,8),%R11

(2930) 0x545bd4 MOV	0x8(%R10,%R14,8),%RAX

(2930) 0x545bd9 VMOVSD	(%RDI,%R14,8),%XMM9

(2930) 0x545bdf CMP	%RAX,%R11

(2930) 0x545be2 JGE	545d66

(2930) 0x545be8 MOV	%RAX,%R8

(2930) 0x545beb SUB	%R11,%R8

(2930) 0x545bee AND	$0x7,%R8D

(2930) 0x545bf2 JE	545cb5

(2930) 0x545bf8 CMP	$0x1,%R8

(2930) 0x545bfc JE	545c98

(2930) 0x545c02 CMP	$0x2,%R8

(2930) 0x545c06 JE	545c84

(2930) 0x545c08 CMP	$0x3,%R8

(2930) 0x545c0c JE	545c70

(2930) 0x545c0e CMP	$0x4,%R8

(2930) 0x545c12 JE	545c5c

(2930) 0x545c14 CMP	$0x5,%R8

(2930) 0x545c18 JE	545c48

(2930) 0x545c1a CMP	$0x6,%R8

(2930) 0x545c1e JE	545c34

(2930) 0x545c20 MOV	(%R12,%R11,8),%RDX

(2930) 0x545c24 VMOVSD	(%R13,%R11,8),%XMM15

(2930) 0x545c2b INC	%R11

(2930) 0x545c2e VFMADD231SD	(%RBX,%RDX,8),%XMM15,%XMM9

(2930) 0x545c34 MOV	(%R12,%R11,8),%RCX

(2930) 0x545c38 VMOVSD	(%R13,%R11,8),%XMM1

(2930) 0x545c3f INC	%R11

(2930) 0x545c42 VFMADD231SD	(%RBX,%RCX,8),%XMM1,%XMM9

(2930) 0x545c48 MOV	(%R12,%R11,8),%RSI

(2930) 0x545c4c VMOVSD	(%R13,%R11,8),%XMM7

(2930) 0x545c53 INC	%R11

(2930) 0x545c56 VFMADD231SD	(%RBX,%RSI,8),%XMM7,%XMM9

(2930) 0x545c5c MOV	(%R12,%R11,8),%R8

(2930) 0x545c60 VMOVSD	(%R13,%R11,8),%XMM0

(2930) 0x545c67 INC	%R11

(2930) 0x545c6a VFMADD231SD	(%RBX,%R8,8),%XMM0,%XMM9

(2930) 0x545c70 MOV	(%R12,%R11,8),%RDX

(2930) 0x545c74 VMOVSD	(%R13,%R11,8),%XMM3

(2930) 0x545c7b INC	%R11

(2930) 0x545c7e VFMADD231SD	(%RBX,%RDX,8),%XMM3,%XMM9

(2930) 0x545c84 MOV	(%R12,%R11,8),%RCX

(2930) 0x545c88 VMOVSD	(%R13,%R11,8),%XMM2

(2930) 0x545c8f INC	%R11

(2930) 0x545c92 VFMADD231SD	(%RBX,%RCX,8),%XMM2,%XMM9

(2930) 0x545c98 MOV	(%R12,%R11,8),%RSI

(2930) 0x545c9c VMOVSD	(%R13,%R11,8),%XMM4

(2930) 0x545ca3 INC	%R11

(2930) 0x545ca6 VFMADD231SD	(%RBX,%RSI,8),%XMM4,%XMM9

(2930) 0x545cac CMP	%RAX,%R11

(2930) 0x545caf JE	545d66

  (2931) 0x545cb5 MOV	(%R12,%R11,8),%R8

  (2931) 0x545cb9 VMOVSD	(%R13,%R11,8),%XMM5

  (2931) 0x545cc0 LEA	0x1(%R11),%RDX

  (2931) 0x545cc4 VFMADD231SD	(%RBX,%R8,8),%XMM5,%XMM9

  (2931) 0x545cca MOV	(%R12,%RDX,8),%RCX

  (2931) 0x545cce VMOVSD	(%R13,%RDX,8),%XMM6

  (2931) 0x545cd5 LEA	0x2(%R11),%R8

  (2931) 0x545cd9 MOV	(%R12,%R8,8),%RSI

  (2931) 0x545cdd VFMADD231SD	(%RBX,%RCX,8),%XMM6,%XMM9

  (2931) 0x545ce3 VMOVSD	(%R13,%R8,8),%XMM10

  (2931) 0x545cea LEA	0x3(%R11),%RDX

  (2931) 0x545cee MOV	(%R12,%RDX,8),%RCX

  (2931) 0x545cf2 VMOVSD	(%R13,%RDX,8),%XMM11

  (2931) 0x545cf9 VFMADD231SD	(%RBX,%RSI,8),%XMM10,%XMM9

  (2931) 0x545cff LEA	0x4(%R11),%R8

  (2931) 0x545d03 MOV	(%R12,%R8,8),%RSI

  (2931) 0x545d07 VMOVSD	(%R13,%R8,8),%XMM13

  (2931) 0x545d0e LEA	0x5(%R11),%RDX

  (2931) 0x545d12 VFMADD231SD	(%RBX,%RCX,8),%XMM11,%XMM9

  (2931) 0x545d18 VMOVSD	(%R13,%RDX,8),%XMM14

  (2931) 0x545d1f MOV	(%R12,%RDX,8),%RCX

  (2931) 0x545d23 LEA	0x6(%R11),%R8

  (2931) 0x545d27 VMOVSD	(%R13,%R8,8),%XMM12

  (2931) 0x545d2e VFMADD231SD	(%RBX,%RSI,8),%XMM13,%XMM9

  (2931) 0x545d34 MOV	(%R12,%R8,8),%RSI

  (2931) 0x545d38 LEA	0x7(%R11),%RDX

  (2931) 0x545d3c VMOVSD	(%R13,%RDX,8),%XMM15

  (2931) 0x545d43 ADD	$0x8,%R11

  (2931) 0x545d47 VFMADD231SD	(%RBX,%RCX,8),%XMM14,%XMM9

  (2931) 0x545d4d MOV	(%R12,%RDX,8),%RCX

  (2931) 0x545d51 VFMADD231SD	(%RBX,%RSI,8),%XMM12,%XMM9

  (2931) 0x545d57 VFMADD231SD	(%RBX,%RCX,8),%XMM15,%XMM9

  (2931) 0x545d5d CMP	%RAX,%R11

  (2931) 0x545d60 JNE	545cb5

(2930) 0x545d66 VMULSD	%XMM9,%XMM8,%XMM9

(2930) 0x545d6b VMOVSD	%XMM9,(%R15,%R14,8)

(2930) 0x545d71 INC	%R14

(2930) 0x545d74 CMP	%R14,%R9

(2930) 0x545d77 JNE	545bd0

0x545d7d JMP	544a58

0x545d82 CMP	%R9,%R14

0x545d85 JGE	544a58

0x545d8b NOPL	(%RAX,%RAX,1)

(2924) 0x545d90 MOV	(%R10,%R14,8),%R11

(2924) 0x545d94 MOV	0x8(%R10,%R14,8),%RAX

(2924) 0x545d99 VMULSD	(%RDI,%R14,8),%XMM8,%XMM10

(2924) 0x545d9f CMP	%RAX,%R11

(2924) 0x545da2 JGE	545f25

(2924) 0x545da8 MOV	%RAX,%RCX

(2924) 0x545dab SUB	%R11,%RCX

(2924) 0x545dae AND	$0x7,%ECX

(2924) 0x545db1 JE	545e74

(2924) 0x545db7 CMP	$0x1,%RCX

(2924) 0x545dbb JE	545e57

(2924) 0x545dc1 CMP	$0x2,%RCX

(2924) 0x545dc5 JE	545e43

(2924) 0x545dc7 CMP	$0x3,%RCX

(2924) 0x545dcb JE	545e2f

(2924) 0x545dcd CMP	$0x4,%RCX

(2924) 0x545dd1 JE	545e1b

(2924) 0x545dd3 CMP	$0x5,%RCX

(2924) 0x545dd7 JE	545e07

(2924) 0x545dd9 CMP	$0x6,%RCX

(2924) 0x545ddd JE	545df3

(2924) 0x545ddf MOV	(%R12,%R11,8),%RSI

(2924) 0x545de3 VMOVSD	(%R13,%R11,8),%XMM5

(2924) 0x545dea INC	%R11

(2924) 0x545ded VFMADD231SD	(%RBX,%RSI,8),%XMM5,%XMM10

(2924) 0x545df3 MOV	(%R12,%R11,8),%R8

(2924) 0x545df7 VMOVSD	(%R13,%R11,8),%XMM6

(2924) 0x545dfe INC	%R11

(2924) 0x545e01 VFMADD231SD	(%RBX,%R8,8),%XMM6,%XMM10

(2924) 0x545e07 MOV	(%R12,%R11,8),%RDX

(2924) 0x545e0b VMOVSD	(%R13,%R11,8),%XMM11

(2924) 0x545e12 INC	%R11

(2924) 0x545e15 VFMADD231SD	(%RBX,%RDX,8),%XMM11,%XMM10

(2924) 0x545e1b MOV	(%R12,%R11,8),%RCX

(2924) 0x545e1f VMOVSD	(%R13,%R11,8),%XMM12

(2924) 0x545e26 INC	%R11

(2924) 0x545e29 VFMADD231SD	(%RBX,%RCX,8),%XMM12,%XMM10

(2924) 0x545e2f MOV	(%R12,%R11,8),%RSI

(2924) 0x545e33 VMOVSD	(%R13,%R11,8),%XMM13

(2924) 0x545e3a INC	%R11

(2924) 0x545e3d VFMADD231SD	(%RBX,%RSI,8),%XMM13,%XMM10

(2924) 0x545e43 MOV	(%R12,%R11,8),%R8

(2924) 0x545e47 VMOVSD	(%R13,%R11,8),%XMM14

(2924) 0x545e4e INC	%R11

(2924) 0x545e51 VFMADD231SD	(%RBX,%R8,8),%XMM14,%XMM10

(2924) 0x545e57 MOV	(%R12,%R11,8),%RDX

(2924) 0x545e5b VMOVSD	(%R13,%R11,8),%XMM15

(2924) 0x545e62 INC	%R11

(2924) 0x545e65 VFMADD231SD	(%RBX,%RDX,8),%XMM15,%XMM10

(2924) 0x545e6b CMP	%RAX,%R11

(2924) 0x545e6e JE	545f25

  (2925) 0x545e74 MOV	(%R12,%R11,8),%RCX

  (2925) 0x545e78 VMOVSD	(%R13,%R11,8),%XMM1

  (2925) 0x545e7f LEA	0x1(%R11),%R8

  (2925) 0x545e83 VFMADD231SD	(%RBX,%RCX,8),%XMM1,%XMM10

  (2925) 0x545e89 MOV	(%R12,%R8,8),%RSI

  (2925) 0x545e8d VMOVSD	(%R13,%R8,8),%XMM7

  (2925) 0x545e94 LEA	0x2(%R11),%RDX

  (2925) 0x545e98 MOV	(%R12,%RDX,8),%RCX

  (2925) 0x545e9c VFMADD231SD	(%RBX,%RSI,8),%XMM7,%XMM10

  (2925) 0x545ea2 VMOVSD	(%R13,%RDX,8),%XMM0

  (2925) 0x545ea9 LEA	0x3(%R11),%R8

  (2925) 0x545ead MOV	(%R12,%R8,8),%RSI

  (2925) 0x545eb1 VMOVSD	(%R13,%R8,8),%XMM3

  (2925) 0x545eb8 VFMADD231SD	(%RBX,%RCX,8),%XMM0,%XMM10

  (2925) 0x545ebe LEA	0x4(%R11),%RDX

  (2925) 0x545ec2 MOV	(%R12,%RDX,8),%RCX

  (2925) 0x545ec6 VMOVSD	(%R13,%RDX,8),%XMM2

  (2925) 0x545ecd LEA	0x5(%R11),%R8

  (2925) 0x545ed1 VFMADD231SD	(%RBX,%RSI,8),%XMM3,%XMM10

  (2925) 0x545ed7 VMOVSD	(%R13,%R8,8),%XMM4

  (2925) 0x545ede MOV	(%R12,%R8,8),%RSI

  (2925) 0x545ee2 LEA	0x6(%R11),%RDX

  (2925) 0x545ee6 VMOVSD	(%R13,%RDX,8),%XMM5

  (2925) 0x545eed VFMADD231SD	(%RBX,%RCX,8),%XMM2,%XMM10

  (2925) 0x545ef3 MOV	(%R12,%RDX,8),%RCX

  (2925) 0x545ef7 LEA	0x7(%R11),%R8

  (2925) 0x545efb VMOVSD	(%R13,%R8,8),%XMM6

  (2925) 0x545f02 ADD	$0x8,%R11

  (2925) 0x545f06 VFMADD231SD	(%RBX,%RSI,8),%XMM4,%XMM10

  (2925) 0x545f0c MOV	(%R12,%R8,8),%RSI

  (2925) 0x545f10 VFMADD231SD	(%RBX,%RCX,8),%XMM5,%XMM10

  (2925) 0x545f16 VFMADD231SD	(%RBX,%RSI,8),%XMM6,%XMM10

  (2925) 0x545f1c CMP	%RAX,%R11

  (2925) 0x545f1f JNE	545e74

(2924) 0x545f25 VMULSD	%XMM10,%XMM9,%XMM10

(2924) 0x545f2a VMOVSD	%XMM10,(%R15,%R14,8)

(2924) 0x545f30 INC	%R14

(2924) 0x545f33 CMP	%R14,%R9

(2924) 0x545f36 JNE	545d90

0x545f3c JMP	544a58

0x545f41 NOPW	%CS:(%RAX,%RAX,1)

0x545f4c NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○97.26	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.38	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	csr_matvec.c:243-404
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:243-365,371-404.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 39.33 to 19.50 cycles (2.02x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 39.33 to 3.31 cycles (11.88x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CSRMatrixGetLoadBalancedPartitionBegin: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:246
hypre_CSRMatrixGetLoadBalancedPartitionEnd: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:247
hypre_error_handler: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:250
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:249
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:248
hypre_fprintf: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:250
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:249
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:248

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:293
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:254
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:266

Type of elements and instruction set

11 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 352 bytes (44 double precision FP elements). The binary function is storing 144 bytes (18 double precision FP elements).

General properties

nb instructions	225
nb uops	236
loop length	934
used x86 registers	16
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	39.33 cycles
front end	39.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	22.00	10.80	26.33	26.33	16.00	10.60	22.00	16.00	16.00	16.00	10.60	26.33
cycles	22.00	10.80	26.33	26.33	16.00	10.60	22.00	16.00	16.00	16.00	10.60	26.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	39.33
Dispatch	26.33
Overall L1	39.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	4%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

INT+FP

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 39.33 cycles. At this rate:

4% of peak load performance is reached (8.95 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.66 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 39.33 to 26.33 cycles (1.49x speedup).

ASM code

In the binary file, the address of the function is: 5447b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x8(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x48(%RDI),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%RDI),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RDI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RDI),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x28(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x40(%RDI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RDI),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RDI),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RDI),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM1,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM7,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 543310 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x40(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 5433a0 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CMP %RAX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x48(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x58(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JG 5450c0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x910>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %R14,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 545068 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x8b8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R14,-0x38(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JL 545068 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x8b8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %R9,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 545010 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x860>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R9,-0x38(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JL 545010 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x860>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCOMISD %XMM0,%XMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JE 544a70 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD 0x15e9b(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD %XMM3,%XMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JNE 544e18 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x668>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD -0x60(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD 0x15e94(%RIP),%XMM8	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JE 545115 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x965>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCOMISD %XMM3,%XMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JE 54569a <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xeea>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVQ 0x162cb(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD -0x60(%RBP),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD 0x15c9b(%RIP),%XMM11	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JNE 544c48 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x498>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VCOMISD 0x15ab8(%RIP),%XMM11	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JNE 5454d1 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xd21>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x158f8(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD %XMM2,%XMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JNE 5452eb <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xb3b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD -0x60(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD %XMM2,%XMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JE 545a0c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x125c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCOMISD %XMM3,%XMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JNE 545bc4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1414>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVQ 0x15d1c(%RIP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x272e5(%RIP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x55d7bd,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x55cc4c,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM8,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 552680 <hypre_fprintf>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x55d7e0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xfa,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 5561b0 <hypre_error_handler>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x38(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 544857 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xa7>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x2728d(%RIP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x55d838,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x55cc4c,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM8,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 552680 <hypre_fprintf>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x55d7e0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xf9,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 5561b0 <hypre_error_handler>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x40(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x58(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 544844 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x94>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x27235(%RIP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x55d66a,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x55cc4c,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM8,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 552680 <hypre_fprintf>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x55d7e0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xf8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 5561b0 <hypre_error_handler>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x40(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x58(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 544831 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x81>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVQ 0x15a4a(%RIP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
VMOVSD -0x60(%RBP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD %XMM2,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JE 545854 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x10a4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCOMISD %XMM3,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM4,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JNE 545d82 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x15d2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVQ 0x15857(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	csr_matvec.c:243-404
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:243-365,371-404.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CSRMatrixGetLoadBalancedPartitionBegin: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:246
hypre_CSRMatrixGetLoadBalancedPartitionEnd: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:247
hypre_error_handler: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:250
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:249
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:248
hypre_fprintf: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:250
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:249
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:248

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCOMISD: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:293
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:254
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:266

Type of elements and instruction set

11 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

General properties

nb instructions	225
nb uops	236
loop length	934
used x86 registers	16
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	39.33 cycles
front end	39.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	22.00	10.80	26.33	26.33	16.00	10.60	22.00	16.00	16.00	16.00	10.60	26.33
cycles	22.00	10.80	26.33	26.33	16.00	10.60	22.00	16.00	16.00	16.00	10.60	26.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	39.33
Dispatch	26.33
Overall L1	39.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	4%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

INT+FP

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 39.33 cycles. At this rate:

4% of peak load performance is reached (8.95 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.66 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 5447b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x8(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x48(%RDI),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%RDI),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RDI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RDI),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x28(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x40(%RDI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RDI),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x20(%RDI),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x10(%RDI),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM1,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM7,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 543310 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x40(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 5433a0 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CMP %RAX,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x48(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x58(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JG 5450c0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x910>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %R14,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 545068 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x8b8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R14,-0x38(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JL 545068 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x8b8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %R9,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JS 545010 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x860>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R9,-0x38(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JL 545010 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x860>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCOMISD %XMM0,%XMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JE 544a70 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD 0x15e9b(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD %XMM3,%XMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JNE 544e18 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x668>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD -0x60(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD 0x15e94(%RIP),%XMM8	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JE 545115 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x965>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCOMISD %XMM3,%XMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JE 54569a <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xeea>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVQ 0x162cb(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD -0x60(%RBP),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD 0x15c9b(%RIP),%XMM11	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JNE 544c48 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x498>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VCOMISD 0x15ab8(%RIP),%XMM11	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JNE 5454d1 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xd21>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x158f8(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD %XMM2,%XMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JNE 5452eb <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xb3b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD -0x60(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD %XMM2,%XMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JE 545a0c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x125c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCOMISD %XMM3,%XMM8	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JNE 545bc4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x1414>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVQ 0x15d1c(%RIP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x272e5(%RIP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x55d7bd,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x55cc4c,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM8,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 552680 <hypre_fprintf>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x55d7e0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xfa,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 5561b0 <hypre_error_handler>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x38(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 544857 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0xa7>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x2728d(%RIP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x55d838,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x55cc4c,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM8,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 552680 <hypre_fprintf>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x55d7e0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xf9,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 5561b0 <hypre_error_handler>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x40(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x58(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 544844 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x94>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x27235(%RIP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x55d66a,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x55cc4c,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM8,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 552680 <hypre_fprintf>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV $0x55d7e0,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0xf8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CALL 5561b0 <hypre_error_handler>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x40(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x48(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x58(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 544831 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x81>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVQ 0x15a4a(%RIP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
VMOVSD -0x60(%RBP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VCOMISD %XMM2,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
JE 545854 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x10a4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VCOMISD %XMM3,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVAPD %XMM4,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JNE 545d82 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x15d2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVQ 0x15857(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JGE 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 544a58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x2a8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6–	24.02	10.38
▼Loop 2928 - csr_matvec.c:334-341 - exec–	1.80	0.68
○Loop 2929 - csr_matvec.c:337-339 - exec	0.03	0.01
▼Loop 2936 - csr_matvec.c:307-314 - exec–	1.16	0.44
○Loop 2937 - csr_matvec.c:310-312 - exec	10.57	3.99
▼Loop 2920 - csr_matvec.c:256-263 - exec–	1.03	0.39
○Loop 2921 - csr_matvec.c:259-261 - exec	9.43	3.56
▼Loop 2922 - csr_matvec.c:373-380 - exec–	0.00	0.00
○Loop 2923 - csr_matvec.c:376-378 - exec	0.00	0.00
▼Loop 2934 - csr_matvec.c:295-302 - exec–	0.00	0.00
○Loop 2935 - csr_matvec.c:298-300 - exec	0.00	0.00
▼Loop 2932 - csr_matvec.c:346-353 - exec–	0.00	0.00
○Loop 2933 - csr_matvec.c:349-351 - exec	0.00	0.00
▼Loop 2918 - csr_matvec.c:268-275 - exec–	0.00	0.00
○Loop 2919 - csr_matvec.c:271-273 - exec	0.00	0.00
▼Loop 2930 - csr_matvec.c:358-365 - exec–	0.00	0.00
○Loop 2931 - csr_matvec.c:361-363 - exec	0.00	0.00
▼Loop 2938 - csr_matvec.c:319-326 - exec–	0.00	0.00
○Loop 2939 - csr_matvec.c:322-324 - exec	0.00	0.00
▼Loop 2926 - csr_matvec.c:385-392 - exec–	0.00	0.00
○Loop 2927 - csr_matvec.c:388-390 - exec	0.00	0.00
▼Loop 2916 - csr_matvec.c:280-287 - exec–	0.00	0.00
○Loop 2917 - csr_matvec.c:283-285 - exec	0.00	0.00
▼Loop 2924 - csr_matvec.c:397-404 - exec–	0.00	0.00
○Loop 2925 - csr_matvec.c:400-402 - exec	0.00	0.00

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Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code