OV - exec - Function hypre_CSRMatrixMatvecOutOfPlace._omp

	Function: hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5	Module: exec	Source: csr_matvec.c:234-237	Coverage (incl. loops): 0.38% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 234 - 237

--------------------------------------------------------------------------------

234: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

235: #endif

236:          for (i = 0; i < num_rows*num_vectors; i++)

237:             y_data[i] *= alpha;

0x544640 PUSH	%RBP

0x544641 MOV	%RSP,%RBP

0x544644 PUSH	%R12

0x544646 MOV	%RDI,%R12

0x544649 PUSH	%RBX

0x54464a CALL	4110b0 <omp_get_num_threads@plt>

0x54464f MOVSXD	%EAX,%RBX

0x544652 CALL	4111f0 <omp_get_thread_num@plt>

0x544657 MOVSXD	%EAX,%RCX

0x54465a MOV	0x18(%R12),%RAX

0x54465f IMUL	0x8(%R12),%RAX

0x544665 CQTO

0x544667 IDIV	%RBX

0x54466a CMP	%RDX,%RCX

0x54466d JL	544798

0x544673 IMUL	%RAX,%RCX

0x544677 ADD	%RCX,%RDX

0x54467a ADD	%RDX,%RAX

0x54467d CMP	%RAX,%RDX

0x544680 JGE	54478f

0x544686 MOV	0x10(%R12),%RSI

0x54468b VMOVSD	(%R12),%XMM0

0x544691 LEA	(%RSI,%RAX,8),%R8

0x544695 LEA	(%RSI,%RDX,8),%RDI

0x544699 MOV	%R8,%R9

0x54469c SUB	%RDI,%R9

0x54469f SUB	$0x8,%R9

0x5446a3 SHR	$0x3,%R9

0x5446a7 INC	%R9

0x5446aa AND	$0x7,%R9D

0x5446ae JE	544738

0x5446b4 CMP	$0x1,%R9

0x5446b8 JE	544726

0x5446ba CMP	$0x2,%R9

0x5446be JE	544719

0x5446c0 CMP	$0x3,%R9

0x5446c4 JE	54470c

0x5446c6 CMP	$0x4,%R9

0x5446ca JE	5446ff

0x5446cc CMP	$0x5,%R9

0x5446d0 JE	5446f2

0x5446d2 CMP	$0x6,%R9

0x5446d6 JE	5446e5

0x5446d8 VMULSD	(%RDI),%XMM0,%XMM1

0x5446dc ADD	$0x8,%RDI

0x5446e0 VMOVSD	%XMM1,-0x8(%RDI)

0x5446e5 VMULSD	(%RDI),%XMM0,%XMM2

0x5446e9 ADD	$0x8,%RDI

0x5446ed VMOVSD	%XMM2,-0x8(%RDI)

0x5446f2 VMULSD	(%RDI),%XMM0,%XMM3

0x5446f6 ADD	$0x8,%RDI

0x5446fa VMOVSD	%XMM3,-0x8(%RDI)

0x5446ff VMULSD	(%RDI),%XMM0,%XMM4

0x544703 ADD	$0x8,%RDI

0x544707 VMOVSD	%XMM4,-0x8(%RDI)

0x54470c VMULSD	(%RDI),%XMM0,%XMM5

0x544710 ADD	$0x8,%RDI

0x544714 VMOVSD	%XMM5,-0x8(%RDI)

0x544719 VMULSD	(%RDI),%XMM0,%XMM6

0x54471d ADD	$0x8,%RDI

0x544721 VMOVSD	%XMM6,-0x8(%RDI)

0x544726 VMULSD	(%RDI),%XMM0,%XMM7

0x54472a ADD	$0x8,%RDI

0x54472e VMOVSD	%XMM7,-0x8(%RDI)

0x544733 CMP	%RDI,%R8

0x544736 JE	54478f

(2915) 0x544738 VMULSD	(%RDI),%XMM0,%XMM8

(2915) 0x54473c VMULSD	0x8(%RDI),%XMM0,%XMM9

(2915) 0x544741 VMULSD	0x10(%RDI),%XMM0,%XMM10

(2915) 0x544746 VMULSD	0x18(%RDI),%XMM0,%XMM11

(2915) 0x54474b VMULSD	0x20(%RDI),%XMM0,%XMM12

(2915) 0x544750 VMULSD	0x28(%RDI),%XMM0,%XMM13

(2915) 0x544755 VMULSD	0x30(%RDI),%XMM0,%XMM14

(2915) 0x54475a VMULSD	0x38(%RDI),%XMM0,%XMM15

(2915) 0x54475f VMOVSD	%XMM8,(%RDI)

(2915) 0x544763 VMOVSD	%XMM9,0x8(%RDI)

(2915) 0x544768 VMOVSD	%XMM10,0x10(%RDI)

(2915) 0x54476d VMOVSD	%XMM11,0x18(%RDI)

(2915) 0x544772 VMOVSD	%XMM12,0x20(%RDI)

(2915) 0x544777 VMOVSD	%XMM13,0x28(%RDI)

(2915) 0x54477c VMOVSD	%XMM14,0x30(%RDI)

(2915) 0x544781 VMOVSD	%XMM15,0x38(%RDI)

(2915) 0x544786 ADD	$0x40,%RDI

(2915) 0x54478a CMP	%RDI,%R8

(2915) 0x54478d JNE	544738

0x54478f POP	%RBX

0x544790 POP	%R12

0x544792 POP	%RBP

0x544793 RET

0x544794 NOPL	(%RAX)

0x544798 INC	%RAX

0x54479b XOR	%EDX,%EDX

0x54479d JMP	544673

0x5447a2 NOPW	%CS:(%RAX,%RAX,1)

0x5447ad NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○97.52	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.48	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	csr_matvec.c:234-237
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:234-237.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.67 to 6.50 cycles (2.10x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 13.67 to 5.00 cycles (2.73x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.67 to 13.00 cycles (1.05x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:234
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:234

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:236

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:236

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 7 FP arithmetical operations:

7: multiply

The binary function is loading 88 bytes (11 double precision FP elements). The binary function is storing 56 bytes (7 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	76
nb uops	82
loop length	281
used x86 registers	11
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.67 cycles
front end	13.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	9.00	8.50	5.00	5.00	6.00	7.60	7.50	6.00	6.00	6.00	7.40	5.00
cycles	9.00	8.50	5.00	5.00	6.00	7.60	7.50	6.00	6.00	6.00	7.40	5.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	13.67
Dispatch	9.00
DIV/SQRT	10.00
Overall L1	13.67

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.67 cycles. At this rate:

3% of peak load performance is reached (6.44 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.10 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 544640

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4110b0 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOVSXD %EAX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
CALL 4111f0 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV 0x18(%R12),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL 0x8(%R12),%RAX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RBX	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 544798 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0x158>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 54478f <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0x14f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x10(%R12),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R12),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%RSI,%RAX,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RSI,%RDX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDI,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
SUB $0x8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x3,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $0x7,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
JE 544738 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0xf8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544726 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0xe6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544719 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0xd9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 54470c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0xcc>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 5446ff <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0xbf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 5446f2 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0xb2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 5446e5 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0xa5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMULSD (%RDI),%XMM0,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM1,-0x8(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD (%RDI),%XMM0,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM2,-0x8(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD (%RDI),%XMM0,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM3,-0x8(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD (%RDI),%XMM0,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM4,-0x8(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD (%RDI),%XMM0,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM5,-0x8(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD (%RDI),%XMM0,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM6,-0x8(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD (%RDI),%XMM0,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM7,-0x8(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RDI,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 54478f <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0x14f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 544673 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0x33>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	csr_matvec.c:234-237
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:234-237.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.67 to 6.50 cycles (2.10x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.67 to 13.00 cycles (1.05x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:234
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:234

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:236

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:236

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 7 FP arithmetical operations:

7: multiply

The binary function is loading 88 bytes (11 double precision FP elements). The binary function is storing 56 bytes (7 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	76
nb uops	82
loop length	281
used x86 registers	11
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.67 cycles
front end	13.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	9.00	8.50	5.00	5.00	6.00	7.60	7.50	6.00	6.00	6.00	7.40	5.00
cycles	9.00	8.50	5.00	5.00	6.00	7.60	7.50	6.00	6.00	6.00	7.40	5.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	13.67
Dispatch	9.00
DIV/SQRT	10.00
Overall L1	13.67

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.67 cycles. At this rate:

3% of peak load performance is reached (6.44 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.10 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 544640

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4110b0 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOVSXD %EAX,%RBX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
CALL 4111f0 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV 0x18(%R12),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL 0x8(%R12),%RAX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RBX	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 544798 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0x158>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 54478f <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0x14f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x10(%R12),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R12),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%RSI,%RAX,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RSI,%RDX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDI,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
SUB $0x8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x3,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $0x7,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
JE 544738 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0xf8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544726 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0xe6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544719 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0xd9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 54470c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0xcc>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 5446ff <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0xbf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 5446f2 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0xb2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 5446e5 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0xa5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMULSD (%RDI),%XMM0,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM1,-0x8(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD (%RDI),%XMM0,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM2,-0x8(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD (%RDI),%XMM0,%XMM3	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM3,-0x8(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD (%RDI),%XMM0,%XMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM4,-0x8(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD (%RDI),%XMM0,%XMM5	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM5,-0x8(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD (%RDI),%XMM0,%XMM6	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM6,-0x8(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSD (%RDI),%XMM0,%XMM7	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (12.5%)
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD %XMM7,-0x8(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RDI,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 54478f <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0x14f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 544673 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5+0x33>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecOutOfPlace._omp_fn.5–	0.38	0.16
○Loop 2915 - csr_matvec.c:237-237 - exec	0.38	0.14

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code