OV - exec - Function hypre_CSRMatrixMatvecOutOfPlace._omp

	Function: hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3	Module: exec	Source: csr_matvec.c:178-204 [...]	Coverage (incl. loops): 0.05% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 178 - 204

--------------------------------------------------------------------------------

178: #pragma omp parallel for private(i,j,jj,m,tempx) HYPRE_SMP_SCHEDULE

179: #endif

180:

181:          for (i = 0; i < num_rownnz; i++)

182:          {

183:             m = A_rownnz[i];

[...]

191:             if ( num_vectors==1 )

192:             {

193:                tempx = 0;

194:                for (jj = A_i[m]; jj < A_i[m+1]; jj++)

195:                   tempx +=  A_data[jj] * x_data[A_j[jj]];

196:                y_data[m] += tempx;

197:             }

198:             else

199:                for ( j=0; j<num_vectors; ++j )

200:                {

201:                   tempx = 0;

202:                   for (jj = A_i[m]; jj < A_i[m+1]; jj++)

203:                      tempx +=  A_data[jj] * x_data[ j*vecstride_x + A_j[jj]*idxstride_x ];

204:                   y_data[ j*vecstride_y + m*idxstride_y] += tempx;

0x5437a0 PUSH	%RBP

0x5437a1 MOV	%RSP,%RBP

0x5437a4 PUSH	%R15

0x5437a6 PUSH	%R14

0x5437a8 PUSH	%R13

0x5437aa PUSH	%R12

0x5437ac PUSH	%RBX

0x5437ad MOV	%RDI,%RBX

0x5437b0 SUB	$0x38,%RSP

0x5437b4 CALL	4110b0 <omp_get_num_threads@plt>

0x5437b9 MOV	%EAX,%R12D

0x5437bc CALL	4111f0 <omp_get_thread_num@plt>

0x5437c1 MOVSXD	%EAX,%RCX

0x5437c4 MOV	0x20(%RBX),%RAX

0x5437c8 MOVSXD	%R12D,%RSI

0x5437cb CQTO

0x5437cd IDIV	%RSI

0x5437d0 CMP	%RDX,%RCX

0x5437d3 JL	543acb

0x5437d9 IMUL	%RAX,%RCX

0x5437dd LEA	(%RCX,%RDX,1),%RDI

0x5437e1 ADD	%RDI,%RAX

0x5437e4 CMP	%RAX,%RDI

0x5437e7 JGE	543abc

0x5437ed MOV	0x40(%RBX),%R8

0x5437f1 MOV	0x30(%RBX),%R10

0x5437f5 MOV	0x18(%RBX),%R11

0x5437f9 MOV	0x50(%RBX),%R9

0x5437fd MOV	%R8,-0x50(%RBP)

0x543801 MOV	%R10,-0x40(%RBP)

0x543805 MOV	0x58(%RBX),%R13

0x543809 MOV	0x48(%RBX),%R14

0x54380d MOV	0x38(%RBX),%R12

0x543811 MOV	0x28(%RBX),%RDX

0x543815 MOV	0x10(%RBX),%RCX

0x543819 MOV	0x8(%RBX),%R8

0x54381d MOV	(%RBX),%RSI

0x543820 LEA	(%R11,%RDI,8),%RDI

0x543824 CMP	$0x1,%R9

0x543828 JNE	543ad5

0x54382e LEA	(%R11,%RAX,8),%R10

0x543832 MOV	%R10,-0x48(%RBP)

0x543836 MOV	(%RDI),%RAX

0x543839 MOV	%RDI,%R15

0x54383c SAL	$0x3,%R14

0x543840 CMP	$0x1,%R12

0x543844 JE	543f07

0x54384a TEST	%R12,%R12

0x54384d JLE	543a4d

(2907) 0x543853 MOV	-0x50(%RBP),%R9

(2907) 0x543857 MOV	(%R8,%RAX,8),%R11

(2907) 0x54385b MOV	0x8(%R8,%RAX,8),%R10

(2907) 0x543860 IMUL	%R9,%RAX

(2907) 0x543864 MOV	-0x40(%RBP),%RBX

(2907) 0x543868 MOV	%R8,-0x38(%RBP)

(2907) 0x54386c LEA	(%RBX,%RAX,8),%R9

(2907) 0x543870 XOR	%EDI,%EDI

(2907) 0x543872 XOR	%EBX,%EBX

(2907) 0x543874 NOPL	(%RAX)

  (2906) 0x543878 MOV	%R11,%RAX

  (2906) 0x54387b VXORPD	%XMM9,%XMM9,%XMM9

  (2906) 0x543880 CMP	%R11,%R10

  (2906) 0x543883 JLE	543a1b

  (2906) 0x543889 MOV	%R10,%R8

  (2906) 0x54388c SUB	%R11,%R8

  (2906) 0x54388f AND	$0x7,%R8D

  (2906) 0x543893 JE	543968

  (2906) 0x543899 CMP	$0x1,%R8

  (2906) 0x54389d JE	543949

  (2906) 0x5438a3 CMP	$0x2,%R8

  (2906) 0x5438a7 JE	543933

  (2906) 0x5438ad CMP	$0x3,%R8

  (2906) 0x5438b1 JE	54391d

  (2906) 0x5438b3 CMP	$0x4,%R8

  (2906) 0x5438b7 JE	543907

  (2906) 0x5438b9 CMP	$0x5,%R8

  (2906) 0x5438bd JE	5438f1

  (2906) 0x5438bf CMP	$0x6,%R8

  (2906) 0x5438c3 JE	5438db

  (2906) 0x5438c5 MOV	(%RCX,%R11,8),%RAX

  (2906) 0x5438c9 ADD	%RDI,%RAX

  (2906) 0x5438cc VMOVSD	(%RDX,%RAX,8),%XMM4

  (2906) 0x5438d1 LEA	0x1(%R11),%RAX

  (2906) 0x5438d5 VFMADD231SD	(%RSI,%R11,8),%XMM4,%XMM9

  (2906) 0x5438db MOV	(%RCX,%RAX,8),%R8

  (2906) 0x5438df ADD	%RDI,%R8

  (2906) 0x5438e2 VMOVSD	(%RDX,%R8,8),%XMM5

  (2906) 0x5438e8 VFMADD231SD	(%RSI,%RAX,8),%XMM5,%XMM9

  (2906) 0x5438ee INC	%RAX

  (2906) 0x5438f1 MOV	(%RCX,%RAX,8),%R8

  (2906) 0x5438f5 ADD	%RDI,%R8

  (2906) 0x5438f8 VMOVSD	(%RDX,%R8,8),%XMM7

  (2906) 0x5438fe VFMADD231SD	(%RSI,%RAX,8),%XMM7,%XMM9

  (2906) 0x543904 INC	%RAX

  (2906) 0x543907 MOV	(%RCX,%RAX,8),%R8

  (2906) 0x54390b ADD	%RDI,%R8

  (2906) 0x54390e VMOVSD	(%RDX,%R8,8),%XMM1

  (2906) 0x543914 VFMADD231SD	(%RSI,%RAX,8),%XMM1,%XMM9

  (2906) 0x54391a INC	%RAX

  (2906) 0x54391d MOV	(%RCX,%RAX,8),%R8

  (2906) 0x543921 ADD	%RDI,%R8

  (2906) 0x543924 VMOVSD	(%RDX,%R8,8),%XMM2

  (2906) 0x54392a VFMADD231SD	(%RSI,%RAX,8),%XMM2,%XMM9

  (2906) 0x543930 INC	%RAX

  (2906) 0x543933 MOV	(%RCX,%RAX,8),%R8

  (2906) 0x543937 ADD	%RDI,%R8

  (2906) 0x54393a VMOVSD	(%RDX,%R8,8),%XMM6

  (2906) 0x543940 VFMADD231SD	(%RSI,%RAX,8),%XMM6,%XMM9

  (2906) 0x543946 INC	%RAX

  (2906) 0x543949 MOV	(%RCX,%RAX,8),%R8

  (2906) 0x54394d ADD	%RDI,%R8

  (2906) 0x543950 VMOVSD	(%RDX,%R8,8),%XMM3

  (2906) 0x543956 VFMADD231SD	(%RSI,%RAX,8),%XMM3,%XMM9

  (2906) 0x54395c INC	%RAX

  (2906) 0x54395f CMP	%R10,%RAX

  (2906) 0x543962 JE	543a1b

    (2908) 0x543968 MOV	(%RCX,%RAX,8),%R8

    (2908) 0x54396c ADD	%RDI,%R8

    (2908) 0x54396f VMOVSD	(%RDX,%R8,8),%XMM10

    (2908) 0x543975 MOV	0x8(%RCX,%RAX,8),%R8

    (2908) 0x54397a VFMADD231SD	(%RSI,%RAX,8),%XMM10,%XMM9

    (2908) 0x543980 ADD	%RDI,%R8

    (2908) 0x543983 VMOVSD	(%RDX,%R8,8),%XMM11

    (2908) 0x543989 MOV	0x10(%RCX,%RAX,8),%R8

    (2908) 0x54398e VFMADD231SD	0x8(%RSI,%RAX,8),%XMM11,%XMM9

    (2908) 0x543995 ADD	%RDI,%R8

    (2908) 0x543998 VMOVSD	(%RDX,%R8,8),%XMM12

    (2908) 0x54399e MOV	0x18(%RCX,%RAX,8),%R8

    (2908) 0x5439a3 VFMADD231SD	0x10(%RSI,%RAX,8),%XMM12,%XMM9

    (2908) 0x5439aa ADD	%RDI,%R8

    (2908) 0x5439ad VMOVSD	(%RDX,%R8,8),%XMM13

    (2908) 0x5439b3 MOV	0x20(%RCX,%RAX,8),%R8

    (2908) 0x5439b8 VFMADD231SD	0x18(%RSI,%RAX,8),%XMM13,%XMM9

    (2908) 0x5439bf ADD	%RDI,%R8

    (2908) 0x5439c2 VMOVSD	(%RDX,%R8,8),%XMM14

    (2908) 0x5439c8 MOV	0x28(%RCX,%RAX,8),%R8

    (2908) 0x5439cd VFMADD231SD	0x20(%RSI,%RAX,8),%XMM14,%XMM9

    (2908) 0x5439d4 ADD	%RDI,%R8

    (2908) 0x5439d7 VMOVSD	(%RDX,%R8,8),%XMM15

    (2908) 0x5439dd MOV	0x30(%RCX,%RAX,8),%R8

    (2908) 0x5439e2 VFMADD231SD	0x28(%RSI,%RAX,8),%XMM15,%XMM9

    (2908) 0x5439e9 ADD	%RDI,%R8

    (2908) 0x5439ec VMOVSD	(%RDX,%R8,8),%XMM0

    (2908) 0x5439f2 MOV	0x38(%RCX,%RAX,8),%R8

    (2908) 0x5439f7 VFMADD231SD	0x30(%RSI,%RAX,8),%XMM0,%XMM9

    (2908) 0x5439fe ADD	%RDI,%R8

    (2908) 0x543a01 VMOVSD	(%RDX,%R8,8),%XMM8

    (2908) 0x543a07 VFMADD231SD	0x38(%RSI,%RAX,8),%XMM8,%XMM9

    (2908) 0x543a0e ADD	$0x8,%RAX

    (2908) 0x543a12 CMP	%R10,%RAX

    (2908) 0x543a15 JNE	543968

  (2906) 0x543a1b VADDSD	(%R9),%XMM9,%XMM9

  (2906) 0x543a20 INC	%RBX

  (2906) 0x543a23 ADD	%R13,%RDI

  (2906) 0x543a26 VMOVSD	%XMM9,(%R9)

  (2906) 0x543a2b ADD	%R14,%R9

  (2906) 0x543a2e CMP	%RBX,%R12

  (2906) 0x543a31 JNE	543878

(2907) 0x543a37 ADD	$0x8,%R15

(2907) 0x543a3b MOV	-0x38(%RBP),%R8

(2907) 0x543a3f CMP	%R15,-0x48(%RBP)

(2907) 0x543a43 JE	543abc

(2907) 0x543a45 MOV	(%R15),%RAX

(2907) 0x543a48 JMP	543853

0x543a4d MOV	-0x48(%RBP),%RDX

0x543a51 SUB	%RDI,%RDX

0x543a54 SUB	$0x8,%RDX

0x543a58 SHR	$0x3,%RDX

0x543a5c INC	%RDX

0x543a5f AND	$0x7,%EDX

0x543a62 JE	543aaf

0x543a64 CMP	$0x1,%RDX

0x543a68 JE	543aa2

0x543a6a CMP	$0x2,%RDX

0x543a6e JE	543a9e

0x543a70 CMP	$0x3,%RDX

0x543a74 JE	543a9a

0x543a76 CMP	$0x4,%RDX

0x543a7a JE	543a96

0x543a7c CMP	$0x5,%RDX

0x543a80 JE	543a92

0x543a82 ADD	$0x8,%RDI

0x543a86 CMP	$0x6,%RDX

0x543a8a CMOVNE	%RDI,%R15

0x543a8e ADD	$0x8,%R15

0x543a92 ADD	$0x8,%R15

0x543a96 ADD	$0x8,%R15

0x543a9a ADD	$0x8,%R15

0x543a9e ADD	$0x8,%R15

0x543aa2 MOV	-0x48(%RBP),%RCX

0x543aa6 ADD	$0x8,%R15

0x543aaa CMP	%RCX,%R15

0x543aad JE	543abc

(2905) 0x543aaf MOV	-0x48(%RBP),%RSI

(2905) 0x543ab3 ADD	$0x40,%R15

(2905) 0x543ab7 CMP	%RSI,%R15

(2905) 0x543aba JNE	543aaf

0x543abc ADD	$0x38,%RSP

0x543ac0 POP	%RBX

0x543ac1 POP	%R12

0x543ac3 POP	%R13

0x543ac5 POP	%R14

0x543ac7 POP	%R15

0x543ac9 POP	%RBP

0x543aca RET

0x543acb INC	%RAX

0x543ace XOR	%EDX,%EDX

0x543ad0 JMP	5437d9

0x543ad5 LEA	(%R11,%RAX,8),%R15

0x543ad9 MOV	%R15,-0x38(%RBP)

0x543add MOV	%RDI,%R10

0x543ae0 MOV	(%RDI),%R15

0x543ae3 LEA	(,%R14,8),%RBX

0x543aeb CMP	$0x1,%R12

0x543aef JE	543e9b

0x543af5 TEST	%R12,%R12

0x543af8 JLE	5440b5

0x543afe MOV	%R15,%RDI

0x543b01 MOV	%R8,%RAX

0x543b04 MOV	%RBX,%R15

0x543b07 MOV	%R10,%R8

(2901) 0x543b0a MOV	-0x50(%RBP),%R14

(2901) 0x543b0e MOV	(%RAX,%RDI,8),%RBX

(2901) 0x543b12 MOV	0x8(%RAX,%RDI,8),%R11

(2901) 0x543b17 IMUL	%R14,%RDI

(2901) 0x543b1b MOV	-0x40(%RBP),%R10

(2901) 0x543b1f MOV	%RAX,-0x48(%RBP)

(2901) 0x543b23 MOV	%R8,-0x58(%RBP)

(2901) 0x543b27 LEA	(%R10,%RDI,8),%R10

(2901) 0x543b2b XOR	%R14D,%R14D

(2901) 0x543b2e XOR	%EDI,%EDI

  (2900) 0x543b30 MOV	%RBX,%RAX

  (2900) 0x543b33 VXORPD	%XMM0,%XMM0,%XMM0

  (2900) 0x543b37 CMP	%R11,%RBX

  (2900) 0x543b3a JGE	543d00

  (2900) 0x543b40 MOV	%R11,%R8

  (2900) 0x543b43 SUB	%RBX,%R8

  (2900) 0x543b46 AND	$0x7,%R8D

  (2900) 0x543b4a JE	543c35

  (2900) 0x543b50 CMP	$0x1,%R8

  (2900) 0x543b54 JE	543c13

  (2900) 0x543b5a CMP	$0x2,%R8

  (2900) 0x543b5e JE	543bfa

  (2900) 0x543b64 CMP	$0x3,%R8

  (2900) 0x543b68 JE	543be1

  (2900) 0x543b6a CMP	$0x4,%R8

  (2900) 0x543b6e JE	543bc8

  (2900) 0x543b70 CMP	$0x5,%R8

  (2900) 0x543b74 JE	543baf

  (2900) 0x543b76 CMP	$0x6,%R8

  (2900) 0x543b7a JE	543b96

  (2900) 0x543b7c MOV	(%RCX,%RBX,8),%RAX

  (2900) 0x543b80 VMOVSD	(%RSI,%RBX,8),%XMM4

  (2900) 0x543b85 IMUL	%R9,%RAX

  (2900) 0x543b89 ADD	%RDI,%RAX

  (2900) 0x543b8c VFMADD231SD	(%RDX,%RAX,8),%XMM4,%XMM0

  (2900) 0x543b92 LEA	0x1(%RBX),%RAX

  (2900) 0x543b96 MOV	(%RCX,%RAX,8),%R8

  (2900) 0x543b9a VMOVSD	(%RSI,%RAX,8),%XMM5

  (2900) 0x543b9f IMUL	%R9,%R8

  (2900) 0x543ba3 INC	%RAX

  (2900) 0x543ba6 ADD	%RDI,%R8

  (2900) 0x543ba9 VFMADD231SD	(%RDX,%R8,8),%XMM5,%XMM0

  (2900) 0x543baf MOV	(%RCX,%RAX,8),%R8

  (2900) 0x543bb3 VMOVSD	(%RSI,%RAX,8),%XMM7

  (2900) 0x543bb8 IMUL	%R9,%R8

  (2900) 0x543bbc INC	%RAX

  (2900) 0x543bbf ADD	%RDI,%R8

  (2900) 0x543bc2 VFMADD231SD	(%RDX,%R8,8),%XMM7,%XMM0

  (2900) 0x543bc8 MOV	(%RCX,%RAX,8),%R8

  (2900) 0x543bcc VMOVSD	(%RSI,%RAX,8),%XMM1

  (2900) 0x543bd1 IMUL	%R9,%R8

  (2900) 0x543bd5 INC	%RAX

  (2900) 0x543bd8 ADD	%RDI,%R8

  (2900) 0x543bdb VFMADD231SD	(%RDX,%R8,8),%XMM1,%XMM0

  (2900) 0x543be1 MOV	(%RCX,%RAX,8),%R8

  (2900) 0x543be5 VMOVSD	(%RSI,%RAX,8),%XMM2

  (2900) 0x543bea IMUL	%R9,%R8

  (2900) 0x543bee INC	%RAX

  (2900) 0x543bf1 ADD	%RDI,%R8

  (2900) 0x543bf4 VFMADD231SD	(%RDX,%R8,8),%XMM2,%XMM0

  (2900) 0x543bfa MOV	(%RCX,%RAX,8),%R8

  (2900) 0x543bfe VMOVSD	(%RSI,%RAX,8),%XMM6

  (2900) 0x543c03 IMUL	%R9,%R8

  (2900) 0x543c07 INC	%RAX

  (2900) 0x543c0a ADD	%RDI,%R8

  (2900) 0x543c0d VFMADD231SD	(%RDX,%R8,8),%XMM6,%XMM0

  (2900) 0x543c13 MOV	(%RCX,%RAX,8),%R8

  (2900) 0x543c17 VMOVSD	(%RSI,%RAX,8),%XMM3

  (2900) 0x543c1c IMUL	%R9,%R8

  (2900) 0x543c20 INC	%RAX

  (2900) 0x543c23 ADD	%RDI,%R8

  (2900) 0x543c26 VFMADD231SD	(%RDX,%R8,8),%XMM3,%XMM0

  (2900) 0x543c2c CMP	%R11,%RAX

  (2900) 0x543c2f JE	543d00

    (2902) 0x543c35 MOV	(%RCX,%RAX,8),%R8

    (2902) 0x543c39 VMOVSD	(%RSI,%RAX,8),%XMM8

    (2902) 0x543c3e IMUL	%R9,%R8

    (2902) 0x543c42 VMOVSD	0x8(%RSI,%RAX,8),%XMM9

    (2902) 0x543c48 VMOVSD	0x10(%RSI,%RAX,8),%XMM10

    (2902) 0x543c4e ADD	%RDI,%R8

    (2902) 0x543c51 VFMADD231SD	(%RDX,%R8,8),%XMM8,%XMM0

    (2902) 0x543c57 MOV	0x8(%RCX,%RAX,8),%R8

    (2902) 0x543c5c VMOVSD	0x18(%RSI,%RAX,8),%XMM11

    (2902) 0x543c62 IMUL	%R9,%R8

    (2902) 0x543c66 VMOVSD	0x20(%RSI,%RAX,8),%XMM12

    (2902) 0x543c6c VMOVSD	0x28(%RSI,%RAX,8),%XMM13

    (2902) 0x543c72 ADD	%RDI,%R8

    (2902) 0x543c75 VFMADD231SD	(%RDX,%R8,8),%XMM9,%XMM0

    (2902) 0x543c7b MOV	0x10(%RCX,%RAX,8),%R8

    (2902) 0x543c80 VMOVSD	0x30(%RSI,%RAX,8),%XMM14

    (2902) 0x543c86 IMUL	%R9,%R8

    (2902) 0x543c8a VMOVSD	0x38(%RSI,%RAX,8),%XMM15

    (2902) 0x543c90 ADD	%RDI,%R8

    (2902) 0x543c93 VFMADD231SD	(%RDX,%R8,8),%XMM10,%XMM0

    (2902) 0x543c99 MOV	0x18(%RCX,%RAX,8),%R8

    (2902) 0x543c9e IMUL	%R9,%R8

    (2902) 0x543ca2 ADD	%RDI,%R8

    (2902) 0x543ca5 VFMADD231SD	(%RDX,%R8,8),%XMM11,%XMM0

    (2902) 0x543cab MOV	0x20(%RCX,%RAX,8),%R8

    (2902) 0x543cb0 IMUL	%R9,%R8

    (2902) 0x543cb4 ADD	%RDI,%R8

    (2902) 0x543cb7 VFMADD231SD	(%RDX,%R8,8),%XMM12,%XMM0

    (2902) 0x543cbd MOV	0x28(%RCX,%RAX,8),%R8

    (2902) 0x543cc2 IMUL	%R9,%R8

    (2902) 0x543cc6 ADD	%RDI,%R8

    (2902) 0x543cc9 VFMADD231SD	(%RDX,%R8,8),%XMM13,%XMM0

    (2902) 0x543ccf MOV	0x30(%RCX,%RAX,8),%R8

    (2902) 0x543cd4 IMUL	%R9,%R8

    (2902) 0x543cd8 ADD	%RDI,%R8

    (2902) 0x543cdb VFMADD231SD	(%RDX,%R8,8),%XMM14,%XMM0

    (2902) 0x543ce1 MOV	0x38(%RCX,%RAX,8),%R8

    (2902) 0x543ce6 ADD	$0x8,%RAX

    (2902) 0x543cea IMUL	%R9,%R8

    (2902) 0x543cee ADD	%RDI,%R8

    (2902) 0x543cf1 VFMADD231SD	(%RDX,%R8,8),%XMM15,%XMM0

    (2902) 0x543cf7 CMP	%R11,%RAX

    (2902) 0x543cfa JNE	543c35

  (2900) 0x543d00 VADDSD	(%R10),%XMM0,%XMM0

  (2900) 0x543d05 INC	%R14

  (2900) 0x543d08 ADD	%R13,%RDI

  (2900) 0x543d0b VMOVSD	%XMM0,(%R10)

  (2900) 0x543d10 ADD	%R15,%R10

  (2900) 0x543d13 CMP	%R14,%R12

  (2900) 0x543d16 JNE	543b30

(2901) 0x543d1c MOV	-0x58(%RBP),%R8

(2901) 0x543d20 MOV	-0x38(%RBP),%RBX

(2901) 0x543d24 ADD	$0x8,%R8

(2901) 0x543d28 MOV	-0x48(%RBP),%RAX

(2901) 0x543d2c CMP	%RBX,%R8

(2901) 0x543d2f JE	543abc

(2901) 0x543d35 MOV	(%R8),%RDI

(2901) 0x543d38 JMP	543b0a

(2897) 0x543d3d MOV	(%RCX,%R13,8),%R11

(2897) 0x543d41 VMOVSD	(%RSI,%R13,8),%XMM4

(2897) 0x543d47 INC	%R13

(2897) 0x543d4a VFMADD231SD	(%RDX,%R11,8),%XMM4,%XMM8

(2897) 0x543d50 MOV	(%RCX,%R13,8),%RDI

(2897) 0x543d54 VMOVSD	(%RSI,%R13,8),%XMM5

(2897) 0x543d5a INC	%R13

(2897) 0x543d5d VFMADD231SD	(%RDX,%RDI,8),%XMM5,%XMM8

(2897) 0x543d63 MOV	(%RCX,%R13,8),%R14

(2897) 0x543d67 VMOVSD	(%RSI,%R13,8),%XMM7

(2897) 0x543d6d INC	%R13

(2897) 0x543d70 VFMADD231SD	(%RDX,%R14,8),%XMM7,%XMM8

(2897) 0x543d76 MOV	(%RCX,%R13,8),%RAX

(2897) 0x543d7a VMOVSD	(%RSI,%R13,8),%XMM1

(2897) 0x543d80 INC	%R13

(2897) 0x543d83 VFMADD231SD	(%RDX,%RAX,8),%XMM1,%XMM8

(2897) 0x543d89 MOV	(%RCX,%R13,8),%RBX

(2897) 0x543d8d VMOVSD	(%RSI,%R13,8),%XMM2

(2897) 0x543d93 INC	%R13

(2897) 0x543d96 VFMADD231SD	(%RDX,%RBX,8),%XMM2,%XMM8

(2897) 0x543d9c MOV	(%RCX,%R13,8),%R15

(2897) 0x543da0 VMOVSD	(%RSI,%R13,8),%XMM6

(2897) 0x543da6 INC	%R13

(2897) 0x543da9 VFMADD231SD	(%RDX,%R15,8),%XMM6,%XMM8

(2897) 0x543daf MOV	(%RCX,%R13,8),%R11

(2897) 0x543db3 VMOVSD	(%RSI,%R13,8),%XMM3

(2897) 0x543db9 INC	%R13

(2897) 0x543dbc VFMADD231SD	(%RDX,%R11,8),%XMM3,%XMM8

(2897) 0x543dc2 CMP	%R9,%R13

(2897) 0x543dc5 JE	543e74

  (2898) 0x543dcb MOV	(%RCX,%R13,8),%RDI

  (2898) 0x543dcf VMOVSD	(%RSI,%R13,8),%XMM9

  (2898) 0x543dd5 LEA	0x1(%R13),%R14

  (2898) 0x543dd9 VFMADD231SD	(%RDX,%RDI,8),%XMM9,%XMM8

  (2898) 0x543ddf MOV	(%RCX,%R14,8),%RAX

  (2898) 0x543de3 VMOVSD	(%RSI,%R14,8),%XMM10

  (2898) 0x543de9 LEA	0x2(%R13),%R15

  (2898) 0x543ded MOV	(%RCX,%R15,8),%RBX

  (2898) 0x543df1 VFMADD231SD	(%RDX,%RAX,8),%XMM10,%XMM8

  (2898) 0x543df7 VMOVSD	(%RSI,%R15,8),%XMM11

  (2898) 0x543dfd LEA	0x3(%R13),%R11

  (2898) 0x543e01 MOV	(%RCX,%R11,8),%RDI

  (2898) 0x543e05 VMOVSD	(%RSI,%R11,8),%XMM12

  (2898) 0x543e0b VFMADD231SD	(%RDX,%RBX,8),%XMM11,%XMM8

  (2898) 0x543e11 LEA	0x4(%R13),%R14

  (2898) 0x543e15 MOV	(%RCX,%R14,8),%RAX

  (2898) 0x543e19 VMOVSD	(%RSI,%R14,8),%XMM13

  (2898) 0x543e1f LEA	0x5(%R13),%R15

  (2898) 0x543e23 VFMADD231SD	(%RDX,%RDI,8),%XMM12,%XMM8

  (2898) 0x543e29 MOV	(%RCX,%R15,8),%RBX

  (2898) 0x543e2d VMOVSD	(%RSI,%R15,8),%XMM14

  (2898) 0x543e33 LEA	0x6(%R13),%R11

  (2898) 0x543e37 MOV	(%RCX,%R11,8),%RDI

  (2898) 0x543e3b VFMADD231SD	(%RDX,%RAX,8),%XMM13,%XMM8

  (2898) 0x543e41 VMOVSD	(%RSI,%R11,8),%XMM15

  (2898) 0x543e47 LEA	0x7(%R13),%R14

  (2898) 0x543e4b MOV	(%RCX,%R14,8),%RAX

  (2898) 0x543e4f VMOVSD	(%RSI,%R14,8),%XMM0

  (2898) 0x543e55 VFMADD231SD	(%RDX,%RBX,8),%XMM14,%XMM8

  (2898) 0x543e5b ADD	$0x8,%R13

  (2898) 0x543e5f VFMADD231SD	(%RDX,%RDI,8),%XMM15,%XMM8

  (2898) 0x543e65 VFMADD231SD	(%RDX,%RAX,8),%XMM0,%XMM8

  (2898) 0x543e6b CMP	%R9,%R13

  (2898) 0x543e6e JNE	543dcb

(2897) 0x543e74 MOV	-0x40(%RBP),%R13

(2897) 0x543e78 ADD	$0x8,%R10

(2897) 0x543e7c ADD	%R13,%R12

(2897) 0x543e7f VADDSD	(%R12),%XMM8,%XMM8

(2897) 0x543e85 VMOVSD	%XMM8,(%R12)

(2897) 0x543e8b MOV	-0x38(%RBP),%R12

(2897) 0x543e8f CMP	%R12,%R10

(2897) 0x543e92 JE	543abc

(2897) 0x543e98 MOV	(%R10),%R15

(2897) 0x543e9b LEA	(,%R15,8),%R12

(2897) 0x543ea3 MOV	(%R8,%R15,8),%R13

(2897) 0x543ea7 MOV	0x8(%R8,%R12,1),%R9

(2897) 0x543eac VXORPD	%XMM8,%XMM8,%XMM8

(2897) 0x543eb1 CMP	%R9,%R13

(2897) 0x543eb4 JGE	543e74

(2897) 0x543eb6 MOV	%R9,%R15

(2897) 0x543eb9 SUB	%R13,%R15

(2897) 0x543ebc AND	$0x7,%R15D

(2897) 0x543ec0 JE	543dcb

(2897) 0x543ec6 CMP	$0x1,%R15

(2897) 0x543eca JE	543daf

(2897) 0x543ed0 CMP	$0x2,%R15

(2897) 0x543ed4 JE	543d9c

(2897) 0x543eda CMP	$0x3,%R15

(2897) 0x543ede JE	543d89

(2897) 0x543ee4 CMP	$0x4,%R15

(2897) 0x543ee8 JE	543d76

(2897) 0x543eee CMP	$0x5,%R15

(2897) 0x543ef2 JE	543d63

(2897) 0x543ef8 CMP	$0x6,%R15

(2897) 0x543efc JE	543d50

(2897) 0x543f02 JMP	543d3d

0x543f07 MOV	-0x40(%RBP),%R14

0x543f0b MOV	-0x48(%RBP),%R13

(2903) 0x543f0f LEA	(,%RAX,8),%R10

(2903) 0x543f17 MOV	(%R8,%RAX,8),%R9

(2903) 0x543f1b MOV	0x8(%R8,%R10,1),%R11

(2903) 0x543f20 VXORPD	%XMM10,%XMM10,%XMM10

(2903) 0x543f25 CMP	%R9,%R11

(2903) 0x543f28 JLE	544093

(2903) 0x543f2e MOV	%R11,%R12

(2903) 0x543f31 SUB	%R9,%R12

(2903) 0x543f34 AND	$0x7,%R12D

(2903) 0x543f38 JE	543fee

(2903) 0x543f3e CMP	$0x1,%R12

(2903) 0x543f42 JE	543fd3

(2903) 0x543f48 CMP	$0x2,%R12

(2903) 0x543f4c JE	543fc1

(2903) 0x543f4e CMP	$0x3,%R12

(2903) 0x543f52 JE	543faf

(2903) 0x543f54 CMP	$0x4,%R12

(2903) 0x543f58 JE	543f9c

(2903) 0x543f5a CMP	$0x5,%R12

(2903) 0x543f5e JE	543f8a

(2903) 0x543f60 CMP	$0x6,%R12

(2903) 0x543f64 JE	543f78

(2903) 0x543f66 MOV	(%RCX,%R9,8),%RDI

(2903) 0x543f6a VMOVSD	(%RDX,%RDI,8),%XMM4

(2903) 0x543f6f VFMADD231SD	(%RSI,%R9,8),%XMM4,%XMM10

(2903) 0x543f75 INC	%R9

(2903) 0x543f78 MOV	(%RCX,%R9,8),%RBX

(2903) 0x543f7c VMOVSD	(%RDX,%RBX,8),%XMM5

(2903) 0x543f81 VFMADD231SD	(%RSI,%R9,8),%XMM5,%XMM10

(2903) 0x543f87 INC	%R9

(2903) 0x543f8a MOV	(%RCX,%R9,8),%RAX

(2903) 0x543f8e VMOVSD	(%RDX,%RAX,8),%XMM7

(2903) 0x543f93 VFMADD231SD	(%RSI,%R9,8),%XMM7,%XMM10

(2903) 0x543f99 INC	%R9

(2903) 0x543f9c MOV	(%RCX,%R9,8),%R12

(2903) 0x543fa0 VMOVSD	(%RDX,%R12,8),%XMM1

(2903) 0x543fa6 VFMADD231SD	(%RSI,%R9,8),%XMM1,%XMM10

(2903) 0x543fac INC	%R9

(2903) 0x543faf MOV	(%RCX,%R9,8),%RDI

(2903) 0x543fb3 VMOVSD	(%RDX,%RDI,8),%XMM2

(2903) 0x543fb8 VFMADD231SD	(%RSI,%R9,8),%XMM2,%XMM10

(2903) 0x543fbe INC	%R9

(2903) 0x543fc1 MOV	(%RCX,%R9,8),%RBX

(2903) 0x543fc5 VMOVSD	(%RDX,%RBX,8),%XMM6

(2903) 0x543fca VFMADD231SD	(%RSI,%R9,8),%XMM6,%XMM10

(2903) 0x543fd0 INC	%R9

(2903) 0x543fd3 MOV	(%RCX,%R9,8),%RAX

(2903) 0x543fd7 VMOVSD	(%RDX,%RAX,8),%XMM3

(2903) 0x543fdc VFMADD231SD	(%RSI,%R9,8),%XMM3,%XMM10

(2903) 0x543fe2 INC	%R9

(2903) 0x543fe5 CMP	%R11,%R9

(2903) 0x543fe8 JE	544093

  (2904) 0x543fee MOV	(%RCX,%R9,8),%R12

  (2904) 0x543ff2 LEA	0x1(%R9),%RDI

  (2904) 0x543ff6 VMOVSD	(%RDX,%R12,8),%XMM11

  (2904) 0x543ffc MOV	(%RCX,%RDI,8),%RBX

  (2904) 0x544000 VFMADD231SD	(%RSI,%R9,8),%XMM11,%XMM10

  (2904) 0x544006 VMOVSD	(%RDX,%RBX,8),%XMM12

  (2904) 0x54400b LEA	0x2(%R9),%RAX

  (2904) 0x54400f MOV	(%RCX,%RAX,8),%R12

  (2904) 0x544013 VFMADD231SD	(%RSI,%RDI,8),%XMM12,%XMM10

  (2904) 0x544019 VMOVSD	(%RDX,%R12,8),%XMM13

  (2904) 0x54401f LEA	0x3(%R9),%RDI

  (2904) 0x544023 MOV	(%RCX,%RDI,8),%RBX

  (2904) 0x544027 VFMADD231SD	(%RSI,%RAX,8),%XMM13,%XMM10

  (2904) 0x54402d VMOVSD	(%RDX,%RBX,8),%XMM14

  (2904) 0x544032 LEA	0x4(%R9),%RAX

  (2904) 0x544036 MOV	(%RCX,%RAX,8),%R12

  (2904) 0x54403a VFMADD231SD	(%RSI,%RDI,8),%XMM14,%XMM10

  (2904) 0x544040 VMOVSD	(%RDX,%R12,8),%XMM15

  (2904) 0x544046 LEA	0x5(%R9),%RDI

  (2904) 0x54404a MOV	(%RCX,%RDI,8),%RBX

  (2904) 0x54404e VFMADD231SD	(%RSI,%RAX,8),%XMM15,%XMM10

  (2904) 0x544054 VMOVSD	(%RDX,%RBX,8),%XMM0

  (2904) 0x544059 LEA	0x6(%R9),%RAX

  (2904) 0x54405d MOV	(%RCX,%RAX,8),%R12

  (2904) 0x544061 VFMADD231SD	(%RSI,%RDI,8),%XMM0,%XMM10

  (2904) 0x544067 VMOVSD	(%RDX,%R12,8),%XMM8

  (2904) 0x54406d LEA	0x7(%R9),%RDI

  (2904) 0x544071 MOV	(%RCX,%RDI,8),%RBX

  (2904) 0x544075 ADD	$0x8,%R9

  (2904) 0x544079 VFMADD231SD	(%RSI,%RAX,8),%XMM8,%XMM10

  (2904) 0x54407f VMOVSD	(%RDX,%RBX,8),%XMM9

  (2904) 0x544084 VFMADD231SD	(%RSI,%RDI,8),%XMM9,%XMM10

  (2904) 0x54408a CMP	%R11,%R9

  (2904) 0x54408d JNE	543fee

(2903) 0x544093 ADD	%R14,%R10

(2903) 0x544096 VADDSD	(%R10),%XMM10,%XMM10

(2903) 0x54409b ADD	$0x8,%R15

(2903) 0x54409f VMOVSD	%XMM10,(%R10)

(2903) 0x5440a4 CMP	%R15,%R13

(2903) 0x5440a7 JE	543abc

(2903) 0x5440ad MOV	(%R15),%RAX

(2903) 0x5440b0 JMP	543f0f

0x5440b5 MOV	-0x38(%RBP),%RAX

0x5440b9 SUB	%RDI,%RAX

0x5440bc SUB	$0x8,%RAX

0x5440c0 SHR	$0x3,%RAX

0x5440c4 INC	%RAX

0x5440c7 AND	$0x7,%EAX

0x5440ca JE	54411b

0x5440cc CMP	$0x1,%RAX

0x5440d0 JE	54410a

0x5440d2 CMP	$0x2,%RAX

0x5440d6 JE	544106

0x5440d8 CMP	$0x3,%RAX

0x5440dc JE	544102

0x5440de CMP	$0x4,%RAX

0x5440e2 JE	5440fe

0x5440e4 CMP	$0x5,%RAX

0x5440e8 JE	5440fa

0x5440ea ADD	$0x8,%RDI

0x5440ee CMP	$0x6,%RAX

0x5440f2 CMOVNE	%RDI,%R10

0x5440f6 ADD	$0x8,%R10

0x5440fa ADD	$0x8,%R10

0x5440fe ADD	$0x8,%R10

0x544102 ADD	$0x8,%R10

0x544106 ADD	$0x8,%R10

0x54410a MOV	-0x38(%RBP),%R13

0x54410e ADD	$0x8,%R10

0x544112 CMP	%R13,%R10

0x544115 JE	543abc

(2899) 0x54411b MOV	-0x38(%RBP),%R9

(2899) 0x54411f ADD	$0x40,%R10

(2899) 0x544123 CMP	%R9,%R10

(2899) 0x544126 JNE	54411b

0x544128 JMP	543abc

0x54412d NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○98.18	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○1.82	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	csr_matvec.c:178-204
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178-183,191-204.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 23.50 to 5.00 cycles (4.70x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 160 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	135
nb uops	141
loop length	473
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.50 cycles
front end	23.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.00	10.80	9.00	9.00	6.00	10.60	14.00	6.00	6.00	6.00	10.60	9.00
cycles	14.00	10.80	9.00	9.00	6.00	10.60	14.00	6.00	6.00	6.00	10.60	9.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	23.50
Dispatch	14.00
DIV/SQRT	10.00
Overall L1	23.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.50 cycles. At this rate:

3% of peak load performance is reached (6.81 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.36 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 23.50 to 14.00 cycles (1.68x speedup).

ASM code

In the binary file, the address of the function is: 5437a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4110b0 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 4111f0 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV 0x20(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %R12D,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RSI	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 543acb <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x32b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RCX,%RDX,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 543abc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x31c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x40(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x50(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R8,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x58(%RBX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x48(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RBX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x28(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%R11,%RDI,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x1,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 543ad5 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x335>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R11,%RAX,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3,%R14	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
CMP $0x1,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 543f07 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x767>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 543a4d <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x2ad>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 543aaf <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x30f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 543aa2 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x302>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 543a9e <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x2fe>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 543a9a <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x2fa>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 543a96 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x2f6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 543a92 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x2f2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVNE %RDI,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x48(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RCX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 543abc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x31c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 5437d9 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x39>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
LEA (%R11,%RAX,8),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (,%R14,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x1,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 543e9b <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x6fb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 5440b5 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x915>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x40(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 54411b <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x97b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 54410a <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x96a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544106 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x966>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544102 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x962>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 5440fe <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x95e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 5440fa <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x95a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVNE %RDI,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JE 543abc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x31c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 543abc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x31c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	csr_matvec.c:178-204
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178-183,191-204.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 160 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	135
nb uops	141
loop length	473
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.50 cycles
front end	23.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.00	10.80	9.00	9.00	6.00	10.60	14.00	6.00	6.00	6.00	10.60	9.00
cycles	14.00	10.80	9.00	9.00	6.00	10.60	14.00	6.00	6.00	6.00	10.60	9.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	23.50
Dispatch	14.00
DIV/SQRT	10.00
Overall L1	23.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.50 cycles. At this rate:

3% of peak load performance is reached (6.81 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.36 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 5437a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4110b0 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 4111f0 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV 0x20(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %R12D,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RSI	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 543acb <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x32b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RCX,%RDX,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 543abc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x31c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x40(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x50(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R8,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x58(%RBX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x48(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RBX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x28(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%R11,%RDI,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x1,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 543ad5 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x335>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R11,%RAX,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SAL $0x3,%R14	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
CMP $0x1,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 543f07 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x767>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 543a4d <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x2ad>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 543aaf <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x30f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 543aa2 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x302>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 543a9e <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x2fe>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 543a9a <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x2fa>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 543a96 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x2f6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 543a92 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x2f2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVNE %RDI,%R15	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x48(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %RCX,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 543abc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x31c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 5437d9 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x39>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
LEA (%R11,%RAX,8),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (,%R14,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP $0x1,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 543e9b <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x6fb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 5440b5 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x915>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x40(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RDI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 54411b <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x97b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 54410a <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x96a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544106 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x966>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 544102 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x962>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 5440fe <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x95e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 5440fa <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x95a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVNE %RDI,%R10	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JE 543abc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x31c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 543abc <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x31c>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3–	0.05	0.02
▼Loop 2903 - csr_matvec.c:183-196 - exec–	0.01	0.01
○Loop 2904 - csr_matvec.c:194-195 - exec	0.04	0.02
▼Loop 2907 - csr_matvec.c:183-204 - exec–	0.00	0.00
▼Loop 2906 - csr_matvec.c:199-204 - exec–	0.00	0.00
○Loop 2908 - csr_matvec.c:202-203 - exec	0.00	0.00
○Loop 2899 - csr_matvec.c:191-191 - exec	0.00	0.00
○Loop 2905 - csr_matvec.c:191-191 - exec	0.00	0.00
▼Loop 2901 - csr_matvec.c:183-204 - exec–	0.00	0.00
▼Loop 2900 - csr_matvec.c:199-204 - exec–	0.00	0.00
○Loop 2902 - csr_matvec.c:202-203 - exec	0.00	0.00
▼Loop 2897 - csr_matvec.c:183-196 - exec–	0.00	0.00
○Loop 2898 - csr_matvec.c:194-195 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code