OV - exec - Function hypre_ParMatmul._omp

	Function: hypre_ParMatmul._omp_fn.3	Module: exec	Source: par_csr_matop.c:829-995 [...]	Coverage (incl. loops): 1.38% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 829 - 995

--------------------------------------------------------------------------------

829: #pragma omp parallel

830: #endif

831:    {

832:     HYPRE_Int *B_marker = NULL;

[...]

840:     ii = hypre_GetThreadNum();

841:     num_threads = hypre_NumActiveThreads();

842:     size = num_rows_diag_A/num_threads;

843:     rest = num_rows_diag_A - size*num_threads;

844:     if (ii < rest)

845:     {

846:        ns = ii*size+ii;

847:        ne = (ii+1)*size+ii+1;

848:     }

849:     else

850:     {

851:        ns = ii*size+rest;

852:        ne = (ii+1)*size+rest;

853:     }

854:     jj_count_diag = C_diag_i[ns];

855:     jj_count_offd = C_offd_i[ns];

856:     if (num_cols_diag_B || num_cols_offd_C)

857:     B_marker = hypre_CTAlloc(HYPRE_Int, num_cols_diag_B+num_cols_offd_C);

858:     for (i1 = 0; i1 < num_cols_diag_B+num_cols_offd_C; i1++)

859:       B_marker[i1] = -1;

[...]

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

875:       {

876:          B_marker[i1] = jj_count_diag;

877:          C_diag_data[jj_count_diag] = zero;

878:          C_diag_j[jj_count_diag] = i1;

879:          jj_count_diag++;

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

[...]

995:     hypre_TFree(B_marker);

0x50fb90 PUSH	%RBP

0x50fb91 MOV	%RSP,%RBP

0x50fb94 PUSH	%R15

0x50fb96 PUSH	%R14

0x50fb98 PUSH	%R13

0x50fb9a MOV	%RDI,%R13

0x50fb9d PUSH	%R12

0x50fb9f PUSH	%RBX

0x50fba0 SUB	$0x108,%RSP

0x50fba7 VMOVSD	0xf8(%RDI),%XMM0

0x50fbaf MOV	0xf0(%RDI),%RAX

0x50fbb6 MOV	0xe8(%RDI),%RDX

0x50fbbd MOV	0xe0(%RDI),%RCX

0x50fbc4 MOV	0xd8(%RDI),%RBX

0x50fbcb MOV	0xd0(%RDI),%RSI

0x50fbd2 MOV	0xc8(%RDI),%R8

0x50fbd9 MOV	0xc0(%RDI),%R9

0x50fbe0 MOV	0xb0(%RDI),%R10

0x50fbe7 VMOVSD	%XMM0,-0x50(%RBP)

0x50fbec MOV	%RAX,-0x110(%RBP)

0x50fbf3 MOV	%RDX,-0x60(%RBP)

0x50fbf7 MOV	%RCX,-0xe8(%RBP)

0x50fbfe MOV	%RBX,-0x68(%RBP)

0x50fc02 MOV	%RSI,-0x70(%RBP)

0x50fc06 MOV	%R8,-0xf0(%RBP)

0x50fc0d MOV	%R9,-0x78(%RBP)

0x50fc11 MOV	%R10,-0x80(%RBP)

0x50fc15 MOV	0xa0(%RDI),%R11

0x50fc1c MOV	0x98(%RDI),%R12

0x50fc23 MOV	0x78(%RDI),%R15

0x50fc27 MOV	0x70(%RDI),%RAX

0x50fc2b MOV	0x58(%RDI),%RSI

0x50fc2f MOV	0x50(%RDI),%R8

0x50fc33 MOV	0x40(%RDI),%R10

0x50fc37 MOV	0x48(%RDI),%R9

0x50fc3b MOV	0x80(%RDI),%R14

0x50fc42 MOV	0x60(%RDI),%RCX

0x50fc46 MOV	0x68(%RDI),%RDX

0x50fc4a MOV	%R11,-0x40(%RBP)

0x50fc4e MOV	%R12,-0x48(%RBP)

0x50fc52 MOV	0x38(%RDI),%R11

0x50fc56 MOV	0x28(%RDI),%R12

0x50fc5a MOV	%R15,-0xb8(%RBP)

0x50fc61 MOV	%RAX,-0x38(%RBP)

0x50fc65 MOV	0x20(%RDI),%R15

0x50fc69 MOV	0x18(%RDI),%RAX

0x50fc6d MOV	%RSI,-0x98(%RBP)

0x50fc74 MOV	%R8,-0x128(%RBP)

0x50fc7b MOV	%R10,-0x130(%RBP)

0x50fc82 MOV	%R11,-0x118(%RBP)

0x50fc89 MOV	%R9,-0xc0(%RBP)

0x50fc90 MOV	%R14,-0x88(%RBP)

0x50fc97 MOV	%RCX,-0xf8(%RBP)

0x50fc9e MOV	0x30(%RDI),%R14

0x50fca2 MOV	%R12,-0x100(%RBP)

0x50fca9 MOV	%RAX,-0x108(%RBP)

0x50fcb0 MOV	0x88(%RDI),%RBX

0x50fcb7 MOV	%RDX,-0x90(%RBP)

0x50fcbe MOV	%R15,-0xe0(%RBP)

0x50fcc5 MOV	0x10(%RDI),%RDX

0x50fcc9 MOV	0x8(%RDI),%RCX

0x50fccd MOV	(%RDI),%RDI

0x50fcd0 MOV	%RDX,-0xc8(%RBP)

0x50fcd7 MOV	%RCX,-0xb0(%RBP)

0x50fcde MOV	%RDI,-0xd0(%RBP)

0x50fce5 CALL	555090 <hypre_GetThreadNum>

0x50fcea MOV	%RAX,%R12

0x50fced CALL	555080 <hypre_NumActiveThreads>

0x50fcf2 MOV	%RAX,%RSI

0x50fcf5 MOV	%R14,%RAX

0x50fcf8 CQTO

0x50fcfa IDIV	%RSI

0x50fcfd MOV	-0x38(%RBP),%R11

0x50fd01 MOV	-0x48(%RBP),%R10

0x50fd05 VMOVSD	-0x50(%RBP),%XMM3

0x50fd0a MOV	%R12,%R8

0x50fd0d IMUL	%RAX,%R8

0x50fd11 ADD	%R8,%RAX

0x50fd14 CMP	%RDX,%R12

0x50fd17 JGE	51023c

0x50fd1d LEA	(%R12,%R8,1),%R9

0x50fd21 MOV	%R9,-0xa0(%RBP)

0x50fd28 LEA	0x1(%R12,%RAX,1),%R14

0x50fd2d MOV	0xb8(%R13),%RAX

0x50fd34 MOV	0x90(%R13),%R15

0x50fd3b MOV	0xa8(%R13),%RDI

0x50fd42 MOV	(%RAX),%RDX

0x50fd45 MOV	(%R15),%RCX

0x50fd48 MOV	(%RDI),%RSI

0x50fd4b MOV	%R11,%R8

0x50fd4e OR	%RDX,%R8

0x50fd51 MOV	(%RCX,%R9,8),%R12

0x50fd55 MOV	(%RSI,%R9,8),%R9

0x50fd59 JNE	5101bc

0x50fd5f XOR	%R8D,%R8D

0x50fd62 CMP	%R14,-0xa0(%RBP)

0x50fd69 JGE	5101a3

0x50fd6f CMPQ	$0,-0x110(%RBP)

0x50fd77 MOV	%R14,-0x120(%RBP)

0x50fd7e MOV	%R10,-0x38(%RBP)

0x50fd82 MOV	%R11,-0x58(%RBP)

0x50fd86 MOV	%R9,-0x50(%RBP)

0x50fd8a JNE	50fed5

    (2358) 0x50fd90 CMPQ	$0,-0x118(%RBP)

    (2358) 0x50fd98 MOV	%R12,%RDX

    (2358) 0x50fd9b JNE	50ff01

  (2356) 0x50fda1 MOV	-0x50(%RBP),%RSI

    (2358) 0x50fda5 MOV	-0xb0(%RBP),%R9

    (2358) 0x50fdac MOV	-0xa0(%RBP),%R11

    (2358) 0x50fdb3 MOV	(%R9,%R11,8),%R14

    (2358) 0x50fdb7 CMP	0x8(%R9,%R11,8),%R14

    (2358) 0x50fdbc JGE	50fea5

    (2358) 0x50fdc2 MOV	%R14,-0x48(%RBP)

    (2358) 0x50fdc6 MOV	-0x128(%RBP),%R11

    (2358) 0x50fdcd MOV	-0x130(%RBP),%R13

    (2358) 0x50fdd4 NOPL	(%RAX)

      (2362) 0x50fdd8 MOV	-0x48(%RBP),%R10

      (2362) 0x50fddc MOV	-0xc8(%RBP),%RDI

      (2362) 0x50fde3 MOV	-0xc0(%RBP),%R15

      (2362) 0x50fdea MOV	(%RDI,%R10,8),%RDI

      (2362) 0x50fdee MOV	-0xd0(%RBP),%RCX

      (2362) 0x50fdf5 LEA	0x8(,%RDI,8),%R9

      (2362) 0x50fdfd LEA	(%R15,%R9,1),%R14

      (2362) 0x50fe01 VMOVSD	(%RCX,%R10,8),%XMM7

      (2362) 0x50fe07 MOV	(%R15,%RDI,8),%RAX

      (2362) 0x50fe0b MOV	(%R14),%R10

      (2362) 0x50fe0e CMP	%R10,%RAX

      (2362) 0x50fe11 JGE	50fe76

      (2362) 0x50fe13 MOV	%R9,-0xa8(%RBP)

      (2362) 0x50fe1a NOPW	%CS:(%RAX,%RAX,1)

      (2362) 0x50fe25 NOPW	%CS:(%RAX,%RAX,1)

      (2362) 0x50fe30 NOPW	%CS:(%RAX,%RAX,1)

      (2362) 0x50fe3b NOPL	(%RAX,%RAX,1)

        (2364) 0x50fe40 MOV	(%R11,%RAX,8),%RCX

        (2364) 0x50fe44 VMULSD	(%R13,%RAX,8),%XMM7,%XMM8

        (2364) 0x50fe4b LEA	(%R8,%RCX,8),%R9

        (2364) 0x50fe4f MOV	(%R9),%R15

        (2364) 0x50fe52 CMP	%R12,%R15

        (2364) 0x50fe55 JL	510060

        (2364) 0x50fe5b LEA	(%RBX,%R15,8),%RCX

        (2364) 0x50fe5f VADDSD	(%RCX),%XMM8,%XMM9

        (2364) 0x50fe63 INC	%RAX

        (2364) 0x50fe66 VMOVSD	%XMM9,(%RCX)

        (2364) 0x50fe6a CMP	%R10,%RAX

        (2364) 0x50fe6d JL	50fe40

      (2362) 0x50fe6f MOV	-0xa8(%RBP),%R9

      (2362) 0x50fe76 CMPQ	$0,-0xb8(%RBP)

      (2362) 0x50fe7e JNE	510090

      (2362) 0x50fe84 INCQ	-0x48(%RBP)

      (2362) 0x50fe88 MOV	-0xb0(%RBP),%R14

      (2362) 0x50fe8f MOV	-0xa0(%RBP),%R15

      (2362) 0x50fe96 MOV	-0x48(%RBP),%RAX

      (2362) 0x50fe9a CMP	%RAX,0x8(%R14,%R15,8)

      (2362) 0x50fe9f JG	50fdd8

    (2358) 0x50fea5 INCQ	-0xa0(%RBP)

    (2358) 0x50feac MOV	-0xa0(%RBP),%R12

    (2358) 0x50feb3 CMP	%R12,-0x120(%RBP)

    (2358) 0x50feba JE	5101a3

    (2358) 0x50fec0 CMPQ	$0,-0x110(%RBP)

    (2358) 0x50fec8 MOV	%RSI,-0x50(%RBP)

    (2358) 0x50fecc MOV	%RDX,%R12

    (2358) 0x50fecf JE	50fd90

(2361) 0x50fed5 MOV	-0xa0(%RBP),%R11

(2361) 0x50fedc MOV	-0x38(%RBP),%R14

(2361) 0x50fee0 CMPQ	$0,-0x118(%RBP)

(2361) 0x50fee8 MOV	%R12,(%R8,%R11,8)

(2361) 0x50feec LEA	0x1(%R12),%RDX

(2361) 0x50fef1 VMOVSD	%XMM3,(%RBX,%R12,8)

(2361) 0x50fef7 MOV	%R11,(%R14,%R12,8)

(2361) 0x50fefb JE	50fda1

    (2358) 0x50ff01 MOV	-0xe0(%RBP),%RDI

    (2358) 0x50ff08 MOV	-0xa0(%RBP),%RSI

    (2358) 0x50ff0f MOV	(%RDI,%RSI,8),%R9

    (2358) 0x50ff13 CMP	0x8(%RDI,%RSI,8),%R9

    (2358) 0x50ff18 JGE	50fda1

    (2358) 0x50ff1e MOV	-0x50(%RBP),%R11

    (2358) 0x50ff22 MOV	%RBX,-0x48(%RBP)

    (2358) 0x50ff26 MOV	-0x58(%RBP),%R14

    (2358) 0x50ff2a MOV	%R11,%RSI

    (2358) 0x50ff2d NOPL	(%RAX)

      (2357) 0x50ff30 MOV	-0x100(%RBP),%RAX

      (2357) 0x50ff37 MOV	-0xe8(%RBP),%R10

      (2357) 0x50ff3e MOV	(%RAX,%R9,8),%RDI

      (2357) 0x50ff42 MOV	-0x108(%RBP),%RBX

      (2357) 0x50ff49 LEA	0x8(,%RDI,8),%R13

      (2357) 0x50ff51 MOV	(%R10,%RDI,8),%RAX

      (2357) 0x50ff55 ADD	%R13,%R10

      (2357) 0x50ff58 MOV	%R10,-0xa8(%RBP)

      (2357) 0x50ff5f MOV	(%R10),%R10

      (2357) 0x50ff62 VMOVSD	(%RBX,%R9,8),%XMM2

      (2357) 0x50ff68 CMP	%R10,%RAX

      (2357) 0x50ff6b JGE	50ffc4

      (2357) 0x50ff6d MOV	%RDX,-0xd8(%RBP)

      (2357) 0x50ff74 NOPW	%CS:(%RAX,%RAX,1)

      (2357) 0x50ff7f NOP

        (2360) 0x50ff80 MOV	-0x60(%RBP),%R15

        (2360) 0x50ff84 MOV	(%R15,%RAX,8),%RCX

        (2360) 0x50ff88 LEA	(%R14,%RCX,1),%RDX

        (2360) 0x50ff8c LEA	(%R8,%RDX,8),%RBX

        (2360) 0x50ff90 MOV	(%RBX),%R15

        (2360) 0x50ff93 MOV	-0x68(%RBP),%RDX

        (2360) 0x50ff97 VMULSD	(%RDX,%RAX,8),%XMM2,%XMM1

        (2360) 0x50ff9c CMP	%R11,%R15

        (2360) 0x50ff9f JL	510170

        (2360) 0x50ffa5 MOV	-0x40(%RBP),%RCX

        (2360) 0x50ffa9 INC	%RAX

        (2360) 0x50ffac LEA	(%RCX,%R15,8),%RBX

        (2360) 0x50ffb0 VADDSD	(%RBX),%XMM1,%XMM4

        (2360) 0x50ffb4 VMOVSD	%XMM4,(%RBX)

        (2360) 0x50ffb8 CMP	%R10,%RAX

        (2360) 0x50ffbb JL	50ff80

      (2357) 0x50ffbd MOV	-0xd8(%RBP),%RDX

      (2357) 0x50ffc4 MOV	-0xf0(%RBP),%RCX

      (2357) 0x50ffcb MOV	(%RCX,%RDI,8),%RAX

      (2357) 0x50ffcf LEA	(%RCX,%R13,1),%RDI

      (2357) 0x50ffd3 MOV	(%RDI),%R10

      (2357) 0x50ffd6 MOV	%RDI,%R15

      (2357) 0x50ffd9 CMP	%R10,%RAX

      (2357) 0x50ffdc JGE	51003a

      (2357) 0x50ffde NOPW	%CS:(%RAX,%RAX,1)

      (2357) 0x50ffe9 NOPW	%CS:(%RAX,%RAX,1)

      (2357) 0x50fff4 NOPW	%CS:(%RAX,%RAX,1)

      (2357) 0x50ffff NOP

        (2359) 0x510000 MOV	-0x70(%RBP),%R13

        (2359) 0x510004 MOV	-0x78(%RBP),%RBX

        (2359) 0x510008 MOV	(%R13,%RAX,8),%RCX

        (2359) 0x51000d VMULSD	(%RBX,%RAX,8),%XMM2,%XMM5

        (2359) 0x510012 LEA	(%R8,%RCX,8),%RDI

        (2359) 0x510016 MOV	(%RDI),%R13

        (2359) 0x510019 CMP	%R12,%R13

        (2359) 0x51001c JL	510140

        (2359) 0x510022 MOV	-0x48(%RBP),%RCX

        (2359) 0x510026 INC	%RAX

        (2359) 0x510029 LEA	(%RCX,%R13,8),%RDI

        (2359) 0x51002d VADDSD	(%RDI),%XMM5,%XMM6

        (2359) 0x510031 VMOVSD	%XMM6,(%RDI)

        (2359) 0x510035 CMP	%R10,%RAX

        (2359) 0x510038 JL	510000

      (2357) 0x51003a MOV	-0xe0(%RBP),%RAX

      (2357) 0x510041 MOV	-0xa0(%RBP),%R15

      (2357) 0x510048 INC	%R9

      (2357) 0x51004b CMP	%R9,0x8(%RAX,%R15,8)

      (2357) 0x510050 JG	50ff30

    (2358) 0x510056 MOV	-0x48(%RBP),%RBX

    (2358) 0x51005a JMP	50fda5

0x51005f NOP

        (2364) 0x510060 MOV	-0x38(%RBP),%R10

        (2364) 0x510064 MOV	%RDX,(%R9)

        (2364) 0x510067 VMOVSD	%XMM8,(%RBX,%RDX,8)

        (2364) 0x51006c MOV	%RCX,(%R10,%RDX,8)

        (2364) 0x510070 INC	%RAX

        (2364) 0x510073 INC	%RDX

        (2364) 0x510076 MOV	(%R14),%R10

        (2364) 0x510079 CMP	%RAX,%R10

        (2364) 0x51007c JG	50fe40

      (2362) 0x510082 JMP	50fe6f

0x510087 NOPW	(%RAX,%RAX,1)

      (2362) 0x510090 MOV	-0xf8(%RBP),%R14

      (2362) 0x510097 MOV	(%R14,%RDI,8),%RAX

      (2362) 0x51009b LEA	(%R14,%R9,1),%R14

      (2362) 0x51009f MOV	(%R14),%R10

      (2362) 0x5100a2 CMP	%R10,%RAX

      (2362) 0x5100a5 JGE	50fe84

      (2362) 0x5100ab NOPL	(%RAX,%RAX,1)

        (2363) 0x5100b0 MOV	-0x90(%RBP),%RDI

        (2363) 0x5100b7 MOV	-0x88(%RBP),%RCX

        (2363) 0x5100be MOV	(%RDI,%RAX,8),%R15

        (2363) 0x5100c2 MOV	-0x58(%RBP),%R9

        (2363) 0x5100c6 MOV	(%RCX,%R15,8),%RCX

        (2363) 0x5100ca MOV	-0x98(%RBP),%R15

        (2363) 0x5100d1 ADD	%RCX,%R9

        (2363) 0x5100d4 LEA	(%R8,%R9,8),%RDI

        (2363) 0x5100d8 VMULSD	(%R15,%RAX,8),%XMM7,%XMM10

        (2363) 0x5100de MOV	(%RDI),%R9

        (2363) 0x5100e1 MOV	-0x50(%RBP),%R15

        (2363) 0x5100e5 CMP	%R15,%R9

        (2363) 0x5100e8 JL	510110

        (2363) 0x5100ea MOV	-0x40(%RBP),%RCX

        (2363) 0x5100ee INC	%RAX

        (2363) 0x5100f1 LEA	(%RCX,%R9,8),%RDI

        (2363) 0x5100f5 VADDSD	(%RDI),%XMM10,%XMM11

        (2363) 0x5100f9 VMOVSD	%XMM11,(%RDI)

        (2363) 0x5100fd CMP	%R10,%RAX

        (2363) 0x510100 JL	5100b0

      (2362) 0x510102 JMP	50fe84

0x510107 NOPW	(%RAX,%RAX,1)

        (2363) 0x510110 MOV	-0x40(%RBP),%R10

        (2363) 0x510114 MOV	-0x80(%RBP),%R9

        (2363) 0x510118 MOV	%RSI,(%RDI)

        (2363) 0x51011b VMOVSD	%XMM10,(%R10,%RSI,8)

        (2363) 0x510121 MOV	%RCX,(%R9,%RSI,8)

        (2363) 0x510125 INC	%RAX

        (2363) 0x510128 INC	%RSI

        (2363) 0x51012b MOV	(%R14),%R10

        (2363) 0x51012e CMP	%RAX,%R10

        (2363) 0x510131 JG	5100b0

      (2362) 0x510137 JMP	50fe84

0x51013c NOPL	(%RAX)

        (2359) 0x510140 MOV	-0x48(%RBP),%R10

        (2359) 0x510144 MOV	-0x38(%RBP),%R13

        (2359) 0x510148 MOV	%RDX,(%RDI)

        (2359) 0x51014b VMOVSD	%XMM5,(%R10,%RDX,8)

        (2359) 0x510151 MOV	%RCX,(%R13,%RDX,8)

        (2359) 0x510156 INC	%RAX

        (2359) 0x510159 INC	%RDX

        (2359) 0x51015c MOV	(%R15),%R10

        (2359) 0x51015f CMP	%RAX,%R10

        (2359) 0x510162 JG	510000

      (2357) 0x510168 JMP	51003a

0x51016d NOPL	(%RAX)

        (2360) 0x510170 MOV	-0x40(%RBP),%R10

        (2360) 0x510174 MOV	-0x80(%RBP),%R15

        (2360) 0x510178 MOV	%RSI,(%RBX)

        (2360) 0x51017b VMOVSD	%XMM1,(%R10,%RSI,8)

        (2360) 0x510181 MOV	%RCX,(%R15,%RSI,8)

        (2360) 0x510185 MOV	-0xa8(%RBP),%RDX

        (2360) 0x51018c INC	%RAX

        (2360) 0x51018f MOV	(%RDX),%R10

        (2360) 0x510192 INC	%RSI

        (2360) 0x510195 CMP	%RAX,%R10

        (2360) 0x510198 JG	50ff80

      (2357) 0x51019e JMP	50ffbd

0x5101a3 ADD	$0x108,%RSP

0x5101aa POP	%RBX

0x5101ab POP	%R12

0x5101ad POP	%R13

0x5101af POP	%R14

0x5101b1 POP	%R15

0x5101b3 MOV	%R8,%RDI

0x5101b6 POP	%RBP

0x5101b7 JMP	552440

0x5101bc LEA	(%R11,%RDX,1),%RDI

0x5101c0 MOV	$0x8,%ESI

0x5101c5 MOV	%R9,-0x58(%RBP)

0x5101c9 MOV	%R10,-0x50(%RBP)

0x5101cd MOV	%R11,-0x38(%RBP)

0x5101d1 VMOVSD	%XMM3,-0x48(%RBP)

0x5101d6 CALL	5523b0 <hypre_CAlloc>

0x5101db MOV	0xb8(%R13),%R13

0x5101e2 MOV	-0x38(%RBP),%R11

0x5101e6 MOV	(%R13),%R10

0x5101ea VMOVSD	-0x48(%RBP),%XMM3

0x5101ef ADD	%R11,%R10

0x5101f2 TEST	%R10,%R10

0x5101f5 MOV	-0x58(%RBP),%R9

0x5101f9 MOV	-0x50(%RBP),%R10

0x5101fd MOV	%RAX,%R8

0x510200 JLE	50fd62

0x510206 XOR	%R15D,%R15D

0x510209 NOPW	%CS:(%RAX,%RAX,1)

0x510214 NOPW	%CS:(%RAX,%RAX,1)

0x51021f NOP

(2365) 0x510220 MOVQ	$-0x1,(%R8,%R15,8)

(2365) 0x510228 INC	%R15

(2365) 0x51022b MOV	(%R13),%RCX

(2365) 0x51022f ADD	%R11,%RCX

(2365) 0x510232 CMP	%R15,%RCX

(2365) 0x510235 JG	510220

0x510237 JMP	50fd62

0x51023c LEA	(%RDX,%R8,1),%R9

0x510240 MOV	%R9,-0xa0(%RBP)

0x510247 LEA	(%RDX,%RAX,1),%R14

0x51024b JMP	50fd2d

Coverage (%)	Name	Source Location	Module
○97.50	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.50	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	par_csr_matop.c:829-995
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:829-832,840-859,865,874-879,886-891,897-899,907-928,937-940,946-948,956-972,980-989,995.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 2.83 cycles (8.82x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 25.00 to 5.00 cycles (5.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CAlloc: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:857
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:840
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:841

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:842

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:842

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 384 bytes. The binary function is storing 296 bytes.

General properties

nb instructions	143
nb uops	150
loop length	688
used x86 registers	16
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	30

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.00 cycles
front end	25.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	5.00	18.00	18.00	23.00	4.00	4.00	23.00	23.00	23.00	4.00	18.00
cycles	4.00	7.00	18.00	18.00	23.00	4.00	4.00	23.00	23.00	23.00	4.00	18.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	25.00
Dispatch	23.00
DIV/SQRT	10.00
Overall L1	25.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

8% of peak load performance is reached (15.36 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (11.84 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 25.00 to 23.00 cycles (1.09x speedup).

ASM code

In the binary file, the address of the function is: 50fb90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x108,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
VMOVSD 0xf8(%RDI),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xf0(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xe8(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xe0(%RDI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xd8(%RDI),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xd0(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xc8(%RDI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xc0(%RDI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb0(%RDI),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM0,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa0(%RDI),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x98(%RDI),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RDI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x58(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x50(%RDI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x40(%RDI),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x48(%RDI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x80(%RDI),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x60(%RDI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x68(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RDI),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RDI),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RDI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x128(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x118(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RDI),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R12,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x88(%RDI),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RDX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 555090 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 555080 <hypre_NumActiveThreads>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RSI	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x50(%RBP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R12,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RDX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 51023c <hypre_ParMatmul._omp_fn.3+0x6ac>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R12,%R8,1),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%R12,%RAX,1),%R14	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0xb8(%R13),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x90(%R13),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xa8(%R13),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R15),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV (%RCX,%R9,8),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RSI,%R9,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 5101bc <hypre_ParMatmul._omp_fn.3+0x62c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R14,-0xa0(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 5101a3 <hypre_ParMatmul._omp_fn.3+0x613>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPQ $0,-0x110(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %R14,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JNE 50fed5 <hypre_ParMatmul._omp_fn.3+0x345>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x108,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
MOV %R8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 552440 <hypre_Free>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
LEA (%R11,%RDX,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM3,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xb8(%R13),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R13),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x48(%RBP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R11,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST %R10,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV -0x58(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 50fd62 <hypre_ParMatmul._omp_fn.3+0x1d2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 50fd62 <hypre_ParMatmul._omp_fn.3+0x1d2>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
LEA (%RDX,%R8,1),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%RAX,1),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 50fd2d <hypre_ParMatmul._omp_fn.3+0x19d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	par_csr_matop.c:829-995
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 2.83 cycles (8.82x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CAlloc: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:857
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:840
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:841

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:842

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:842

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 384 bytes. The binary function is storing 296 bytes.

General properties

nb instructions	143
nb uops	150
loop length	688
used x86 registers	16
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	30

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.00 cycles
front end	25.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	5.00	18.00	18.00	23.00	4.00	4.00	23.00	23.00	23.00	4.00	18.00
cycles	4.00	7.00	18.00	18.00	23.00	4.00	4.00	23.00	23.00	23.00	4.00	18.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	25.00
Dispatch	23.00
DIV/SQRT	10.00
Overall L1	25.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

8% of peak load performance is reached (15.36 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (11.84 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 50fb90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x108,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
VMOVSD 0xf8(%RDI),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xf0(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xe8(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xe0(%RDI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xd8(%RDI),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xd0(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xc8(%RDI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xc0(%RDI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb0(%RDI),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM0,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa0(%RDI),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x98(%RDI),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RDI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x58(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x50(%RDI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x40(%RDI),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x48(%RDI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x80(%RDI),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x60(%RDI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x68(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RDI),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RDI),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RDI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x128(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x118(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RDI),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R12,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x88(%RDI),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RDX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 555090 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 555080 <hypre_NumActiveThreads>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RSI	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x50(%RBP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R12,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RDX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 51023c <hypre_ParMatmul._omp_fn.3+0x6ac>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (%R12,%R8,1),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%R12,%RAX,1),%R14	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0xb8(%R13),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x90(%R13),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xa8(%R13),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R15),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV (%RCX,%R9,8),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RSI,%R9,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 5101bc <hypre_ParMatmul._omp_fn.3+0x62c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R14,-0xa0(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JGE 5101a3 <hypre_ParMatmul._omp_fn.3+0x613>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPQ $0,-0x110(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %R14,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JNE 50fed5 <hypre_ParMatmul._omp_fn.3+0x345>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x108,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
MOV %R8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 552440 <hypre_Free>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
LEA (%R11,%RDX,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM3,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xb8(%R13),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R13),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x48(%RBP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R11,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
TEST %R10,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV -0x58(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 50fd62 <hypre_ParMatmul._omp_fn.3+0x1d2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 50fd62 <hypre_ParMatmul._omp_fn.3+0x1d2>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
LEA (%RDX,%R8,1),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%RAX,1),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 50fd2d <hypre_ParMatmul._omp_fn.3+0x19d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Name	Coverage (%)	Time (s)
▼hypre_ParMatmul._omp_fn.3–	1.38	0.60
○Loop 2365 - par_csr_matop.c:858-859 - exec	0.00	0.00
▼Loop 2361 - par_csr_matop.c:865-989 - exec–	0.00	0.00
▼Loop 2356 - par_csr_matop.c:865-989 - exec–	0.00	0.00
▼Loop 2358 - par_csr_matop.c:865-989 - exec–	0.02	0.01
▼Loop 2362 - par_csr_matop.c:937-989 - exec–	0.49	0.18
○Loop 2364 - par_csr_matop.c:946-965 - exec	0.86	0.32
○Loop 2363 - par_csr_matop.c:970-989 - exec	0.00	0.01
▼Loop 2357 - par_csr_matop.c:888-928 - exec–	0.00	0.01
○Loop 2360 - par_csr_matop.c:897-915 - exec	0.00	0.01
○Loop 2359 - par_csr_matop.c:917-928 - exec	0.00	0.00

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