OV - exec - Function hypre_BoomerAMGCreateS._omp

	Function: hypre_BoomerAMGCreateS._omp_fn.1	Module: exec	Source: par_strength.c:246-513 [...]	Coverage (incl. loops): 1.59% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 246 - 513

--------------------------------------------------------------------------------

246: #pragma omp parallel private(i,diag,row_scale,row_sum,jA,jS)

247: #endif

248:    {

249:    HYPRE_Int start, stop;

250:    hypre_GetSimpleThreadPartition(&start, &stop, num_variables);

251:    HYPRE_Int jS_diag = 0, jS_offd = 0;

252:

253:    for (i = start; i < stop; i++)

254:    {

255:       S_diag_i[i] = jS_diag;

256:       if (num_cols_offd)

257:       {

258:          S_offd_i[i] = jS_offd;

259:       }

260:

261:       diag = A_diag_data[A_diag_i[i]];

262:

263:       /* compute scaling factor and row sum */

264:       row_scale = 0.0;

265:       row_sum = diag;

266:       if (num_functions > 1)

267:       {

268:          if (diag < 0)

269:          {

270:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

271:             {

272:                if (dof_func[i] == dof_func[A_diag_j[jA]])

273:                {

274:                   row_scale = hypre_max(row_scale, A_diag_data[jA]);

275:                   row_sum += A_diag_data[jA];

276:                }

277:             }

278:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

279:             {

280:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

281:                {

282:                   row_scale = hypre_max(row_scale, A_offd_data[jA]);

283:                   row_sum += A_offd_data[jA];

[...]

289:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

290:             {

291:                if (dof_func[i] == dof_func[A_diag_j[jA]])

292:                {

293:                   row_scale = hypre_min(row_scale, A_diag_data[jA]);

294:                   row_sum += A_diag_data[jA];

295:                }

296:             }

297:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

298:             {

299:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

300:                {

301:                   row_scale = hypre_min(row_scale, A_offd_data[jA]);

302:                   row_sum += A_offd_data[jA];

[...]

309:          if (diag < 0)

310:          {

311:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

312:             {

313:                row_scale = hypre_max(row_scale, A_diag_data[jA]);

314:                row_sum += A_diag_data[jA];

315:             }

316:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

317:             {

318:                row_scale = hypre_max(row_scale, A_offd_data[jA]);

319:                row_sum += A_offd_data[jA];

320:             }

321:          }

322:          else

323:          {

324:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

325:             {

326:                row_scale = hypre_min(row_scale, A_diag_data[jA]);

327:                row_sum += A_diag_data[jA];

328:             }

329:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

330:             {

331:                row_scale = hypre_min(row_scale, A_offd_data[jA]);

332:                row_sum += A_offd_data[jA];

333:             }

334:          } /* diag >= 0*/

335:       } /* num_functions <= 1 */

336:

337:       jS_diag += A_diag_i[i + 1] - A_diag_i[i] - 1;

338:       jS_offd += A_offd_i[i + 1] - A_offd_i[i];

339:

340:       /* compute row entries of S */

341:       S_temp_diag_j[A_diag_i[i]] = -1;

342:       if ((fabs(row_sum) > fabs(diag)*max_row_sum) && (max_row_sum < 1.0))

343:       {

344:          /* make all dependencies weak */

345:          for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

346:          {

347:             S_temp_diag_j[jA] = -1;

348:          }

349:          jS_diag -= A_diag_i[i + 1] - (A_diag_i[i] + 1);

350:

351:          for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

352:          {

353:             S_temp_offd_j[jA] = -1;

354:          }

355:          jS_offd -= A_offd_i[i + 1] - A_offd_i[i];

[...]

363:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

364:                {

365:                   if (A_diag_data[jA] <= strength_threshold * row_scale

366:                       || dof_func[i] != dof_func[A_diag_j[jA]])

367:                   {

368:                      S_temp_diag_j[jA] = -1;

369:                      --jS_diag;

[...]

376:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

377:                {

378:                   if (A_offd_data[jA] <= strength_threshold * row_scale

379:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

380:                   {

381:                      S_temp_offd_j[jA] = -1;

382:                      --jS_offd;

[...]

392:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

393:                {

394:                   if (A_diag_data[jA] >= strength_threshold * row_scale

395:                       || dof_func[i] != dof_func[A_diag_j[jA]])

396:                   {

397:                      S_temp_diag_j[jA] = -1;

398:                      --jS_diag;

[...]

405:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

406:                {

407:                   if (A_offd_data[jA] >= strength_threshold * row_scale

408:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

409:                   {

410:                      S_temp_offd_j[jA] = -1;

411:                      --jS_offd;

[...]

424:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

425:                {

426:                   if (A_diag_data[jA] <= strength_threshold * row_scale)

427:                   {

428:                      S_temp_diag_j[jA] = -1;

429:                      --jS_diag;

430:                   }

431:                   else

432:                   {

433:                      S_temp_diag_j[jA] = A_diag_j[jA];

434:                   }

435:                }

436:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

437:                {

438:                   if (A_offd_data[jA] <= strength_threshold * row_scale)

439:                   {

440:                      S_temp_offd_j[jA] = -1;

441:                      --jS_offd;

442:                   }

443:                   else

444:                   {

445:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

451:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

452:                {

453:                   if (A_diag_data[jA] >= strength_threshold * row_scale)

454:                   {

455:                      S_temp_diag_j[jA] = -1;

456:                      --jS_diag;

457:                   }

458:                   else

459:                   {

460:                      S_temp_diag_j[jA] = A_diag_j[jA];

461:                   }

462:                }

463:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

464:                {

465:                   if (A_offd_data[jA] >= strength_threshold * row_scale)

466:                   {

467:                      S_temp_offd_j[jA] = -1;

468:                      --jS_offd;

469:                   }

470:                   else

471:                   {

472:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

480:    hypre_prefix_sum_pair(&jS_diag, S_diag_i + num_variables, &jS_offd, S_offd_i + num_variables, prefix_sum_workspace);

[...]

492:    for (i = start; i < stop; i++)

493:    {

494:       S_diag_i[i] += jS_diag;

495:       S_offd_i[i] += jS_offd;

496:

497:       jS = S_diag_i[i];

498:       for (jA = A_diag_i[i]; jA < A_diag_i[i+1]; jA++)

499:       {

500:          if (S_temp_diag_j[jA] > -1)

501:          {

502:             S_diag_j[jS]    = S_temp_diag_j[jA];

503:             jS++;

504:          }

505:       }

506:

507:       jS = S_offd_i[i];

508:       for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

509:       {

510:          if (S_temp_offd_j[jA] > -1)

511:          {

512:             S_offd_j[jS]    = S_temp_offd_j[jA];

513:             jS++;

0x4d2ed0 PUSH	%RBP

0x4d2ed1 MOV	%RSP,%RBP

0x4d2ed4 PUSH	%R15

0x4d2ed6 PUSH	%R14

0x4d2ed8 PUSH	%R13

0x4d2eda PUSH	%R12

0x4d2edc PUSH	%RBX

0x4d2edd SUB	$0xd8,%RSP

0x4d2ee4 MOV	0x68(%RDI),%R8

0x4d2ee8 MOV	0x88(%RDI),%RAX

0x4d2eef MOV	0x80(%RDI),%RDX

0x4d2ef6 MOV	0x78(%RDI),%RCX

0x4d2efa MOV	0x70(%RDI),%RSI

0x4d2efe MOV	0x60(%RDI),%R9

0x4d2f02 MOV	0x58(%RDI),%R10

0x4d2f06 MOV	%R8,-0xf8(%RBP)

0x4d2f0d MOV	%RAX,-0xe8(%RBP)

0x4d2f14 MOV	%RDX,-0x78(%RBP)

0x4d2f18 MOV	%RCX,-0xf0(%RBP)

0x4d2f1f MOV	%RSI,-0xb8(%RBP)

0x4d2f26 MOV	0x50(%RDI),%RCX

0x4d2f2a MOV	%R9,-0x90(%RBP)

0x4d2f31 MOV	%R10,-0x98(%RBP)

0x4d2f38 MOV	0x98(%RDI),%R12

0x4d2f3f MOV	0x90(%RDI),%RBX

0x4d2f46 MOV	0x48(%RDI),%R13

0x4d2f4a MOV	0x40(%RDI),%R14

0x4d2f4e MOV	0x30(%RDI),%R15

0x4d2f52 MOV	0x20(%RDI),%RDX

0x4d2f56 MOV	0x10(%RDI),%RSI

0x4d2f5a MOV	0x38(%RDI),%R11

0x4d2f5e VMOVSD	0x8(%RDI),%XMM5

0x4d2f63 VMOVSD	(%RDI),%XMM4

0x4d2f67 MOV	0x28(%RDI),%RAX

0x4d2f6b MOV	%R15,-0xc8(%RBP)

0x4d2f72 MOV	%RDX,-0xd0(%RBP)

0x4d2f79 MOV	%RSI,-0xa0(%RBP)

0x4d2f80 MOV	0x18(%RDI),%R15

0x4d2f84 LEA	-0x48(%RBP),%RSI

0x4d2f88 LEA	-0x50(%RBP),%RDI

0x4d2f8c MOV	%RCX,%RDX

0x4d2f8f MOV	%R11,-0x80(%RBP)

0x4d2f93 VMOVSD	%XMM5,-0x68(%RBP)

0x4d2f98 VMOVSD	%XMM4,-0x60(%RBP)

0x4d2f9d MOV	%RAX,-0x70(%RBP)

0x4d2fa1 MOV	%RCX,-0x58(%RBP)

0x4d2fa5 CALL	5550a0 <hypre_GetSimpleThreadPartition>

0x4d2faa MOV	-0x48(%RBP),%R8

0x4d2fae MOV	-0x50(%RBP),%RDI

0x4d2fb2 MOV	%R8,-0xa8(%RBP)

0x4d2fb9 CMP	%R8,%RDI

0x4d2fbc MOVQ	$0,-0x40(%RBP)

0x4d2fc4 MOVQ	$0,-0x38(%RBP)

0x4d2fcc MOV	-0x58(%RBP),%RSI

0x4d2fd0 VMOVSD	-0x60(%RBP),%XMM4

0x4d2fd5 VMOVSD	-0x68(%RBP),%XMM5

0x4d2fda MOV	-0x70(%RBP),%R8

0x4d2fde MOV	-0x80(%RBP),%R11

0x4d2fe2 JGE	4d3688

0x4d2fe8 VMOVSD	0x87728(%RIP),%XMM0

0x4d2ff0 MOV	-0xc8(%RBP),%RCX

0x4d2ff7 VCOMISD	%XMM5,%XMM0

0x4d2ffb LEA	(,%RDI,8),%R10

0x4d3003 LEA	(%RCX,%R10,1),%RAX

0x4d3007 MOV	-0xd0(%RBP),%RDX

0x4d300e SETAB	-0xb9(%RBP)

0x4d3015 MOV	%RAX,-0x70(%RBP)

0x4d3019 ADD	$0x8,%R10

0x4d301d MOV	%RSI,-0x100(%RBP)

0x4d3024 ADD	%R10,%RCX

0x4d3027 VMOVQ	0x87e21(%RIP),%XMM3

0x4d302f ADD	%RDX,%R10

0x4d3032 MOV	%R10,-0x58(%RBP)

0x4d3036 MOV	%R12,-0x68(%RBP)

0x4d303a XOR	%R10D,%R10D

0x4d303d MOV	%RBX,%R12

0x4d3040 XOR	%EDX,%EDX

0x4d3042 VXORPD	%XMM6,%XMM6,%XMM6

0x4d3046 MOV	%RDI,%RBX

0x4d3049 NOPL	(%RAX)

(1762) 0x4d3050 MOV	-0x90(%RBP),%R9

(1762) 0x4d3057 CMPQ	$0,-0x98(%RBP)

(1762) 0x4d305f MOV	%RDX,(%R9,%RBX,8)

(1762) 0x4d3063 JE	4d3070

(1762) 0x4d3065 MOV	-0xb8(%RBP),%RSI

(1762) 0x4d306c MOV	%R10,(%RSI,%RBX,8)

(1762) 0x4d3070 MOV	-0x58(%RBP),%R9

(1762) 0x4d3074 CMPQ	$0x1,-0xa0(%RBP)

(1762) 0x4d307c MOV	-0x8(%R9),%RAX

(1762) 0x4d3080 MOV	(%R9),%R9

(1762) 0x4d3083 MOV	%RAX,-0x80(%RBP)

(1762) 0x4d3087 MOV	%R9,-0x60(%RBP)

(1762) 0x4d308b VMOVSD	(%R8,%RAX,8),%XMM7

(1762) 0x4d3091 LEA	(,%RAX,8),%RDI

(1762) 0x4d3099 LEA	0x1(%RAX),%RSI

(1762) 0x4d309d JLE	4d37d0

(1762) 0x4d30a3 VCOMISD	%XMM7,%XMM6

(1762) 0x4d30a7 JA	4d3ba0

(1762) 0x4d30ad CMP	%R9,%RSI

(1762) 0x4d30b0 JGE	4d4599

(1762) 0x4d30b6 MOV	%R9,%RAX

(1762) 0x4d30b9 SUB	%RSI,%RAX

(1762) 0x4d30bc MOV	(%R15,%RBX,8),%RDI

(1762) 0x4d30c0 VMOVAPD	%XMM7,%XMM1

(1762) 0x4d30c4 VXORPD	%XMM0,%XMM0,%XMM0

(1762) 0x4d30c8 AND	$0x7,%EAX

(1762) 0x4d30cb JE	4d31c7

(1762) 0x4d30d1 CMP	$0x1,%RAX

(1762) 0x4d30d5 JE	4d319d

(1762) 0x4d30db CMP	$0x2,%RAX

(1762) 0x4d30df JE	4d3180

(1762) 0x4d30e5 CMP	$0x3,%RAX

(1762) 0x4d30e9 JE	4d3163

(1762) 0x4d30eb CMP	$0x4,%RAX

(1762) 0x4d30ef JE	4d3146

(1762) 0x4d30f1 CMP	$0x5,%RAX

(1762) 0x4d30f5 JE	4d3129

(1762) 0x4d30f7 CMP	$0x6,%RAX

(1762) 0x4d30fb JE	4d3118

(1762) 0x4d30fd MOV	(%R14,%RSI,8),%R9

(1762) 0x4d3101 CMP	(%R15,%R9,8),%RDI

(1762) 0x4d3105 JNE	4d3115

(1762) 0x4d3107 VMOVSD	(%R8,%RSI,8),%XMM2

(1762) 0x4d310d VMINSD	%XMM2,%XMM0,%XMM0

(1762) 0x4d3111 VADDSD	%XMM2,%XMM7,%XMM1

(1762) 0x4d3115 INC	%RSI

(1762) 0x4d3118 MOV	(%R14,%RSI,8),%RAX

(1762) 0x4d311c CMP	(%R15,%RAX,8),%RDI

(1762) 0x4d3120 JE	4d4584

(1762) 0x4d3126 INC	%RSI

(1762) 0x4d3129 MOV	(%R14,%RSI,8),%R9

(1762) 0x4d312d CMP	(%R15,%R9,8),%RDI

(1762) 0x4d3131 JNE	4d3143

(1762) 0x4d3133 VMOVSD	(%R8,%RSI,8),%XMM9

(1762) 0x4d3139 VMINSD	%XMM9,%XMM0,%XMM0

(1762) 0x4d313e VADDSD	%XMM9,%XMM1,%XMM1

(1762) 0x4d3143 INC	%RSI

(1762) 0x4d3146 MOV	(%R14,%RSI,8),%RAX

(1762) 0x4d314a CMP	(%R15,%RAX,8),%RDI

(1762) 0x4d314e JNE	4d3160

(1762) 0x4d3150 VMOVSD	(%R8,%RSI,8),%XMM10

(1762) 0x4d3156 VMINSD	%XMM10,%XMM0,%XMM0

(1762) 0x4d315b VADDSD	%XMM10,%XMM1,%XMM1

(1762) 0x4d3160 INC	%RSI

(1762) 0x4d3163 MOV	(%R14,%RSI,8),%R9

(1762) 0x4d3167 CMP	(%R15,%R9,8),%RDI

(1762) 0x4d316b JNE	4d317d

(1762) 0x4d316d VMOVSD	(%R8,%RSI,8),%XMM11

(1762) 0x4d3173 VMINSD	%XMM11,%XMM0,%XMM0

(1762) 0x4d3178 VADDSD	%XMM11,%XMM1,%XMM1

(1762) 0x4d317d INC	%RSI

(1762) 0x4d3180 MOV	(%R14,%RSI,8),%RAX

(1762) 0x4d3184 CMP	(%R15,%RAX,8),%RDI

(1762) 0x4d3188 JNE	4d319a

(1762) 0x4d318a VMOVSD	(%R8,%RSI,8),%XMM12

(1762) 0x4d3190 VMINSD	%XMM12,%XMM0,%XMM0

(1762) 0x4d3195 VADDSD	%XMM12,%XMM1,%XMM1

(1762) 0x4d319a INC	%RSI

(1762) 0x4d319d MOV	(%R14,%RSI,8),%R9

(1762) 0x4d31a1 CMP	(%R15,%R9,8),%RDI

(1762) 0x4d31a5 JNE	4d31b7

(1762) 0x4d31a7 VMOVSD	(%R8,%RSI,8),%XMM15

(1762) 0x4d31ad VMINSD	%XMM15,%XMM0,%XMM0

(1762) 0x4d31b2 VADDSD	%XMM15,%XMM1,%XMM1

(1762) 0x4d31b7 MOV	-0x60(%RBP),%RAX

(1762) 0x4d31bb INC	%RSI

(1762) 0x4d31be CMP	%RAX,%RSI

(1762) 0x4d31c1 JE	4d32c2

  (1782) 0x4d31c7 MOV	(%R14,%RSI,8),%R9

  (1782) 0x4d31cb CMP	(%R15,%R9,8),%RDI

  (1782) 0x4d31cf JNE	4d31e1

  (1782) 0x4d31d1 VMOVSD	(%R8,%RSI,8),%XMM14

  (1782) 0x4d31d7 VMINSD	%XMM14,%XMM0,%XMM0

  (1782) 0x4d31dc VADDSD	%XMM14,%XMM1,%XMM1

  (1782) 0x4d31e1 LEA	0x1(%RSI),%RAX

  (1782) 0x4d31e5 MOV	(%R14,%RAX,8),%RSI

  (1782) 0x4d31e9 CMP	(%R15,%RSI,8),%RDI

  (1782) 0x4d31ed JNE	4d31ff

  (1782) 0x4d31ef VMOVSD	(%R8,%RAX,8),%XMM13

  (1782) 0x4d31f5 VMINSD	%XMM13,%XMM0,%XMM0

  (1782) 0x4d31fa VADDSD	%XMM13,%XMM1,%XMM1

  (1782) 0x4d31ff LEA	0x1(%RAX),%RSI

  (1782) 0x4d3203 MOV	(%R14,%RSI,8),%R9

  (1782) 0x4d3207 CMP	(%R15,%R9,8),%RDI

  (1782) 0x4d320b JNE	4d321b

  (1782) 0x4d320d VMOVSD	(%R8,%RSI,8),%XMM2

  (1782) 0x4d3213 VMINSD	%XMM2,%XMM0,%XMM0

  (1782) 0x4d3217 VADDSD	%XMM2,%XMM1,%XMM1

  (1782) 0x4d321b LEA	0x2(%RAX),%RSI

  (1782) 0x4d321f MOV	(%R14,%RSI,8),%R9

  (1782) 0x4d3223 CMP	(%R15,%R9,8),%RDI

  (1782) 0x4d3227 JNE	4d3239

  (1782) 0x4d3229 VMOVSD	(%R8,%RSI,8),%XMM8

  (1782) 0x4d322f VMINSD	%XMM8,%XMM0,%XMM0

  (1782) 0x4d3234 VADDSD	%XMM8,%XMM1,%XMM1

  (1782) 0x4d3239 LEA	0x3(%RAX),%RSI

  (1782) 0x4d323d MOV	(%R14,%RSI,8),%R9

  (1782) 0x4d3241 CMP	(%R15,%R9,8),%RDI

  (1782) 0x4d3245 JNE	4d3257

  (1782) 0x4d3247 VMOVSD	(%R8,%RSI,8),%XMM9

  (1782) 0x4d324d VMINSD	%XMM9,%XMM0,%XMM0

  (1782) 0x4d3252 VADDSD	%XMM9,%XMM1,%XMM1

  (1782) 0x4d3257 LEA	0x4(%RAX),%RSI

  (1782) 0x4d325b MOV	(%R14,%RSI,8),%R9

  (1782) 0x4d325f CMP	(%R15,%R9,8),%RDI

  (1782) 0x4d3263 JNE	4d3275

  (1782) 0x4d3265 VMOVSD	(%R8,%RSI,8),%XMM10

  (1782) 0x4d326b VMINSD	%XMM10,%XMM0,%XMM0

  (1782) 0x4d3270 VADDSD	%XMM10,%XMM1,%XMM1

  (1782) 0x4d3275 LEA	0x5(%RAX),%RSI

  (1782) 0x4d3279 MOV	(%R14,%RSI,8),%R9

  (1782) 0x4d327d CMP	(%R15,%R9,8),%RDI

  (1782) 0x4d3281 JNE	4d3293

  (1782) 0x4d3283 VMOVSD	(%R8,%RSI,8),%XMM11

  (1782) 0x4d3289 VMINSD	%XMM11,%XMM0,%XMM0

  (1782) 0x4d328e VADDSD	%XMM11,%XMM1,%XMM1

  (1782) 0x4d3293 LEA	0x6(%RAX),%RSI

  (1782) 0x4d3297 MOV	(%R14,%RSI,8),%R9

  (1782) 0x4d329b CMP	(%R15,%R9,8),%RDI

  (1782) 0x4d329f JNE	4d32b1

  (1782) 0x4d32a1 VMOVSD	(%R8,%RSI,8),%XMM12

  (1782) 0x4d32a7 VMINSD	%XMM12,%XMM0,%XMM0

  (1782) 0x4d32ac VADDSD	%XMM12,%XMM1,%XMM1

  (1782) 0x4d32b1 LEA	0x7(%RAX),%RSI

  (1782) 0x4d32b5 MOV	-0x60(%RBP),%RAX

  (1782) 0x4d32b9 CMP	%RAX,%RSI

  (1782) 0x4d32bc JNE	4d31c7

(1762) 0x4d32c2 MOV	-0x70(%RBP),%RDI

(1762) 0x4d32c6 MOV	(%RCX),%R9

(1762) 0x4d32c9 MOV	(%RDI),%RAX

(1762) 0x4d32cc MOV	%R9,-0x88(%RBP)

(1762) 0x4d32d3 MOV	%RAX,-0xb0(%RBP)

(1762) 0x4d32da CMP	%R9,%RAX

(1762) 0x4d32dd JGE	4d3569

(1762) 0x4d32e3 MOV	-0x88(%RBP),%RDI

(1762) 0x4d32ea MOV	(%R15,%RBX,8),%R9

(1762) 0x4d32ee SUB	%RAX,%RDI

(1762) 0x4d32f1 MOV	%RAX,%RSI

(1762) 0x4d32f4 AND	$0x7,%EDI

(1762) 0x4d32f7 JE	4d3433

(1762) 0x4d32fd CMP	$0x1,%RDI

(1762) 0x4d3301 JE	4d3401

(1762) 0x4d3307 CMP	$0x2,%RDI

(1762) 0x4d330b JE	4d33df

(1762) 0x4d3311 CMP	$0x3,%RDI

(1762) 0x4d3315 JE	4d33bd

(1762) 0x4d331b CMP	$0x4,%RDI

(1762) 0x4d331f JE	4d339d

(1762) 0x4d3321 CMP	$0x5,%RDI

(1762) 0x4d3325 JE	4d337b

(1762) 0x4d3327 CMP	$0x6,%RDI

(1762) 0x4d332b JE	4d3365

(1762) 0x4d332d MOV	-0xb0(%RBP),%RSI

(1762) 0x4d3334 MOV	-0x78(%RBP),%RAX

(1762) 0x4d3338 MOV	(%R13,%RSI,8),%RSI

(1762) 0x4d333d CMP	(%RAX,%RSI,8),%R9

(1762) 0x4d3341 JNE	4d335a

(1762) 0x4d3343 MOV	-0xb0(%RBP),%RSI

(1762) 0x4d334a VMOVSD	(%R11,%RSI,8),%XMM15

(1762) 0x4d3350 VMINSD	%XMM15,%XMM0,%XMM0

(1762) 0x4d3355 VADDSD	%XMM15,%XMM1,%XMM1

(1762) 0x4d335a MOV	-0xb0(%RBP),%RAX

(1762) 0x4d3361 LEA	0x1(%RAX),%RSI

(1762) 0x4d3365 MOV	(%R13,%RSI,8),%RAX

(1762) 0x4d336a MOV	-0x78(%RBP),%RDI

(1762) 0x4d336e CMP	(%RDI,%RAX,8),%R9

(1762) 0x4d3372 JE	4d456f

(1762) 0x4d3378 INC	%RSI

(1762) 0x4d337b MOV	(%R13,%RSI,8),%RAX

(1762) 0x4d3380 MOV	-0x78(%RBP),%RDI

(1762) 0x4d3384 CMP	(%RDI,%RAX,8),%R9

(1762) 0x4d3388 JNE	4d339a

(1762) 0x4d338a VMOVSD	(%R11,%RSI,8),%XMM13

(1762) 0x4d3390 VMINSD	%XMM13,%XMM0,%XMM0

(1762) 0x4d3395 VADDSD	%XMM13,%XMM1,%XMM1

(1762) 0x4d339a INC	%RSI

(1762) 0x4d339d MOV	(%R13,%RSI,8),%RAX

(1762) 0x4d33a2 MOV	-0x78(%RBP),%RDI

(1762) 0x4d33a6 CMP	(%RDI,%RAX,8),%R9

(1762) 0x4d33aa JNE	4d33ba

(1762) 0x4d33ac VMOVSD	(%R11,%RSI,8),%XMM2

(1762) 0x4d33b2 VMINSD	%XMM2,%XMM0,%XMM0

(1762) 0x4d33b6 VADDSD	%XMM2,%XMM1,%XMM1

(1762) 0x4d33ba INC	%RSI

(1762) 0x4d33bd MOV	(%R13,%RSI,8),%RAX

(1762) 0x4d33c2 MOV	-0x78(%RBP),%RDI

(1762) 0x4d33c6 CMP	(%RDI,%RAX,8),%R9

(1762) 0x4d33ca JNE	4d33dc

(1762) 0x4d33cc VMOVSD	(%R11,%RSI,8),%XMM8

(1762) 0x4d33d2 VMINSD	%XMM8,%XMM0,%XMM0

(1762) 0x4d33d7 VADDSD	%XMM8,%XMM1,%XMM1

(1762) 0x4d33dc INC	%RSI

(1762) 0x4d33df MOV	(%R13,%RSI,8),%RAX

(1762) 0x4d33e4 MOV	-0x78(%RBP),%RDI

(1762) 0x4d33e8 CMP	(%RDI,%RAX,8),%R9

(1762) 0x4d33ec JNE	4d33fe

(1762) 0x4d33ee VMOVSD	(%R11,%RSI,8),%XMM9

(1762) 0x4d33f4 VMINSD	%XMM9,%XMM0,%XMM0

(1762) 0x4d33f9 VADDSD	%XMM9,%XMM1,%XMM1

(1762) 0x4d33fe INC	%RSI

(1762) 0x4d3401 MOV	(%R13,%RSI,8),%RAX

(1762) 0x4d3406 MOV	-0x78(%RBP),%RDI

(1762) 0x4d340a CMP	(%RDI,%RAX,8),%R9

(1762) 0x4d340e JNE	4d3420

(1762) 0x4d3410 VMOVSD	(%R11,%RSI,8),%XMM10

(1762) 0x4d3416 VMINSD	%XMM10,%XMM0,%XMM0

(1762) 0x4d341b VADDSD	%XMM10,%XMM1,%XMM1

(1762) 0x4d3420 MOV	-0x88(%RBP),%RAX

(1762) 0x4d3427 INC	%RSI

(1762) 0x4d342a CMP	%RAX,%RSI

(1762) 0x4d342d JE	4d3569

(1762) 0x4d3433 MOV	%RDX,-0xe0(%RBP)

(1762) 0x4d343a MOV	%R14,-0xd8(%RBP)

(1762) 0x4d3441 MOV	%R9,%RDI

(1762) 0x4d3444 MOV	%R12,%R14

(1762) 0x4d3447 MOV	-0x88(%RBP),%R9

(1762) 0x4d344e MOV	-0x78(%RBP),%R12

  (1781) 0x4d3452 MOV	(%R13,%RSI,8),%RDX

  (1781) 0x4d3457 CMP	(%R12,%RDX,8),%RDI

  (1781) 0x4d345b JNE	4d346d

  (1781) 0x4d345d VMOVSD	(%R11,%RSI,8),%XMM11

  (1781) 0x4d3463 VMINSD	%XMM11,%XMM0,%XMM0

  (1781) 0x4d3468 VADDSD	%XMM11,%XMM1,%XMM1

  (1781) 0x4d346d LEA	0x1(%RSI),%RAX

  (1781) 0x4d3471 MOV	(%R13,%RAX,8),%RSI

  (1781) 0x4d3476 CMP	(%R12,%RSI,8),%RDI

  (1781) 0x4d347a JNE	4d348c

  (1781) 0x4d347c VMOVSD	(%R11,%RAX,8),%XMM12

  (1781) 0x4d3482 VMINSD	%XMM12,%XMM0,%XMM0

  (1781) 0x4d3487 VADDSD	%XMM12,%XMM1,%XMM1

  (1781) 0x4d348c LEA	0x1(%RAX),%RSI

  (1781) 0x4d3490 MOV	(%R13,%RSI,8),%RDX

  (1781) 0x4d3495 CMP	(%R12,%RDX,8),%RDI

  (1781) 0x4d3499 JNE	4d34ab

  (1781) 0x4d349b VMOVSD	(%R11,%RSI,8),%XMM15

  (1781) 0x4d34a1 VMINSD	%XMM15,%XMM0,%XMM0

  (1781) 0x4d34a6 VADDSD	%XMM15,%XMM1,%XMM1

  (1781) 0x4d34ab LEA	0x2(%RAX),%RSI

  (1781) 0x4d34af MOV	(%R13,%RSI,8),%RDX

  (1781) 0x4d34b4 CMP	(%R12,%RDX,8),%RDI

  (1781) 0x4d34b8 JNE	4d34ca

  (1781) 0x4d34ba VMOVSD	(%R11,%RSI,8),%XMM14

  (1781) 0x4d34c0 VMINSD	%XMM14,%XMM0,%XMM0

  (1781) 0x4d34c5 VADDSD	%XMM14,%XMM1,%XMM1

  (1781) 0x4d34ca LEA	0x3(%RAX),%RSI

  (1781) 0x4d34ce MOV	(%R13,%RSI,8),%RDX

  (1781) 0x4d34d3 CMP	(%R12,%RDX,8),%RDI

  (1781) 0x4d34d7 JNE	4d34e9

  (1781) 0x4d34d9 VMOVSD	(%R11,%RSI,8),%XMM13

  (1781) 0x4d34df VMINSD	%XMM13,%XMM0,%XMM0

  (1781) 0x4d34e4 VADDSD	%XMM13,%XMM1,%XMM1

  (1781) 0x4d34e9 LEA	0x4(%RAX),%RSI

  (1781) 0x4d34ed MOV	(%R13,%RSI,8),%RDX

  (1781) 0x4d34f2 CMP	(%R12,%RDX,8),%RDI

  (1781) 0x4d34f6 JNE	4d3506

  (1781) 0x4d34f8 VMOVSD	(%R11,%RSI,8),%XMM2

  (1781) 0x4d34fe VMINSD	%XMM2,%XMM0,%XMM0

  (1781) 0x4d3502 VADDSD	%XMM2,%XMM1,%XMM1

  (1781) 0x4d3506 LEA	0x5(%RAX),%RSI

  (1781) 0x4d350a MOV	(%R13,%RSI,8),%RDX

  (1781) 0x4d350f CMP	(%R12,%RDX,8),%RDI

  (1781) 0x4d3513 JNE	4d3525

  (1781) 0x4d3515 VMOVSD	(%R11,%RSI,8),%XMM8

  (1781) 0x4d351b VMINSD	%XMM8,%XMM0,%XMM0

  (1781) 0x4d3520 VADDSD	%XMM8,%XMM1,%XMM1

  (1781) 0x4d3525 LEA	0x6(%RAX),%RSI

  (1781) 0x4d3529 MOV	(%R13,%RSI,8),%RDX

  (1781) 0x4d352e CMP	(%R12,%RDX,8),%RDI

  (1781) 0x4d3532 JNE	4d3544

  (1781) 0x4d3534 VMOVSD	(%R11,%RSI,8),%XMM9

  (1781) 0x4d353a VMINSD	%XMM9,%XMM0,%XMM0

  (1781) 0x4d353f VADDSD	%XMM9,%XMM1,%XMM1

  (1781) 0x4d3544 LEA	0x7(%RAX),%RSI

  (1781) 0x4d3548 CMP	%R9,%RSI

  (1781) 0x4d354b JNE	4d3452

(1762) 0x4d3551 MOV	%R9,-0x88(%RBP)

(1762) 0x4d3558 MOV	%R14,%R12

(1762) 0x4d355b MOV	-0xe0(%RBP),%RDX

(1762) 0x4d3562 MOV	-0xd8(%RBP),%R14

(1762) 0x4d3569 VANDPD	%XMM3,%XMM7,%XMM7

(1762) 0x4d356d VMULSD	%XMM5,%XMM7,%XMM10

(1762) 0x4d3571 MOV	-0x80(%RBP),%RAX

(1762) 0x4d3575 MOV	-0x60(%RBP),%RDI

(1762) 0x4d3579 MOV	-0xb0(%RBP),%RSI

(1762) 0x4d3580 MOV	-0x88(%RBP),%R9

(1762) 0x4d3587 MOVQ	$-0x1,(%R12,%RAX,8)

(1762) 0x4d358f SUB	%RAX,%RDI

(1762) 0x4d3592 SUB	%RSI,%R9

(1762) 0x4d3595 MOV	-0x58(%RBP),%RAX

(1762) 0x4d3599 VANDPD	%XMM3,%XMM1,%XMM1

(1762) 0x4d359d ADD	%R9,%R10

(1762) 0x4d35a0 VCOMISD	%XMM10,%XMM1

(1762) 0x4d35a5 LEA	-0x1(%RDX,%RDI,1),%RDX

(1762) 0x4d35aa MOV	-0x8(%RAX),%RDI

(1762) 0x4d35ae MOV	%RDI,-0x60(%RBP)

(1762) 0x4d35b2 LEA	0x1(%RDI),%RSI

(1762) 0x4d35b6 MOV	(%RAX),%RDI

(1762) 0x4d35b9 JBE	4d35c8

(1762) 0x4d35bb CMPB	$0,-0xb9(%RBP)

(1762) 0x4d35c2 JNE	4d44b8

(1762) 0x4d35c8 CMP	%RDI,%RSI

(1762) 0x4d35cb JGE	4d3604

(1762) 0x4d35cd VMULSD	%XMM0,%XMM4,%XMM11

(1762) 0x4d35d1 MOV	-0x58(%RBP),%RDI

(1762) 0x4d35d5 NOPL	(%RAX)

  (1780) 0x4d35d8 VCOMISD	(%R8,%RSI,8),%XMM11

  (1780) 0x4d35de JBE	4d35ee

  (1780) 0x4d35e0 MOV	(%R14,%RSI,8),%RAX

  (1780) 0x4d35e4 MOV	(%R15,%RAX,8),%R9

  (1780) 0x4d35e8 CMP	%R9,(%R15,%RBX,8)

  (1780) 0x4d35ec JE	4d35f8

  (1780) 0x4d35ee DEC	%RDX

  (1780) 0x4d35f1 MOV	$-0x1,%RAX

  (1780) 0x4d35f8 MOV	%RAX,(%R12,%RSI,8)

  (1780) 0x4d35fc INC	%RSI

  (1780) 0x4d35ff CMP	%RSI,(%RDI)

  (1780) 0x4d3602 JG	4d35d8

(1762) 0x4d3604 MOV	-0x70(%RBP),%RSI

(1762) 0x4d3608 MOV	(%RSI),%RSI

(1762) 0x4d360b CMP	(%RCX),%RSI

(1762) 0x4d360e JGE	4d3651

(1762) 0x4d3610 VMULSD	%XMM0,%XMM4,%XMM0

(1762) 0x4d3614 MOV	%RDX,-0x60(%RBP)

(1762) 0x4d3618 MOV	-0x68(%RBP),%RDI

(1762) 0x4d361c MOV	-0x78(%RBP),%R9

  (1779) 0x4d3620 VCOMISD	(%R11,%RSI,8),%XMM0

  (1779) 0x4d3626 JBE	4d3637

  (1779) 0x4d3628 MOV	(%R13,%RSI,8),%RAX

  (1779) 0x4d362d MOV	(%R9,%RAX,8),%RDX

  (1779) 0x4d3631 CMP	%RDX,(%R15,%RBX,8)

  (1779) 0x4d3635 JE	4d3641

  (1779) 0x4d3637 DEC	%R10

  (1779) 0x4d363a MOV	$-0x1,%RAX

  (1779) 0x4d3641 MOV	%RAX,(%RDI,%RSI,8)

  (1779) 0x4d3645 INC	%RSI

  (1779) 0x4d3648 CMP	%RSI,(%RCX)

  (1779) 0x4d364b JG	4d3620

(1762) 0x4d364d MOV	-0x60(%RBP),%RDX

(1762) 0x4d3651 MOV	-0xa8(%RBP),%RAX

(1762) 0x4d3658 INC	%RBX

(1762) 0x4d365b ADDQ	$0x8,-0x70(%RBP)

(1762) 0x4d3660 ADDQ	$0x8,-0x58(%RBP)

(1762) 0x4d3665 ADD	$0x8,%RCX

(1762) 0x4d3669 CMP	%RAX,%RBX

(1762) 0x4d366c JNE	4d3050

0x4d3672 MOV	%R10,-0x38(%RBP)

0x4d3676 MOV	%RDX,-0x40(%RBP)

0x4d367a MOV	%R12,%RBX

0x4d367d MOV	-0x100(%RBP),%RSI

0x4d3684 MOV	-0x68(%RBP),%R12

0x4d3688 MOV	-0xb8(%RBP),%R15

0x4d368f MOV	-0x90(%RBP),%R14

0x4d3696 LEA	(,%RSI,8),%RSI

0x4d369e MOV	-0xe8(%RBP),%R8

0x4d36a5 LEA	(%R15,%RSI,1),%RCX

0x4d36a9 LEA	-0x38(%RBP),%RDX

0x4d36ad ADD	%R14,%RSI

0x4d36b0 LEA	-0x40(%RBP),%RDI

0x4d36b4 CALL	5564d0 <hypre_prefix_sum_pair>

0x4d36b9 MOV	-0x50(%RBP),%R11

0x4d36bd MOV	-0x48(%RBP),%RDX

0x4d36c1 CMP	%RDX,%R11

0x4d36c4 JGE	4d37b5

0x4d36ca MOV	-0x90(%RBP),%RCX

0x4d36d1 SAL	$0x3,%R11

0x4d36d5 MOV	-0xd0(%RBP),%RDI

0x4d36dc MOV	-0xc8(%RBP),%RSI

0x4d36e3 MOV	%R15,%R10

0x4d36e6 LEA	(%RCX,%RDX,8),%R9

0x4d36ea LEA	(%RCX,%R11,1),%R8

0x4d36ee ADD	%R11,%R10

0x4d36f1 ADD	$0x8,%R11

0x4d36f5 MOV	%R9,-0x58(%RBP)

0x4d36f9 ADD	%R11,%RDI

0x4d36fc ADD	%R11,%RSI

0x4d36ff MOV	-0x40(%RBP),%R14

0x4d3703 MOV	-0x38(%RBP),%R13

0x4d3707 MOV	-0xf8(%RBP),%R11

0x4d370e MOV	-0xf0(%RBP),%R9

0x4d3715 NOPL	(%RAX)

(1759) 0x4d3718 ADD	%R14,(%R8)

(1759) 0x4d371b MOV	(%R10),%RDX

(1759) 0x4d371e ADD	%R13,%RDX

(1759) 0x4d3721 MOV	%RDX,(%R10)

(1759) 0x4d3724 MOV	-0x8(%RDI),%RAX

(1759) 0x4d3728 MOV	(%RDI),%R15

(1759) 0x4d372b MOV	(%R8),%RCX

(1759) 0x4d372e CMP	%R15,%RAX

(1759) 0x4d3731 JGE	4d375e

(1759) 0x4d3733 NOPW	%CS:(%RAX,%RAX,1)

(1759) 0x4d373e XCHG	%AX,%AX

  (1761) 0x4d3740 MOV	(%RBX,%RAX,8),%RDX

  (1761) 0x4d3744 TEST	%RDX,%RDX

  (1761) 0x4d3747 JS	4d3753

  (1761) 0x4d3749 MOV	%RDX,(%R11,%RCX,8)

  (1761) 0x4d374d INC	%RCX

  (1761) 0x4d3750 MOV	(%RDI),%R15

  (1761) 0x4d3753 INC	%RAX

  (1761) 0x4d3756 CMP	%R15,%RAX

  (1761) 0x4d3759 JL	4d3740

(1759) 0x4d375b MOV	(%R10),%RDX

(1759) 0x4d375e MOV	-0x8(%RSI),%RAX

(1759) 0x4d3762 MOV	(%RSI),%R15

(1759) 0x4d3765 CMP	%R15,%RAX

(1759) 0x4d3768 JGE	4d379b

(1759) 0x4d376a NOPW	%CS:(%RAX,%RAX,1)

(1759) 0x4d3775 NOPW	%CS:(%RAX,%RAX,1)

  (1760) 0x4d3780 MOV	(%R12,%RAX,8),%RCX

  (1760) 0x4d3784 TEST	%RCX,%RCX

  (1760) 0x4d3787 JS	4d3793

  (1760) 0x4d3789 MOV	%RCX,(%R9,%RDX,8)

  (1760) 0x4d378d INC	%RDX

  (1760) 0x4d3790 MOV	(%RSI),%R15

  (1760) 0x4d3793 INC	%RAX

  (1760) 0x4d3796 CMP	%R15,%RAX

  (1760) 0x4d3799 JL	4d3780

(1759) 0x4d379b ADD	$0x8,%R8

(1759) 0x4d379f ADD	$0x8,%R10

(1759) 0x4d37a3 ADD	$0x8,%RDI

(1759) 0x4d37a7 ADD	$0x8,%RSI

(1759) 0x4d37ab CMP	%R8,-0x58(%RBP)

(1759) 0x4d37af JNE	4d3718

0x4d37b5 ADD	$0xd8,%RSP

0x4d37bc POP	%RBX

0x4d37bd POP	%R12

0x4d37bf POP	%R13

0x4d37c1 POP	%R14

0x4d37c3 POP	%R15

0x4d37c5 POP	%RBP

0x4d37c6 RET

0x4d37c7 NOPW	(%RAX,%RAX,1)

(1762) 0x4d37d0 VCOMISD	%XMM7,%XMM6

(1762) 0x4d37d4 JA	4d4110

(1762) 0x4d37da CMP	%R9,%RSI

(1762) 0x4d37dd JGE	4d45b3

(1762) 0x4d37e3 LEA	(%R8,%R9,8),%RAX

(1762) 0x4d37e7 LEA	0x8(%R8,%RDI,1),%RSI

(1762) 0x4d37ec MOV	%RAX,%RDI

(1762) 0x4d37ef SUB	%RSI,%RDI

(1762) 0x4d37f2 SUB	$0x8,%RDI

(1762) 0x4d37f6 SHR	$0x3,%RDI

(1762) 0x4d37fa INC	%RDI

(1762) 0x4d37fd VMOVAPD	%XMM7,%XMM14

(1762) 0x4d3801 VXORPD	%XMM13,%XMM13,%XMM13

(1762) 0x4d3806 AND	$0x7,%EDI

(1762) 0x4d3809 JE	4d38b6

(1762) 0x4d380f CMP	$0x1,%RDI

(1762) 0x4d3813 JE	4d389f

(1762) 0x4d3819 CMP	$0x2,%RDI

(1762) 0x4d381d JE	4d388d

(1762) 0x4d381f CMP	$0x3,%RDI

(1762) 0x4d3823 JE	4d387b

(1762) 0x4d3825 CMP	$0x4,%RDI

(1762) 0x4d3829 JE	4d3869

(1762) 0x4d382b CMP	$0x5,%RDI

(1762) 0x4d382f JE	4d3857

(1762) 0x4d3831 CMP	$0x6,%RDI

(1762) 0x4d3835 JE	4d3847

(1762) 0x4d3837 VMOVSD	(%RSI),%XMM1

(1762) 0x4d383b ADD	$0x8,%RSI

(1762) 0x4d383f VMINSD	%XMM1,%XMM13,%XMM13

(1762) 0x4d3843 VADDSD	%XMM1,%XMM7,%XMM14

(1762) 0x4d3847 VMOVSD	(%RSI),%XMM2

(1762) 0x4d384b ADD	$0x8,%RSI

(1762) 0x4d384f VMINSD	%XMM2,%XMM13,%XMM13

(1762) 0x4d3853 VADDSD	%XMM2,%XMM14,%XMM14

(1762) 0x4d3857 VMOVSD	(%RSI),%XMM8

(1762) 0x4d385b ADD	$0x8,%RSI

(1762) 0x4d385f VMINSD	%XMM8,%XMM13,%XMM13

(1762) 0x4d3864 VADDSD	%XMM8,%XMM14,%XMM14

(1762) 0x4d3869 VMOVSD	(%RSI),%XMM9

(1762) 0x4d386d ADD	$0x8,%RSI

(1762) 0x4d3871 VMINSD	%XMM9,%XMM13,%XMM13

(1762) 0x4d3876 VADDSD	%XMM9,%XMM14,%XMM14

(1762) 0x4d387b VMOVSD	(%RSI),%XMM10

(1762) 0x4d387f ADD	$0x8,%RSI

(1762) 0x4d3883 VMINSD	%XMM10,%XMM13,%XMM13

(1762) 0x4d3888 VADDSD	%XMM10,%XMM14,%XMM14

(1762) 0x4d388d VMOVSD	(%RSI),%XMM11

(1762) 0x4d3891 ADD	$0x8,%RSI

(1762) 0x4d3895 VMINSD	%XMM11,%XMM13,%XMM13

(1762) 0x4d389a VADDSD	%XMM11,%XMM14,%XMM14

(1762) 0x4d389f VMOVSD	(%RSI),%XMM12

(1762) 0x4d38a3 ADD	$0x8,%RSI

(1762) 0x4d38a7 VMINSD	%XMM12,%XMM13,%XMM13

(1762) 0x4d38ac VADDSD	%XMM12,%XMM14,%XMM14

(1762) 0x4d38b1 CMP	%RSI,%RAX

(1762) 0x4d38b4 JE	4d3930

  (1774) 0x4d38b6 VMOVSD	(%RSI),%XMM15

  (1774) 0x4d38ba VMOVSD	0x8(%RSI),%XMM2

  (1774) 0x4d38bf VMINSD	%XMM15,%XMM13,%XMM0

  (1774) 0x4d38c4 VADDSD	%XMM15,%XMM14,%XMM1

  (1774) 0x4d38c9 VMOVSD	0x10(%RSI),%XMM10

  (1774) 0x4d38ce VMINSD	%XMM2,%XMM0,%XMM8

  (1774) 0x4d38d2 VADDSD	%XMM2,%XMM1,%XMM9

  (1774) 0x4d38d6 VMOVSD	0x18(%RSI),%XMM13

  (1774) 0x4d38db VMINSD	%XMM10,%XMM8,%XMM11

  (1774) 0x4d38e0 VADDSD	%XMM10,%XMM9,%XMM12

  (1774) 0x4d38e5 VMOVSD	0x20(%RSI),%XMM1

  (1774) 0x4d38ea VMINSD	%XMM13,%XMM11,%XMM14

  (1774) 0x4d38ef VADDSD	%XMM13,%XMM12,%XMM15

  (1774) 0x4d38f4 VMOVSD	0x28(%RSI),%XMM2

  (1774) 0x4d38f9 VMINSD	%XMM1,%XMM14,%XMM0

  (1774) 0x4d38fd VADDSD	%XMM1,%XMM15,%XMM8

  (1774) 0x4d3901 VMOVSD	0x30(%RSI),%XMM11

  (1774) 0x4d3906 VMINSD	%XMM2,%XMM0,%XMM9

  (1774) 0x4d390a VADDSD	%XMM2,%XMM8,%XMM10

  (1774) 0x4d390e VMOVSD	0x38(%RSI),%XMM15

  (1774) 0x4d3913 VMINSD	%XMM11,%XMM9,%XMM12

  (1774) 0x4d3918 VADDSD	%XMM11,%XMM10,%XMM14

  (1774) 0x4d391d ADD	$0x40,%RSI

  (1774) 0x4d3921 VMINSD	%XMM15,%XMM12,%XMM13

  (1774) 0x4d3926 VADDSD	%XMM15,%XMM14,%XMM14

  (1774) 0x4d392b CMP	%RSI,%RAX

  (1774) 0x4d392e JNE	4d38b6

(1762) 0x4d3930 MOV	-0x70(%RBP),%R9

(1762) 0x4d3934 MOV	(%R9),%RSI

(1762) 0x4d3937 MOV	(%RCX),%R9

(1762) 0x4d393a MOV	%RSI,-0x88(%RBP)

(1762) 0x4d3941 CMP	%R9,%RSI

(1762) 0x4d3944 JGE	4d3a8b

(1762) 0x4d394a LEA	(%R11,%R9,8),%RAX

(1762) 0x4d394e LEA	(%R11,%RSI,8),%RSI

(1762) 0x4d3952 MOV	%RAX,%RDI

(1762) 0x4d3955 SUB	%RSI,%RDI

(1762) 0x4d3958 SUB	$0x8,%RDI

(1762) 0x4d395c SHR	$0x3,%RDI

(1762) 0x4d3960 INC	%RDI

(1762) 0x4d3963 AND	$0x7,%EDI

(1762) 0x4d3966 JE	4d3a11

(1762) 0x4d396c CMP	$0x1,%RDI

(1762) 0x4d3970 JE	4d39fa

(1762) 0x4d3976 CMP	$0x2,%RDI

(1762) 0x4d397a JE	4d39e8

(1762) 0x4d397c CMP	$0x3,%RDI

(1762) 0x4d3980 JE	4d39d6

(1762) 0x4d3982 CMP	$0x4,%RDI

(1762) 0x4d3986 JE	4d39c6

(1762) 0x4d3988 CMP	$0x5,%RDI

(1762) 0x4d398c JE	4d39b4

(1762) 0x4d398e CMP	$0x6,%RDI

(1762) 0x4d3992 JE	4d39a4

(1762) 0x4d3994 VMOVSD	(%RSI),%XMM1

(1762) 0x4d3998 ADD	$0x8,%RSI

(1762) 0x4d399c VMINSD	%XMM1,%XMM13,%XMM13

(1762) 0x4d39a0 VADDSD	%XMM1,%XMM14,%XMM14

(1762) 0x4d39a4 VMOVSD	(%RSI),%XMM0

(1762) 0x4d39a8 ADD	$0x8,%RSI

(1762) 0x4d39ac VMINSD	%XMM0,%XMM13,%XMM13

(1762) 0x4d39b0 VADDSD	%XMM0,%XMM14,%XMM14

(1762) 0x4d39b4 VMOVSD	(%RSI),%XMM8

(1762) 0x4d39b8 ADD	$0x8,%RSI

(1762) 0x4d39bc VMINSD	%XMM8,%XMM13,%XMM13

(1762) 0x4d39c1 VADDSD	%XMM8,%XMM14,%XMM14

(1762) 0x4d39c6 VMOVSD	(%RSI),%XMM2

(1762) 0x4d39ca ADD	$0x8,%RSI

(1762) 0x4d39ce VMINSD	%XMM2,%XMM13,%XMM13

(1762) 0x4d39d2 VADDSD	%XMM2,%XMM14,%XMM14

(1762) 0x4d39d6 VMOVSD	(%RSI),%XMM9

(1762) 0x4d39da ADD	$0x8,%RSI

(1762) 0x4d39de VMINSD	%XMM9,%XMM13,%XMM13

(1762) 0x4d39e3 VADDSD	%XMM9,%XMM14,%XMM14

(1762) 0x4d39e8 VMOVSD	(%RSI),%XMM10

(1762) 0x4d39ec ADD	$0x8,%RSI

(1762) 0x4d39f0 VMINSD	%XMM10,%XMM13,%XMM13

(1762) 0x4d39f5 VADDSD	%XMM10,%XMM14,%XMM14

(1762) 0x4d39fa VMOVSD	(%RSI),%XMM11

(1762) 0x4d39fe ADD	$0x8,%RSI

(1762) 0x4d3a02 VMINSD	%XMM11,%XMM13,%XMM13

(1762) 0x4d3a07 VADDSD	%XMM11,%XMM14,%XMM14

(1762) 0x4d3a0c CMP	%RSI,%RAX

(1762) 0x4d3a0f JE	4d3a8b

  (1773) 0x4d3a11 VMOVSD	(%RSI),%XMM12

  (1773) 0x4d3a15 VMOVSD	0x8(%RSI),%XMM15

  (1773) 0x4d3a1a VMINSD	%XMM12,%XMM13,%XMM13

  (1773) 0x4d3a1f VADDSD	%XMM12,%XMM14,%XMM14

  (1773) 0x4d3a24 VMOVSD	0x10(%RSI),%XMM8

  (1773) 0x4d3a29 VMINSD	%XMM15,%XMM13,%XMM0

  (1773) 0x4d3a2e VADDSD	%XMM15,%XMM14,%XMM1

  (1773) 0x4d3a33 VMOVSD	0x18(%RSI),%XMM2

  (1773) 0x4d3a38 VMINSD	%XMM8,%XMM0,%XMM9

  (1773) 0x4d3a3d VADDSD	%XMM8,%XMM1,%XMM10

  (1773) 0x4d3a42 VMOVSD	0x20(%RSI),%XMM13

  (1773) 0x4d3a47 VMINSD	%XMM2,%XMM9,%XMM11

  (1773) 0x4d3a4b VADDSD	%XMM2,%XMM10,%XMM12

  (1773) 0x4d3a4f VMOVSD	0x28(%RSI),%XMM1

  (1773) 0x4d3a54 VMINSD	%XMM13,%XMM11,%XMM14

  (1773) 0x4d3a59 VADDSD	%XMM13,%XMM12,%XMM15

  (1773) 0x4d3a5e VMOVSD	0x30(%RSI),%XMM9

  (1773) 0x4d3a63 VMINSD	%XMM1,%XMM14,%XMM0

  (1773) 0x4d3a67 VADDSD	%XMM1,%XMM15,%XMM8

  (1773) 0x4d3a6b VMOVSD	0x38(%RSI),%XMM2

  (1773) 0x4d3a70 VMINSD	%XMM9,%XMM0,%XMM10

  (1773) 0x4d3a75 VADDSD	%XMM9,%XMM8,%XMM11

  (1773) 0x4d3a7a ADD	$0x40,%RSI

  (1773) 0x4d3a7e VMINSD	%XMM2,%XMM10,%XMM13

  (1773) 0x4d3a82 VADDSD	%XMM2,%XMM11,%XMM14

  (1773) 0x4d3a86 CMP	%RSI,%RAX

  (1773) 0x4d3a89 JNE	4d3a11

(1762) 0x4d3a8b VANDPD	%XMM3,%XMM7,%XMM7

(1762) 0x4d3a8f VMULSD	%XMM5,%XMM7,%XMM12

(1762) 0x4d3a93 MOV	-0x80(%RBP),%RAX

(1762) 0x4d3a97 MOV	-0x88(%RBP),%RDI

(1762) 0x4d3a9e MOVQ	$-0x1,(%R12,%RAX,8)

(1762) 0x4d3aa6 SUB	%RDI,%R9

(1762) 0x4d3aa9 MOV	-0x60(%RBP),%RSI

(1762) 0x4d3aad ADD	%R9,%R10

(1762) 0x4d3ab0 VANDPD	%XMM3,%XMM14,%XMM14

(1762) 0x4d3ab4 MOV	-0x58(%RBP),%R9

(1762) 0x4d3ab8 SUB	%RAX,%RSI

(1762) 0x4d3abb VCOMISD	%XMM12,%XMM14

(1762) 0x4d3ac0 LEA	-0x1(%RDX,%RSI,1),%RDX

(1762) 0x4d3ac5 MOV	-0x8(%R9),%RSI

(1762) 0x4d3ac9 MOV	(%R9),%RDI

(1762) 0x4d3acc MOV	%RSI,-0x60(%RBP)

(1762) 0x4d3ad0 LEA	0x1(%RSI),%RSI

(1762) 0x4d3ad4 JBE	4d3ae3

(1762) 0x4d3ad6 CMPB	$0,-0xb9(%RBP)

(1762) 0x4d3add JNE	4d44b8

(1762) 0x4d3ae3 CMP	%RSI,%RDI

(1762) 0x4d3ae6 JLE	4d3b1c

(1762) 0x4d3ae8 VMULSD	%XMM13,%XMM4,%XMM15

(1762) 0x4d3aed NOPW	%CS:(%RAX,%RAX,1)

(1762) 0x4d3af8 NOPL	(%RAX,%RAX,1)

  (1772) 0x4d3b00 VCOMISD	(%R8,%RSI,8),%XMM15

  (1772) 0x4d3b06 JBE	4d3b80

  (1772) 0x4d3b08 MOV	(%R14,%RSI,8),%RAX

  (1772) 0x4d3b0c MOV	-0x58(%RBP),%R9

  (1772) 0x4d3b10 MOV	%RAX,(%R12,%RSI,8)

  (1772) 0x4d3b14 INC	%RSI

  (1772) 0x4d3b17 CMP	%RSI,(%R9)

  (1772) 0x4d3b1a JG	4d3b00

(1762) 0x4d3b1c MOV	-0x70(%RBP),%RSI

(1762) 0x4d3b20 MOV	(%RSI),%R9

(1762) 0x4d3b23 CMP	(%RCX),%R9

(1762) 0x4d3b26 JGE	4d3651

(1762) 0x4d3b2c VMULSD	%XMM13,%XMM4,%XMM13

(1762) 0x4d3b31 NOPL	(%RAX)

  (1770) 0x4d3b38 VCOMISD	(%R11,%R9,8),%XMM13

  (1770) 0x4d3b3e JBE	4d3b61

  (1771) 0x4d3b40 MOV	(%R13,%R9,8),%RAX

  (1771) 0x4d3b45 MOV	-0x68(%RBP),%RDI

  (1771) 0x4d3b49 MOV	%RAX,(%RDI,%R9,8)

  (1771) 0x4d3b4d INC	%R9

  (1771) 0x4d3b50 CMP	%R9,(%RCX)

  (1771) 0x4d3b53 JLE	4d3651

  (1771) 0x4d3b59 VCOMISD	(%R11,%R9,8),%XMM13

  (1771) 0x4d3b5f JA	4d3b40

  (1770) 0x4d3b61 MOV	-0x68(%RBP),%RSI

  (1770) 0x4d3b65 DEC	%R10

  (1770) 0x4d3b68 MOVQ	$-0x1,(%RSI,%R9,8)

  (1770) 0x4d3b70 INC	%R9

  (1770) 0x4d3b73 CMP	%R9,(%RCX)

  (1770) 0x4d3b76 JG	4d3b38

(1762) 0x4d3b78 JMP	4d3651

0x4d3b7d NOPL	(%RAX)

  (1772) 0x4d3b80 MOVQ	$-0x1,(%R12,%RSI,8)

  (1772) 0x4d3b88 MOV	-0x58(%RBP),%RDI

  (1772) 0x4d3b8c INC	%RSI

  (1772) 0x4d3b8f DEC	%RDX

  (1772) 0x4d3b92 CMP	%RSI,(%RDI)

  (1772) 0x4d3b95 JG	4d3b00

(1762) 0x4d3b9b JMP	4d3b1c

(1762) 0x4d3ba0 CMP	%R9,%RSI

(1762) 0x4d3ba3 JGE	4d45a6

(1762) 0x4d3ba9 MOV	%R9,%RAX

(1762) 0x4d3bac SUB	%RSI,%RAX

(1762) 0x4d3baf MOV	(%R15,%RBX,8),%RDI

(1762) 0x4d3bb3 VMOVAPD	%XMM7,%XMM0

(1762) 0x4d3bb7 VXORPD	%XMM1,%XMM1,%XMM1

(1762) 0x4d3bbb AND	$0x7,%EAX

(1762) 0x4d3bbe JE	4d3cae

(1762) 0x4d3bc4 CMP	$0x1,%RAX

(1762) 0x4d3bc8 JE	4d3c84

(1762) 0x4d3bce CMP	$0x2,%RAX

(1762) 0x4d3bd2 JE	4d3c67

(1762) 0x4d3bd8 CMP	$0x3,%RAX

(1762) 0x4d3bdc JE	4d3c4c

(1762) 0x4d3bde CMP	$0x4,%RAX

(1762) 0x4d3be2 JE	4d3c2f

(1762) 0x4d3be4 CMP	$0x5,%RAX

(1762) 0x4d3be8 JE	4d3c1e

(1762) 0x4d3bea CMP	$0x6,%RAX

(1762) 0x4d3bee JE	4d3c01

(1762) 0x4d3bf0 MOV	(%R14,%RSI,8),%R9

(1762) 0x4d3bf4 CMP	(%R15,%R9,8),%RDI

(1762) 0x4d3bf8 JE	4d45ed

(1762) 0x4d3bfe INC	%RSI

(1762) 0x4d3c01 MOV	(%R14,%RSI,8),%RAX

(1762) 0x4d3c05 CMP	(%R15,%RAX,8),%RDI

(1762) 0x4d3c09 JNE	4d3c1b

(1762) 0x4d3c0b VMOVSD	(%R8,%RSI,8),%XMM15

(1762) 0x4d3c11 VMAXSD	%XMM15,%XMM1,%XMM1

(1762) 0x4d3c16 VADDSD	%XMM15,%XMM0,%XMM0

(1762) 0x4d3c1b INC	%RSI

(1762) 0x4d3c1e MOV	(%R14,%RSI,8),%R9

(1762) 0x4d3c22 CMP	(%R15,%R9,8),%RDI

(1762) 0x4d3c26 JE	4d455a

(1762) 0x4d3c2c INC	%RSI

(1762) 0x4d3c2f MOV	(%R14,%RSI,8),%RAX

(1762) 0x4d3c33 CMP	(%R15,%RAX,8),%RDI

(1762) 0x4d3c37 JNE	4d3c49

(1762) 0x4d3c39 VMOVSD	(%R8,%RSI,8),%XMM13

(1762) 0x4d3c3f VMAXSD	%XMM13,%XMM1,%XMM1

(1762) 0x4d3c44 VADDSD	%XMM13,%XMM0,%XMM0

(1762) 0x4d3c49 INC	%RSI

(1762) 0x4d3c4c MOV	(%R14,%RSI,8),%R9

(1762) 0x4d3c50 CMP	(%R15,%R9,8),%RDI

(1762) 0x4d3c54 JNE	4d3c64

(1762) 0x4d3c56 VMOVSD	(%R8,%RSI,8),%XMM2

(1762) 0x4d3c5c VMAXSD	%XMM2,%XMM1,%XMM1

(1762) 0x4d3c60 VADDSD	%XMM2,%XMM0,%XMM0

(1762) 0x4d3c64 INC	%RSI

(1762) 0x4d3c67 MOV	(%R14,%RSI,8),%RAX

(1762) 0x4d3c6b CMP	(%R15,%RAX,8),%RDI

(1762) 0x4d3c6f JNE	4d3c81

(1762) 0x4d3c71 VMOVSD	(%R8,%RSI,8),%XMM8

(1762) 0x4d3c77 VMAXSD	%XMM8,%XMM1,%XMM1

(1762) 0x4d3c7c VADDSD	%XMM8,%XMM0,%XMM0

(1762) 0x4d3c81 INC	%RSI

(1762) 0x4d3c84 MOV	(%R14,%RSI,8),%R9

(1762) 0x4d3c88 CMP	(%R15,%R9,8),%RDI

(1762) 0x4d3c8c JNE	4d3c9e

(1762) 0x4d3c8e VMOVSD	(%R8,%RSI,8),%XMM9

(1762) 0x4d3c94 VMAXSD	%XMM9,%XMM1,%XMM1

(1762) 0x4d3c99 VADDSD	%XMM9,%XMM0,%XMM0

(1762) 0x4d3c9e MOV	-0x60(%RBP),%RAX

(1762) 0x4d3ca2 INC	%RSI

(1762) 0x4d3ca5 CMP	%RAX,%RSI

(1762) 0x4d3ca8 JE	4d3da9

  (1778) 0x4d3cae MOV	(%R14,%RSI,8),%R9

  (1778) 0x4d3cb2 CMP	(%R15,%R9,8),%RDI

  (1778) 0x4d3cb6 JNE	4d3cc8

  (1778) 0x4d3cb8 VMOVSD	(%R8,%RSI,8),%XMM10

  (1778) 0x4d3cbe VMAXSD	%XMM10,%XMM1,%XMM1

  (1778) 0x4d3cc3 VADDSD	%XMM10,%XMM0,%XMM0

  (1778) 0x4d3cc8 LEA	0x1(%RSI),%RAX

  (1778) 0x4d3ccc MOV	(%R14,%RAX,8),%RSI

  (1778) 0x4d3cd0 CMP	(%R15,%RSI,8),%RDI

  (1778) 0x4d3cd4 JNE	4d3ce6

  (1778) 0x4d3cd6 VMOVSD	(%R8,%RAX,8),%XMM11

  (1778) 0x4d3cdc VMAXSD	%XMM11,%XMM1,%XMM1

  (1778) 0x4d3ce1 VADDSD	%XMM11,%XMM0,%XMM0

  (1778) 0x4d3ce6 LEA	0x1(%RAX),%RSI

  (1778) 0x4d3cea MOV	(%R14,%RSI,8),%R9

  (1778) 0x4d3cee CMP	(%R15,%R9,8),%RDI

  (1778) 0x4d3cf2 JNE	4d3d04

  (1778) 0x4d3cf4 VMOVSD	(%R8,%RSI,8),%XMM12

  (1778) 0x4d3cfa VMAXSD	%XMM12,%XMM1,%XMM1

  (1778) 0x4d3cff VADDSD	%XMM12,%XMM0,%XMM0

  (1778) 0x4d3d04 LEA	0x2(%RAX),%RSI

  (1778) 0x4d3d08 MOV	(%R14,%RSI,8),%R9

  (1778) 0x4d3d0c CMP	(%R15,%R9,8),%RDI

  (1778) 0x4d3d10 JNE	4d3d22

  (1778) 0x4d3d12 VMOVSD	(%R8,%RSI,8),%XMM15

  (1778) 0x4d3d18 VMAXSD	%XMM15,%XMM1,%XMM1

  (1778) 0x4d3d1d VADDSD	%XMM15,%XMM0,%XMM0

  (1778) 0x4d3d22 LEA	0x3(%RAX),%RSI

  (1778) 0x4d3d26 MOV	(%R14,%RSI,8),%R9

  (1778) 0x4d3d2a CMP	(%R15,%R9,8),%RDI

  (1778) 0x4d3d2e JNE	4d3d40

  (1778) 0x4d3d30 VMOVSD	(%R8,%RSI,8),%XMM14

  (1778) 0x4d3d36 VMAXSD	%XMM14,%XMM1,%XMM1

  (1778) 0x4d3d3b VADDSD	%XMM14,%XMM0,%XMM0

  (1778) 0x4d3d40 LEA	0x4(%RAX),%RSI

  (1778) 0x4d3d44 MOV	(%R14,%RSI,8),%R9

  (1778) 0x4d3d48 CMP	(%R15,%R9,8),%RDI

  (1778) 0x4d3d4c JNE	4d3d5e

  (1778) 0x4d3d4e VMOVSD	(%R8,%RSI,8),%XMM13

  (1778) 0x4d3d54 VMAXSD	%XMM13,%XMM1,%XMM1

  (1778) 0x4d3d59 VADDSD	%XMM13,%XMM0,%XMM0

  (1778) 0x4d3d5e LEA	0x5(%RAX),%RSI

  (1778) 0x4d3d62 MOV	(%R14,%RSI,8),%R9

  (1778) 0x4d3d66 CMP	(%R15,%R9,8),%RDI

  (1778) 0x4d3d6a JNE	4d3d7a

  (1778) 0x4d3d6c VMOVSD	(%R8,%RSI,8),%XMM2

  (1778) 0x4d3d72 VMAXSD	%XMM2,%XMM1,%XMM1

  (1778) 0x4d3d76 VADDSD	%XMM2,%XMM0,%XMM0

  (1778) 0x4d3d7a LEA	0x6(%RAX),%RSI

  (1778) 0x4d3d7e MOV	(%R14,%RSI,8),%R9

  (1778) 0x4d3d82 CMP	(%R15,%R9,8),%RDI

  (1778) 0x4d3d86 JNE	4d3d98

  (1778) 0x4d3d88 VMOVSD	(%R8,%RSI,8),%XMM8

  (1778) 0x4d3d8e VMAXSD	%XMM8,%XMM1,%XMM1

  (1778) 0x4d3d93 VADDSD	%XMM8,%XMM0,%XMM0

  (1778) 0x4d3d98 LEA	0x7(%RAX),%RSI

  (1778) 0x4d3d9c MOV	-0x60(%RBP),%RAX

  (1778) 0x4d3da0 CMP	%RAX,%RSI

  (1778) 0x4d3da3 JNE	4d3cae

(1762) 0x4d3da9 MOV	-0x70(%RBP),%RDI

(1762) 0x4d3dad MOV	(%RCX),%R9

(1762) 0x4d3db0 MOV	(%RDI),%RAX

(1762) 0x4d3db3 MOV	%R9,-0x88(%RBP)

(1762) 0x4d3dba MOV	%RAX,-0xb0(%RBP)

(1762) 0x4d3dc1 CMP	%R9,%RAX

(1762) 0x4d3dc4 JGE	4d4019

(1762) 0x4d3dca SUB	%RAX,%R9

(1762) 0x4d3dcd MOV	(%R15,%RBX,8),%RDI

(1762) 0x4d3dd1 MOV	%RAX,%RSI

(1762) 0x4d3dd4 AND	$0x7,%R9D

(1762) 0x4d3dd8 JE	4d3efc

(1762) 0x4d3dde CMP	$0x1,%R9

(1762) 0x4d3de2 JE	4d3eca

(1762) 0x4d3de8 CMP	$0x2,%R9

(1762) 0x4d3dec JE	4d3ea8

(1762) 0x4d3df2 CMP	$0x3,%R9

(1762) 0x4d3df6 JE	4d3e86

(1762) 0x4d3dfc CMP	$0x4,%R9

(1762) 0x4d3e00 JE	4d3e64

(1762) 0x4d3e02 CMP	$0x5,%R9

(1762) 0x4d3e06 JE	4d3e4e

(1762) 0x4d3e08 CMP	$0x6,%R9

(1762) 0x4d3e0c JE	4d3e2c

(1762) 0x4d3e0e MOV	(%R13,%RAX,8),%RSI

(1762) 0x4d3e13 MOV	-0x78(%RBP),%RAX

(1762) 0x4d3e17 CMP	(%RAX,%RSI,8),%RDI

(1762) 0x4d3e1b JE	4d4602

(1762) 0x4d3e21 MOV	-0xb0(%RBP),%RSI

(1762) 0x4d3e28 LEA	0x1(%RSI),%RSI

(1762) 0x4d3e2c MOV	(%R13,%RSI,8),%R9

(1762) 0x4d3e31 MOV	-0x78(%RBP),%RAX

(1762) 0x4d3e35 CMP	(%RAX,%R9,8),%RDI

(1762) 0x4d3e39 JNE	4d3e4b

(1762) 0x4d3e3b VMOVSD	(%R11,%RSI,8),%XMM10

(1762) 0x4d3e41 VMAXSD	%XMM10,%XMM1,%XMM1

(1762) 0x4d3e46 VADDSD	%XMM10,%XMM0,%XMM0

(1762) 0x4d3e4b INC	%RSI

(1762) 0x4d3e4e MOV	(%R13,%RSI,8),%R9

(1762) 0x4d3e53 MOV	-0x78(%RBP),%RAX

(1762) 0x4d3e57 CMP	(%RAX,%R9,8),%RDI

(1762) 0x4d3e5b JE	4d4545

(1762) 0x4d3e61 INC	%RSI

(1762) 0x4d3e64 MOV	(%R13,%RSI,8),%R9

(1762) 0x4d3e69 MOV	-0x78(%RBP),%RAX

(1762) 0x4d3e6d CMP	(%RAX,%R9,8),%RDI

(1762) 0x4d3e71 JNE	4d3e83

(1762) 0x4d3e73 VMOVSD	(%R11,%RSI,8),%XMM12

(1762) 0x4d3e79 VMAXSD	%XMM12,%XMM1,%XMM1

(1762) 0x4d3e7e VADDSD	%XMM12,%XMM0,%XMM0

(1762) 0x4d3e83 INC	%RSI

(1762) 0x4d3e86 MOV	(%R13,%RSI,8),%R9

(1762) 0x4d3e8b MOV	-0x78(%RBP),%RAX

(1762) 0x4d3e8f CMP	(%RAX,%R9,8),%RDI

(1762) 0x4d3e93 JNE	4d3ea5

(1762) 0x4d3e95 VMOVSD	(%R11,%RSI,8),%XMM15

(1762) 0x4d3e9b VMAXSD	%XMM15,%XMM1,%XMM1

(1762) 0x4d3ea0 VADDSD	%XMM15,%XMM0,%XMM0

(1762) 0x4d3ea5 INC	%RSI

(1762) 0x4d3ea8 MOV	(%R13,%RSI,8),%R9

(1762) 0x4d3ead MOV	-0x78(%RBP),%RAX

(1762) 0x4d3eb1 CMP	(%RAX,%R9,8),%RDI

(1762) 0x4d3eb5 JNE	4d3ec7

(1762) 0x4d3eb7 VMOVSD	(%R11,%RSI,8),%XMM14

(1762) 0x4d3ebd VMAXSD	%XMM14,%XMM1,%XMM1

(1762) 0x4d3ec2 VADDSD	%XMM14,%XMM0,%XMM0

(1762) 0x4d3ec7 INC	%RSI

(1762) 0x4d3eca MOV	(%R13,%RSI,8),%R9

(1762) 0x4d3ecf MOV	-0x78(%RBP),%RAX

(1762) 0x4d3ed3 CMP	(%RAX,%R9,8),%RDI

(1762) 0x4d3ed7 JNE	4d3ee9

(1762) 0x4d3ed9 VMOVSD	(%R11,%RSI,8),%XMM13

(1762) 0x4d3edf VMAXSD	%XMM13,%XMM1,%XMM1

(1762) 0x4d3ee4 VADDSD	%XMM13,%XMM0,%XMM0

(1762) 0x4d3ee9 MOV	-0x88(%RBP),%R9

(1762) 0x4d3ef0 INC	%RSI

(1762) 0x4d3ef3 CMP	%R9,%RSI

(1762) 0x4d3ef6 JE	4d4019

(1762) 0x4d3efc MOV	-0x78(%RBP),%R9

(1762) 0x4d3f00 MOV	%R14,-0xd8(%RBP)

(1762) 0x4d3f07 MOV	%R12,%R14

  (1777) 0x4d3f0a MOV	(%R13,%RSI,8),%R12

  (1777) 0x4d3f0f CMP	(%R9,%R12,8),%RDI

  (1777) 0x4d3f13 JNE	4d3f23

  (1777) 0x4d3f15 VMOVSD	(%R11,%RSI,8),%XMM2

  (1777) 0x4d3f1b VMAXSD	%XMM2,%XMM1,%XMM1

  (1777) 0x4d3f1f VADDSD	%XMM2,%XMM0,%XMM0

  (1777) 0x4d3f23 INC	%RSI

  (1777) 0x4d3f26 MOV	(%R13,%RSI,8),%RAX

  (1777) 0x4d3f2b CMP	(%R9,%RAX,8),%RDI

  (1777) 0x4d3f2f JNE	4d3f41

  (1777) 0x4d3f31 VMOVSD	(%R11,%RSI,8),%XMM8

  (1777) 0x4d3f37 VMAXSD	%XMM8,%XMM1,%XMM1

  (1777) 0x4d3f3c VADDSD	%XMM8,%XMM0,%XMM0

  (1777) 0x4d3f41 LEA	0x1(%RSI),%R12

  (1777) 0x4d3f45 MOV	(%R13,%R12,8),%RAX

  (1777) 0x4d3f4a CMP	(%R9,%RAX,8),%RDI

  (1777) 0x4d3f4e JNE	4d3f60

  (1777) 0x4d3f50 VMOVSD	(%R11,%R12,8),%XMM9

  (1777) 0x4d3f56 VMAXSD	%XMM9,%XMM1,%XMM1

  (1777) 0x4d3f5b VADDSD	%XMM9,%XMM0,%XMM0

  (1777) 0x4d3f60 LEA	0x2(%RSI),%R12

  (1777) 0x4d3f64 MOV	(%R13,%R12,8),%RAX

  (1777) 0x4d3f69 CMP	(%R9,%RAX,8),%RDI

  (1777) 0x4d3f6d JNE	4d3f7f

  (1777) 0x4d3f6f VMOVSD	(%R11,%R12,8),%XMM10

  (1777) 0x4d3f75 VMAXSD	%XMM10,%XMM1,%XMM1

  (1777) 0x4d3f7a VADDSD	%XMM10,%XMM0,%XMM0

  (1777) 0x4d3f7f LEA	0x3(%RSI),%R12

  (1777) 0x4d3f83 MOV	(%R13,%R12,8),%RAX

  (1777) 0x4d3f88 CMP	(%R9,%RAX,8),%RDI

  (1777) 0x4d3f8c JNE	4d3f9e

  (1777) 0x4d3f8e VMOVSD	(%R11,%R12,8),%XMM11

  (1777) 0x4d3f94 VMAXSD	%XMM11,%XMM1,%XMM1

  (1777) 0x4d3f99 VADDSD	%XMM11,%XMM0,%XMM0

  (1777) 0x4d3f9e LEA	0x4(%RSI),%R12

  (1777) 0x4d3fa2 MOV	(%R13,%R12,8),%RAX

  (1777) 0x4d3fa7 CMP	(%R9,%RAX,8),%RDI

  (1777) 0x4d3fab JNE	4d3fbd

  (1777) 0x4d3fad VMOVSD	(%R11,%R12,8),%XMM12

  (1777) 0x4d3fb3 VMAXSD	%XMM12,%XMM1,%XMM1

  (1777) 0x4d3fb8 VADDSD	%XMM12,%XMM0,%XMM0

  (1777) 0x4d3fbd LEA	0x5(%RSI),%R12

  (1777) 0x4d3fc1 MOV	(%R13,%R12,8),%RAX

  (1777) 0x4d3fc6 CMP	(%R9,%RAX,8),%RDI

  (1777) 0x4d3fca JNE	4d3fdc

  (1777) 0x4d3fcc VMOVSD	(%R11,%R12,8),%XMM15

  (1777) 0x4d3fd2 VMAXSD	%XMM15,%XMM1,%XMM1

  (1777) 0x4d3fd7 VADDSD	%XMM15,%XMM0,%XMM0

  (1777) 0x4d3fdc LEA	0x6(%RSI),%R12

  (1777) 0x4d3fe0 MOV	(%R13,%R12,8),%RAX

  (1777) 0x4d3fe5 CMP	(%R9,%RAX,8),%RDI

  (1777) 0x4d3fe9 JNE	4d3ffb

  (1777) 0x4d3feb VMOVSD	(%R11,%R12,8),%XMM14

  (1777) 0x4d3ff1 VMAXSD	%XMM14,%XMM1,%XMM1

  (1777) 0x4d3ff6 VADDSD	%XMM14,%XMM0,%XMM0

  (1777) 0x4d3ffb MOV	-0x88(%RBP),%R12

  (1777) 0x4d4002 ADD	$0x7,%RSI

  (1777) 0x4d4006 CMP	%R12,%RSI

  (1777) 0x4d4009 JNE	4d3f0a

(1762) 0x4d400f MOV	%R14,%R12

(1762) 0x4d4012 MOV	-0xd8(%RBP),%R14

(1762) 0x4d4019 VANDPD	%XMM3,%XMM7,%XMM7

(1762) 0x4d401d VMULSD	%XMM5,%XMM7,%XMM13

(1762) 0x4d4021 MOV	-0x80(%RBP),%RDI

(1762) 0x4d4025 MOV	-0x88(%RBP),%R9

(1762) 0x4d402c MOV	-0xb0(%RBP),%RAX

(1762) 0x4d4033 MOVQ	$-0x1,(%R12,%RDI,8)

(1762) 0x4d403b SUB	%RAX,%R9

(1762) 0x4d403e MOV	-0x60(%RBP),%RSI

(1762) 0x4d4042 ADD	%R9,%R10

(1762) 0x4d4045 VANDPD	%XMM3,%XMM0,%XMM0

(1762) 0x4d4049 MOV	-0x58(%RBP),%R9

(1762) 0x4d404d SUB	%RDI,%RSI

(1762) 0x4d4050 VCOMISD	%XMM13,%XMM0

(1762) 0x4d4055 LEA	-0x1(%RDX,%RSI,1),%RDX

(1762) 0x4d405a MOV	-0x8(%R9),%RSI

(1762) 0x4d405e MOV	(%R9),%RDI

(1762) 0x4d4061 MOV	%RSI,-0x60(%RBP)

(1762) 0x4d4065 LEA	0x1(%RSI),%RSI

(1762) 0x4d4069 JBE	4d4078

(1762) 0x4d406b CMPB	$0,-0xb9(%RBP)

(1762) 0x4d4072 JNE	4d44b8

(1762) 0x4d4078 CMP	%RSI,%RDI

(1762) 0x4d407b JLE	4d40b4

(1762) 0x4d407d VMULSD	%XMM1,%XMM4,%XMM2

(1762) 0x4d4081 MOV	-0x58(%RBP),%RDI

(1762) 0x4d4085 NOPL	(%RAX)

  (1776) 0x4d4088 VCOMISD	(%R8,%RSI,8),%XMM2

  (1776) 0x4d408e JAE	4d409e

  (1776) 0x4d4090 MOV	(%R14,%RSI,8),%RAX

  (1776) 0x4d4094 MOV	(%R15,%RAX,8),%R9

  (1776) 0x4d4098 CMP	%R9,(%R15,%RBX,8)

  (1776) 0x4d409c JE	4d40a8

  (1776) 0x4d409e DEC	%RDX

  (1776) 0x4d40a1 MOV	$-0x1,%RAX

  (1776) 0x4d40a8 MOV	%RAX,(%R12,%RSI,8)

  (1776) 0x4d40ac INC	%RSI

  (1776) 0x4d40af CMP	%RSI,(%RDI)

  (1776) 0x4d40b2 JG	4d4088

(1762) 0x4d40b4 MOV	-0x70(%RBP),%RSI

(1762) 0x4d40b8 MOV	(%RSI),%RSI

(1762) 0x4d40bb CMP	(%RCX),%RSI

(1762) 0x4d40be JGE	4d3651

(1762) 0x4d40c4 VMULSD	%XMM1,%XMM4,%XMM1

(1762) 0x4d40c8 MOV	%RDX,-0x60(%RBP)

(1762) 0x4d40cc MOV	-0x68(%RBP),%RDI

(1762) 0x4d40d0 MOV	-0x78(%RBP),%R9

(1762) 0x4d40d4 NOPL	(%RAX)

  (1775) 0x4d40d8 VCOMISD	(%R11,%RSI,8),%XMM1

  (1775) 0x4d40de JAE	4d40ef

  (1775) 0x4d40e0 MOV	(%R13,%RSI,8),%RAX

  (1775) 0x4d40e5 MOV	(%R9,%RAX,8),%RDX

  (1775) 0x4d40e9 CMP	%RDX,(%R15,%RBX,8)

  (1775) 0x4d40ed JE	4d40f9

  (1775) 0x4d40ef DEC	%R10

  (1775) 0x4d40f2 MOV	$-0x1,%RAX

  (1775) 0x4d40f9 MOV	%RAX,(%RDI,%RSI,8)

  (1775) 0x4d40fd INC	%RSI

  (1775) 0x4d4100 CMP	%RSI,(%RCX)

  (1775) 0x4d4103 JG	4d40d8

(1762) 0x4d4105 MOV	-0x60(%RBP),%RDX

(1762) 0x4d4109 JMP	4d3651

0x4d410e XCHG	%AX,%AX

(1762) 0x4d4110 CMP	%R9,%RSI

(1762) 0x4d4113 JGE	4d461e

(1762) 0x4d4119 LEA	(%R8,%R9,8),%R9

(1762) 0x4d411d LEA	0x8(%R8,%RDI,1),%RAX

(1762) 0x4d4122 MOV	%R9,%RDI

(1762) 0x4d4125 SUB	%RAX,%RDI

(1762) 0x4d4128 SUB	$0x8,%RDI

(1762) 0x4d412c SHR	$0x3,%RDI

(1762) 0x4d4130 INC	%RDI

(1762) 0x4d4133 VMOVAPD	%XMM7,%XMM14

(1762) 0x4d4137 VXORPD	%XMM0,%XMM0,%XMM0

(1762) 0x4d413b AND	$0x7,%EDI

(1762) 0x4d413e JE	4d41db

(1762) 0x4d4144 CMP	$0x1,%RDI

(1762) 0x4d4148 JE	4d41c4

(1762) 0x4d414a CMP	$0x2,%RDI

(1762) 0x4d414e JE	4d41b4

(1762) 0x4d4150 CMP	$0x3,%RDI

(1762) 0x4d4154 JE	4d41a2

(1762) 0x4d4156 CMP	$0x4,%RDI

(1762) 0x4d415a JE	4d4190

(1762) 0x4d415c CMP	$0x5,%RDI

(1762) 0x4d4160 JE	4d417e

(1762) 0x4d4162 CMP	$0x6,%RDI

(1762) 0x4d4166 JNE	4d45c1

(1762) 0x4d416c VMOVSD	(%RAX),%XMM8

(1762) 0x4d4170 ADD	$0x8,%RAX

(1762) 0x4d4174 VMAXSD	%XMM8,%XMM0,%XMM0

(1762) 0x4d4179 VADDSD	%XMM8,%XMM14,%XMM14

(1762) 0x4d417e VMOVSD	(%RAX),%XMM9

(1762) 0x4d4182 ADD	$0x8,%RAX

(1762) 0x4d4186 VMAXSD	%XMM9,%XMM0,%XMM0

(1762) 0x4d418b VADDSD	%XMM9,%XMM14,%XMM14

(1762) 0x4d4190 VMOVSD	(%RAX),%XMM10

(1762) 0x4d4194 ADD	$0x8,%RAX

(1762) 0x4d4198 VMAXSD	%XMM10,%XMM0,%XMM0

(1762) 0x4d419d VADDSD	%XMM10,%XMM14,%XMM14

(1762) 0x4d41a2 VMOVSD	(%RAX),%XMM11

(1762) 0x4d41a6 ADD	$0x8,%RAX

(1762) 0x4d41aa VMAXSD	%XMM11,%XMM0,%XMM0

(1762) 0x4d41af VADDSD	%XMM11,%XMM14,%XMM14

(1762) 0x4d41b4 VMOVSD	(%RAX),%XMM2

(1762) 0x4d41b8 ADD	$0x8,%RAX

(1762) 0x4d41bc VMAXSD	%XMM2,%XMM0,%XMM0

(1762) 0x4d41c0 VADDSD	%XMM2,%XMM14,%XMM14

(1762) 0x4d41c4 VMOVSD	(%RAX),%XMM12

(1762) 0x4d41c8 ADD	$0x8,%RAX

(1762) 0x4d41cc VMAXSD	%XMM12,%XMM0,%XMM0

(1762) 0x4d41d1 VADDSD	%XMM12,%XMM14,%XMM14

(1762) 0x4d41d6 CMP	%RAX,%R9

(1762) 0x4d41d9 JE	4d4257

  (1769) 0x4d41db VMOVSD	(%RAX),%XMM15

  (1769) 0x4d41df VMOVSD	0x8(%RAX),%XMM8

  (1769) 0x4d41e4 VMAXSD	%XMM15,%XMM0,%XMM13

  (1769) 0x4d41e9 VADDSD	%XMM15,%XMM14,%XMM1

  (1769) 0x4d41ee VMOVSD	0x10(%RAX),%XMM11

  (1769) 0x4d41f3 VMAXSD	%XMM8,%XMM13,%XMM9

  (1769) 0x4d41f8 VADDSD	%XMM8,%XMM1,%XMM10

  (1769) 0x4d41fd VMOVSD	0x18(%RAX),%XMM2

  (1769) 0x4d4202 VMAXSD	%XMM11,%XMM9,%XMM12

  (1769) 0x4d4207 VADDSD	%XMM11,%XMM10,%XMM14

  (1769) 0x4d420c VMOVSD	0x20(%RAX),%XMM13

  (1769) 0x4d4211 VMAXSD	%XMM2,%XMM12,%XMM0

  (1769) 0x4d4215 VADDSD	%XMM2,%XMM14,%XMM15

  (1769) 0x4d4219 VMOVSD	0x28(%RAX),%XMM9

  (1769) 0x4d421e VMAXSD	%XMM13,%XMM0,%XMM8

  (1769) 0x4d4223 VADDSD	%XMM13,%XMM15,%XMM1

  (1769) 0x4d4228 VMOVSD	0x30(%RAX),%XMM12

  (1769) 0x4d422d VMAXSD	%XMM9,%XMM8,%XMM10

  (1769) 0x4d4232 VADDSD	%XMM9,%XMM1,%XMM11

  (1769) 0x4d4237 VMOVSD	0x38(%RAX),%XMM2

  (1769) 0x4d423c VMAXSD	%XMM12,%XMM10,%XMM14

  (1769) 0x4d4241 VADDSD	%XMM12,%XMM11,%XMM15

  (1769) 0x4d4246 ADD	$0x40,%RAX

  (1769) 0x4d424a VMAXSD	%XMM2,%XMM14,%XMM0

  (1769) 0x4d424e VADDSD	%XMM2,%XMM15,%XMM14

  (1769) 0x4d4252 CMP	%RAX,%R9

  (1769) 0x4d4255 JNE	4d41db

(1762) 0x4d4257 MOV	-0x70(%RBP),%RSI

(1762) 0x4d425b MOV	(%RCX),%R9

(1762) 0x4d425e MOV	(%RSI),%RAX

(1762) 0x4d4261 MOV	%RAX,-0x88(%RBP)

(1762) 0x4d4268 CMP	%R9,%RAX

(1762) 0x4d426b JGE	4d43a4

(1762) 0x4d4271 LEA	(%R11,%RAX,8),%RSI

(1762) 0x4d4275 LEA	(%R11,%R9,8),%RAX

(1762) 0x4d4279 MOV	%RAX,%RDI

(1762) 0x4d427c SUB	%RSI,%RDI

(1762) 0x4d427f SUB	$0x8,%RDI

(1762) 0x4d4283 SHR	$0x3,%RDI

(1762) 0x4d4287 INC	%RDI

(1762) 0x4d428a AND	$0x7,%EDI

(1762) 0x4d428d JE	4d432a

(1762) 0x4d4293 CMP	$0x1,%RDI

(1762) 0x4d4297 JE	4d4313

(1762) 0x4d4299 CMP	$0x2,%RDI

(1762) 0x4d429d JE	4d4301

(1762) 0x4d429f CMP	$0x3,%RDI

(1762) 0x4d42a3 JE	4d42ef

(1762) 0x4d42a5 CMP	$0x4,%RDI

(1762) 0x4d42a9 JE	4d42dd

(1762) 0x4d42ab CMP	$0x5,%RDI

(1762) 0x4d42af JE	4d42cd

(1762) 0x4d42b1 CMP	$0x6,%RDI

(1762) 0x4d42b5 JNE	4d45d6

(1762) 0x4d42bb VMOVSD	(%RSI),%XMM8

(1762) 0x4d42bf ADD	$0x8,%RSI

(1762) 0x4d42c3 VMAXSD	%XMM8,%XMM0,%XMM0

(1762) 0x4d42c8 VADDSD	%XMM8,%XMM14,%XMM14

(1762) 0x4d42cd VMOVSD	(%RSI),%XMM1

(1762) 0x4d42d1 ADD	$0x8,%RSI

(1762) 0x4d42d5 VMAXSD	%XMM1,%XMM0,%XMM0

(1762) 0x4d42d9 VADDSD	%XMM1,%XMM14,%XMM14

(1762) 0x4d42dd VMOVSD	(%RSI),%XMM9

(1762) 0x4d42e1 ADD	$0x8,%RSI

(1762) 0x4d42e5 VMAXSD	%XMM9,%XMM0,%XMM0

(1762) 0x4d42ea VADDSD	%XMM9,%XMM14,%XMM14

(1762) 0x4d42ef VMOVSD	(%RSI),%XMM10

(1762) 0x4d42f3 ADD	$0x8,%RSI

(1762) 0x4d42f7 VMAXSD	%XMM10,%XMM0,%XMM0

(1762) 0x4d42fc VADDSD	%XMM10,%XMM14,%XMM14

(1762) 0x4d4301 VMOVSD	(%RSI),%XMM11

(1762) 0x4d4305 ADD	$0x8,%RSI

(1762) 0x4d4309 VMAXSD	%XMM11,%XMM0,%XMM0

(1762) 0x4d430e VADDSD	%XMM11,%XMM14,%XMM14

(1762) 0x4d4313 VMOVSD	(%RSI),%XMM12

(1762) 0x4d4317 ADD	$0x8,%RSI

(1762) 0x4d431b VMAXSD	%XMM12,%XMM0,%XMM0

(1762) 0x4d4320 VADDSD	%XMM12,%XMM14,%XMM14

(1762) 0x4d4325 CMP	%RSI,%RAX

(1762) 0x4d4328 JE	4d43a4

  (1768) 0x4d432a VMOVSD	(%RSI),%XMM15

  (1768) 0x4d432e VMOVSD	0x8(%RSI),%XMM2

  (1768) 0x4d4333 VMAXSD	%XMM15,%XMM0,%XMM0

  (1768) 0x4d4338 VADDSD	%XMM15,%XMM14,%XMM14

  (1768) 0x4d433d VMOVSD	0x10(%RSI),%XMM1

  (1768) 0x4d4342 VMAXSD	%XMM2,%XMM0,%XMM13

  (1768) 0x4d4346 VADDSD	%XMM2,%XMM14,%XMM8

  (1768) 0x4d434a VMOVSD	0x18(%RSI),%XMM11

  (1768) 0x4d434f VMAXSD	%XMM1,%XMM13,%XMM9

  (1768) 0x4d4353 VADDSD	%XMM1,%XMM8,%XMM10

  (1768) 0x4d4357 VMOVSD	0x20(%RSI),%XMM14

  (1768) 0x4d435c VMAXSD	%XMM11,%XMM9,%XMM12

  (1768) 0x4d4361 VADDSD	%XMM11,%XMM10,%XMM15

  (1768) 0x4d4366 VMOVSD	0x28(%RSI),%XMM2

  (1768) 0x4d436b VMAXSD	%XMM14,%XMM12,%XMM0

  (1768) 0x4d4370 VADDSD	%XMM14,%XMM15,%XMM13

  (1768) 0x4d4375 VMOVSD	0x30(%RSI),%XMM9

  (1768) 0x4d437a VMAXSD	%XMM2,%XMM0,%XMM8

  (1768) 0x4d437e VADDSD	%XMM2,%XMM13,%XMM1

  (1768) 0x4d4382 VMOVSD	0x38(%RSI),%XMM12

  (1768) 0x4d4387 VMAXSD	%XMM9,%XMM8,%XMM10

  (1768) 0x4d438c VADDSD	%XMM9,%XMM1,%XMM11

  (1768) 0x4d4391 ADD	$0x40,%RSI

  (1768) 0x4d4395 VMAXSD	%XMM12,%XMM10,%XMM0

  (1768) 0x4d439a VADDSD	%XMM12,%XMM11,%XMM14

  (1768) 0x4d439f CMP	%RSI,%RAX

  (1768) 0x4d43a2 JNE	4d432a

(1762) 0x4d43a4 VANDPD	%XMM3,%XMM7,%XMM7

(1762) 0x4d43a8 VMULSD	%XMM5,%XMM7,%XMM15

(1762) 0x4d43ac MOV	-0x80(%RBP),%RAX

(1762) 0x4d43b0 MOV	-0x60(%RBP),%RSI

(1762) 0x4d43b4 MOV	-0x88(%RBP),%RDI

(1762) 0x4d43bb MOVQ	$-0x1,(%R12,%RAX,8)

(1762) 0x4d43c3 SUB	%RAX,%RSI

(1762) 0x4d43c6 SUB	%RDI,%R9

(1762) 0x4d43c9 MOV	-0x58(%RBP),%RAX

(1762) 0x4d43cd VANDPD	%XMM3,%XMM14,%XMM14

(1762) 0x4d43d1 ADD	%R9,%R10

(1762) 0x4d43d4 VCOMISD	%XMM15,%XMM14

(1762) 0x4d43d9 LEA	-0x1(%RDX,%RSI,1),%RDX

(1762) 0x4d43de MOV	-0x8(%RAX),%RSI

(1762) 0x4d43e2 MOV	(%RAX),%RDI

(1762) 0x4d43e5 MOV	%RSI,-0x60(%RBP)

(1762) 0x4d43e9 LEA	0x1(%RSI),%RSI

(1762) 0x4d43ed JBE	4d43fc

(1762) 0x4d43ef CMPB	$0,-0xb9(%RBP)

(1762) 0x4d43f6 JNE	4d44b8

(1762) 0x4d43fc CMP	%RSI,%RDI

(1762) 0x4d43ff JLE	4d443c

(1762) 0x4d4401 VMULSD	%XMM0,%XMM4,%XMM13

(1762) 0x4d4405 NOPW	%CS:(%RAX,%RAX,1)

(1762) 0x4d4410 NOPW	%CS:(%RAX,%RAX,1)

(1762) 0x4d441b NOPL	(%RAX,%RAX,1)

  (1765) 0x4d4420 VCOMISD	(%R8,%RSI,8),%XMM13

  (1765) 0x4d4426 JAE	4d4498

  (1765) 0x4d4428 MOV	(%R14,%RSI,8),%R9

  (1765) 0x4d442c MOV	-0x58(%RBP),%RDI

  (1765) 0x4d4430 MOV	%R9,(%R12,%RSI,8)

  (1765) 0x4d4434 INC	%RSI

  (1765) 0x4d4437 CMP	%RSI,(%RDI)

  (1765) 0x4d443a JG	4d4420

(1762) 0x4d443c MOV	-0x70(%RBP),%RSI

(1762) 0x4d4440 MOV	(%RSI),%R9

(1762) 0x4d4443 CMP	(%RCX),%R9

(1762) 0x4d4446 JGE	4d3651

(1762) 0x4d444c VMULSD	%XMM0,%XMM4,%XMM0

  (1763) 0x4d4450 VCOMISD	(%R11,%R9,8),%XMM0

  (1763) 0x4d4456 JAE	4d4479

  (1764) 0x4d4458 MOV	(%R13,%R9,8),%RAX

  (1764) 0x4d445d MOV	-0x68(%RBP),%RDI

  (1764) 0x4d4461 MOV	%RAX,(%RDI,%R9,8)

  (1764) 0x4d4465 INC	%R9

  (1764) 0x4d4468 CMP	%R9,(%RCX)

  (1764) 0x4d446b JLE	4d3651

  (1764) 0x4d4471 VCOMISD	(%R11,%R9,8),%XMM0

  (1764) 0x4d4477 JB	4d4458

  (1763) 0x4d4479 MOV	-0x68(%RBP),%RSI

  (1763) 0x4d447d DEC	%R10

  (1763) 0x4d4480 MOVQ	$-0x1,(%RSI,%R9,8)

  (1763) 0x4d4488 INC	%R9

  (1763) 0x4d448b CMP	%R9,(%RCX)

  (1763) 0x4d448e JG	4d4450

(1762) 0x4d4490 JMP	4d3651

0x4d4495 NOPL	(%RAX)

  (1765) 0x4d4498 MOVQ	$-0x1,(%R12,%RSI,8)

  (1765) 0x4d44a0 MOV	-0x58(%RBP),%RAX

  (1765) 0x4d44a4 INC	%RSI

  (1765) 0x4d44a7 DEC	%RDX

  (1765) 0x4d44aa CMP	%RSI,(%RAX)

  (1765) 0x4d44ad JG	4d4420

(1762) 0x4d44b3 JMP	4d443c

0x4d44b5 NOPL	(%RAX)

(1762) 0x4d44b8 MOV	-0x58(%RBP),%RAX

(1762) 0x4d44bc CMP	%RDI,%RSI

(1762) 0x4d44bf JGE	4d4503

(1762) 0x4d44c1 NOPW	%CS:(%RAX,%RAX,1)

(1762) 0x4d44cc NOPW	%CS:(%RAX,%RAX,1)

(1762) 0x4d44d7 NOPW	(%RAX,%RAX,1)

  (1767) 0x4d44e0 MOVQ	$-0x1,(%R12,%RSI,8)

  (1767) 0x4d44e8 INC	%RSI

  (1767) 0x4d44eb MOV	(%RAX),%RDI

  (1767) 0x4d44ee CMP	%RSI,%RDI

  (1767) 0x4d44f1 JG	4d44e0

(1762) 0x4d44f3 MOV	-0x58(%RBP),%R9

(1762) 0x4d44f7 MOV	-0x8(%R9),%RSI

(1762) 0x4d44fb MOV	%RSI,-0x60(%RBP)

(1762) 0x4d44ff LEA	0x1(%RSI),%RSI

(1762) 0x4d4503 SUB	%RSI,%RDI

(1762) 0x4d4506 SUB	%RDI,%RDX

(1762) 0x4d4509 MOV	-0x70(%RBP),%RDI

(1762) 0x4d450d MOV	(%RCX),%R9

(1762) 0x4d4510 MOV	(%RDI),%RDI

(1762) 0x4d4513 MOV	-0x68(%RBP),%RAX

(1762) 0x4d4517 CMP	%R9,%RDI

(1762) 0x4d451a JGE	4d453a

(1762) 0x4d451c NOPL	(%RAX)

  (1766) 0x4d4520 MOVQ	$-0x1,(%RAX,%RDI,8)

  (1766) 0x4d4528 INC	%RDI

  (1766) 0x4d452b MOV	(%RCX),%R9

  (1766) 0x4d452e CMP	%RDI,%R9

  (1766) 0x4d4531 JG	4d4520

(1762) 0x4d4533 MOV	-0x70(%RBP),%RSI

(1762) 0x4d4537 MOV	(%RSI),%RDI

(1762) 0x4d453a SUB	%RDI,%R9

(1762) 0x4d453d SUB	%R9,%R10

(1762) 0x4d4540 JMP	4d3651

(1762) 0x4d4545 VMOVSD	(%R11,%RSI,8),%XMM11

(1762) 0x4d454b VMAXSD	%XMM11,%XMM1,%XMM1

(1762) 0x4d4550 VADDSD	%XMM11,%XMM0,%XMM0

(1762) 0x4d4555 JMP	4d3e61

(1762) 0x4d455a VMOVSD	(%R8,%RSI,8),%XMM14

(1762) 0x4d4560 VMAXSD	%XMM14,%XMM1,%XMM1

(1762) 0x4d4565 VADDSD	%XMM14,%XMM0,%XMM0

(1762) 0x4d456a JMP	4d3c2c

(1762) 0x4d456f VMOVSD	(%R11,%RSI,8),%XMM14

(1762) 0x4d4575 VMINSD	%XMM14,%XMM0,%XMM0

(1762) 0x4d457a VADDSD	%XMM14,%XMM1,%XMM1

(1762) 0x4d457f JMP	4d3378

(1762) 0x4d4584 VMOVSD	(%R8,%RSI,8),%XMM8

(1762) 0x4d458a VMINSD	%XMM8,%XMM0,%XMM0

(1762) 0x4d458f VADDSD	%XMM8,%XMM1,%XMM1

(1762) 0x4d4594 JMP	4d3126

(1762) 0x4d4599 VMOVAPD	%XMM7,%XMM1

(1762) 0x4d459d VXORPD	%XMM0,%XMM0,%XMM0

(1762) 0x4d45a1 JMP	4d32c2

(1762) 0x4d45a6 VMOVAPD	%XMM7,%XMM0

(1762) 0x4d45aa VXORPD	%XMM1,%XMM1,%XMM1

(1762) 0x4d45ae JMP	4d3da9

(1762) 0x4d45b3 VMOVAPD	%XMM7,%XMM14

(1762) 0x4d45b7 VXORPD	%XMM13,%XMM13,%XMM13

(1762) 0x4d45bc JMP	4d3930

(1762) 0x4d45c1 VMOVSD	(%RAX),%XMM1

(1762) 0x4d45c5 ADD	$0x8,%RAX

(1762) 0x4d45c9 VMAXSD	%XMM1,%XMM0,%XMM0

(1762) 0x4d45cd VADDSD	%XMM1,%XMM7,%XMM14

(1762) 0x4d45d1 JMP	4d416c

(1762) 0x4d45d6 VMOVSD	(%RSI),%XMM13

(1762) 0x4d45da ADD	$0x8,%RSI

(1762) 0x4d45de VMAXSD	%XMM13,%XMM0,%XMM0

(1762) 0x4d45e3 VADDSD	%XMM13,%XMM14,%XMM14

(1762) 0x4d45e8 JMP	4d42bb

(1762) 0x4d45ed VMOVSD	(%R8,%RSI,8),%XMM12

(1762) 0x4d45f3 VMAXSD	%XMM12,%XMM1,%XMM1

(1762) 0x4d45f8 VADDSD	%XMM12,%XMM7,%XMM0

(1762) 0x4d45fd JMP	4d3bfe

(1762) 0x4d4602 MOV	-0xb0(%RBP),%R9

(1762) 0x4d4609 VMOVSD	(%R11,%R9,8),%XMM9

(1762) 0x4d460f VMAXSD	%XMM9,%XMM1,%XMM1

(1762) 0x4d4614 VADDSD	%XMM9,%XMM0,%XMM0

(1762) 0x4d4619 JMP	4d3e21

(1762) 0x4d461e VMOVAPD	%XMM7,%XMM14

(1762) 0x4d4622 VXORPD	%XMM0,%XMM0,%XMM0

(1762) 0x4d4626 JMP	4d4257

0x4d462b NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○97.76	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.24	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	par_strength.c:246-513
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:246-283,289-302,309-355,363-369,376-382,392-398,405-411,424-445,451-472,480,492-513.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.17 to 2.33 cycles (9.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 22.17 to 1.88 cycles (11.79x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_GetSimpleThreadPartition: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:250
hypre_prefix_sum_pair: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:480

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

SETA: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:342

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 360 bytes (45 double precision FP elements). The binary function is storing 201 bytes (25 double precision FP elements).

General properties

nb instructions	129
nb uops	133
loop length	593
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	22

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.17 cycles
front end	22.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.50	3.40	17.33	17.33	17.00	3.40	3.50	17.00	17.00	17.00	3.20	17.33
cycles	3.50	3.40	17.33	17.33	17.00	3.40	3.50	17.00	17.00	17.00	3.20	17.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	22.17
Dispatch	17.33
Overall L1	22.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	11%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	12%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.17 cycles. At this rate:

8% of peak load performance is reached (16.24 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.07 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 22.17 to 17.33 cycles (1.28x speedup).

ASM code

In the binary file, the address of the function is: 4d2ed0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xd8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x68(%RDI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x80(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RDI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x60(%RDI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x58(%RDI),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RDI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x98(%RDI),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x90(%RDI),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x48(%RDI),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x40(%RDI),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RDI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RDI),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x8(%RDI),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RDI),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x28(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RDI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA -0x48(%RBP),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x50(%RBP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM5,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM4,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 5550a0 <hypre_GetSimpleThreadPartition>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV -0x58(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x60(%RBP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD -0x68(%RBP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x70(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x80(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JGE 4d3688 <hypre_BoomerAMGCreateS._omp_fn.1+0x7b8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD 0x87728(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xc8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VCOMISD %XMM5,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (,%RDI,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RCX,%R10,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xd0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SETAB -0xb9(%RBP)	3	1	0	0	0	0.50	0	1	0.50	0.50	0.50	0	0	1-2	1	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R10,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVQ 0x87e21(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RDX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R10,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM6,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x100(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xb8(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x90(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (,%RSI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xe8(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%R15,%RSI,1),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R14,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x40(%RBP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 5564d0 <hypre_prefix_sum_pair>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x50(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4d37b5 <hypre_BoomerAMGCreateS._omp_fn.1+0x8e5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x90(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%R11	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV -0xd0(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xc8(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RCX,%RDX,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RCX,%R11,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R11,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x8,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R11,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R11,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x40(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x38(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xf8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf0(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0xd8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	par_strength.c:246-513
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.17 to 2.33 cycles (9.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_GetSimpleThreadPartition: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:250
hypre_prefix_sum_pair: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:480

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

SETA: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:342

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

General properties

nb instructions	129
nb uops	133
loop length	593
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	22

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.17 cycles
front end	22.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.50	3.40	17.33	17.33	17.00	3.40	3.50	17.00	17.00	17.00	3.20	17.33
cycles	3.50	3.40	17.33	17.33	17.00	3.40	3.50	17.00	17.00	17.00	3.20	17.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	22.17
Dispatch	17.33
Overall L1	22.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	11%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	12%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.17 cycles. At this rate:

8% of peak load performance is reached (16.24 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.07 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4d2ed0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xd8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x68(%RDI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x80(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RDI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x60(%RDI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x58(%RDI),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RDI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x98(%RDI),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x90(%RDI),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x48(%RDI),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x40(%RDI),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RDI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RDI),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x8(%RDI),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD (%RDI),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x28(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RDI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA -0x48(%RBP),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x50(%RBP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM5,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM4,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 5550a0 <hypre_GetSimpleThreadPartition>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x48(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x50(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV -0x58(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x60(%RBP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD -0x68(%RBP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x70(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x80(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JGE 4d3688 <hypre_BoomerAMGCreateS._omp_fn.1+0x7b8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD 0x87728(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xc8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VCOMISD %XMM5,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
LEA (,%RDI,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RCX,%R10,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xd0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SETAB -0xb9(%RBP)	3	1	0	0	0	0.50	0	1	0.50	0.50	0.50	0	0	1-2	1	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R10,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVQ 0x87e21(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RDX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R10,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM6,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x100(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xb8(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x90(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (,%RSI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0xe8(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%R15,%RSI,1),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x38(%RBP),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R14,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x40(%RBP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 5564d0 <hypre_prefix_sum_pair>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x50(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %RDX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 4d37b5 <hypre_BoomerAMGCreateS._omp_fn.1+0x8e5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x90(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%R11	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV -0xd0(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xc8(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RCX,%RDX,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RCX,%R11,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R11,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD $0x8,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R11,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R11,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x40(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x38(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xf8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf0(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0xd8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCreateS._omp_fn.1–	1.59	0.69
▼Loop 1762 - par_strength.c:253-472 - exec–	0.14	0.05
○Loop 1772 - par_strength.c:451-460 - exec	0.39	0.15
○Loop 1774 - par_strength.c:324-327 - exec	0.39	0.15
○Loop 1771 - par_strength.c:463-472 - exec	0.00	0.00
○Loop 1773 - par_strength.c:329-332 - exec	0.00	0.00
○Loop 1770 - par_strength.c:463-468 - exec	0.00	0.00
○Loop 1769 - par_strength.c:311-314 - exec	0.00	0.00
○Loop 1764 - par_strength.c:436-445 - exec	0.00	0.00
○Loop 1776 - par_strength.c:363-369 - exec	0.00	0.00
○Loop 1779 - par_strength.c:405-411 - exec	0.00	0.00
○Loop 1767 - par_strength.c:345-347 - exec	0.00	0.00
○Loop 1766 - par_strength.c:351-353 - exec	0.00	0.00
○Loop 1775 - par_strength.c:376-382 - exec	0.00	0.00
○Loop 1763 - par_strength.c:436-441 - exec	0.00	0.00
○Loop 1777 - par_strength.c:278-283 - exec	0.00	0.00
○Loop 1768 - par_strength.c:316-319 - exec	0.00	0.00
○Loop 1780 - par_strength.c:392-398 - exec	0.00	0.00
○Loop 1782 - par_strength.c:289-294 - exec	0.00	0.00
○Loop 1778 - par_strength.c:270-275 - exec	0.00	0.00
○Loop 1781 - par_strength.c:297-302 - exec	0.00	0.00
○Loop 1765 - par_strength.c:424-433 - exec	0.00	0.00
▼Loop 1759 - par_strength.c:492-513 - exec–	0.06	0.02
○Loop 1761 - par_strength.c:498-503 - exec	0.60	0.23
○Loop 1760 - par_strength.c:508-513 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code