OV - exec - Function hypre_BoomerAMGBuildMultipass._omp

	Function: hypre_BoomerAMGBuildMultipass._omp_fn.9	Module: exec	Source: par_multi_interp.c:1575-1663 [...]	Coverage (incl. loops): 0.44% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663

--------------------------------------------------------------------------------

1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa)

[...]

1584:            tmp_marker = NULL;

1585:            if (n_fine)

1586:            {   tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1587:            tmp_marker_offd = NULL;

1588:            if (num_cols_offd)

1589:            {   tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1590:            for (i=0; i < n_fine; i++)

1591:            {   tmp_marker[i] = -1; }

1592:            for (i=0; i < num_cols_offd; i++)

1593:            {   tmp_marker_offd[i] = -1; }

1594:

1595:            /* Compute this thread's range of pass_length */

1596:            my_thread_num = hypre_GetThreadNum();

1597:            num_threads = hypre_NumActiveThreads();

1598:            thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num;

1599:            if (my_thread_num == num_threads-1)

1600:            {  thread_stop = pass_pointer[1] + pass_length; }

1601:            else

1602:            {  thread_stop = pass_pointer[1] + (pass_length/num_threads)*(my_thread_num+1); }

1603:

1604:            /* determine P for points of pass 1, i.e. neighbors of coarse points */

1605:            for (i=thread_start; i < thread_stop; i++)

1606:            {

1607:              i1 = pass_array[i];

1608:              sum_C = 0;

1609:              sum_N = 0;

1610:              j_start = P_diag_start[i1];

1611:              j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1612:              for (j=j_start; j < j_end; j++)

1613:              {

1614:                 k1 = P_diag_pass[1][j];

1615:                 tmp_marker[C_array[k1]] = i1;

1616:              }

1617:              cnt = P_diag_i[i1];

1618:              for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1619:              {

1620:                 j1 = A_diag_j[j];

1621:                 if (CF_marker[j1] != -3 &&

1622:                    (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1623:                    sum_N += A_diag_data[j];

1624:                 if (j1 != -1 && tmp_marker[j1] == i1)

1625:                 {

1626:                    P_diag_data[cnt] = A_diag_data[j];

1627:                    P_diag_j[cnt++] = fine_to_coarse[j1];

1628:                    sum_C += A_diag_data[j];

1629:                 }

1630:              }

1631:              j_start = P_offd_start[i1];

1632:              j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1633:              for (j=j_start; j < j_end; j++)

1634:              {

1635:                 k1 = P_offd_pass[1][j];

1636:                 tmp_marker_offd[C_array_offd[k1]] = i1;

1637:              }

1638:              cnt_offd = P_offd_i[i1];

1639:              for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1640:              {

1641:                 if (col_offd_S_to_A)

1642:                     j1 = map_A_to_S[A_offd_j[j]];

1643:                 else

1644:                     j1 = A_offd_j[j];

1645:                 if (CF_marker_offd[j1] != -3 &&

1646:                   (num_functions == 1 || dof_func[i1] == dof_func_offd[j1]))

1647:                     sum_N += A_offd_data[j];

1648:                 if (j1 != -1 && tmp_marker_offd[j1] == i1)

1649:                 {

1650:                    P_offd_data[cnt_offd] = A_offd_data[j];

1651:                    P_offd_j[cnt_offd++] = map_S_to_new[j1];

1652:                    sum_C += A_offd_data[j];

1653:                 }

1654:              }

1655:              diagonal = A_diag_data[A_diag_i[i1]];

1656:              if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1657:              for (j=P_diag_i[i1]; j < cnt; j++)

1658:                 P_diag_data[j] *= alfa;

1659:              for (j=P_offd_i[i1]; j < cnt_offd; j++)

1660:                 P_offd_data[j] *= alfa;

1661:           }

1662:           hypre_TFree(tmp_marker);

1663:           hypre_TFree(tmp_marker_offd);

0x467b70 PUSH	%RBP

0x467b71 MOV	%RSP,%RBP

0x467b74 PUSH	%R15

0x467b76 PUSH	%R14

0x467b78 PUSH	%R13

0x467b7a PUSH	%R12

0x467b7c PUSH	%RBX

0x467b7d SUB	$0xf8,%RSP

0x467b84 MOV	0xf8(%RDI),%RAX

0x467b8b MOV	0xf0(%RDI),%RDX

0x467b92 MOV	0xe0(%RDI),%RCX

0x467b99 MOV	0xd8(%RDI),%RSI

0x467ba0 MOV	0xd0(%RDI),%R8

0x467ba7 MOV	0xc8(%RDI),%R9

0x467bae MOV	0xc0(%RDI),%R10

0x467bb5 MOV	0xb8(%RDI),%R11

0x467bbc MOV	0xb0(%RDI),%R12

0x467bc3 MOV	%RAX,-0x50(%RBP)

0x467bc7 MOV	%RDX,-0x98(%RBP)

0x467bce MOV	%RCX,-0x120(%RBP)

0x467bd5 MOV	%RSI,-0xa0(%RBP)

0x467bdc MOV	%R8,-0x100(%RBP)

0x467be3 MOV	%R9,-0x108(%RBP)

0x467bea MOV	%R10,-0xc8(%RBP)

0x467bf1 MOV	%R11,-0xd0(%RBP)

0x467bf8 MOV	0xe8(%RDI),%RBX

0x467bff MOV	%R12,-0x58(%RBP)

0x467c03 MOV	0x90(%RDI),%RAX

0x467c0a MOV	0x80(%RDI),%RDX

0x467c11 MOV	0x78(%RDI),%RCX

0x467c15 MOV	0x70(%RDI),%RSI

0x467c19 MOV	0x68(%RDI),%R8

0x467c1d MOV	0xa8(%RDI),%R13

0x467c24 MOV	0x58(%RDI),%R11

0x467c28 MOV	0x60(%RDI),%R9

0x467c2c MOV	%RAX,-0x68(%RBP)

0x467c30 MOV	%RDX,-0xa8(%RBP)

0x467c37 MOV	0x40(%RDI),%RAX

0x467c3b MOV	0x38(%RDI),%RDX

0x467c3f MOV	%RCX,-0xd8(%RBP)

0x467c46 MOV	%RSI,-0x78(%RBP)

0x467c4a MOV	0x28(%RDI),%RCX

0x467c4e MOV	0x20(%RDI),%RSI

0x467c52 MOV	%R8,-0xb0(%RBP)

0x467c59 MOV	0x18(%RDI),%R8

0x467c5d MOV	%R13,-0xc0(%RBP)

0x467c64 MOV	%R11,-0x80(%RBP)

0x467c68 MOV	%RAX,-0xe8(%RBP)

0x467c6f MOV	0xa0(%RDI),%R14

0x467c76 MOV	0x98(%RDI),%R15

0x467c7d MOV	0x88(%RDI),%R10

0x467c84 MOV	0x50(%RDI),%R12

0x467c88 MOV	0x48(%RDI),%R13

0x467c8c MOV	0x30(%RDI),%R11

0x467c90 MOV	%R9,-0xe0(%RBP)

0x467c97 MOV	%RDX,-0x48(%RBP)

0x467c9b MOV	%RCX,-0xf0(%RBP)

0x467ca2 MOV	%RSI,-0x38(%RBP)

0x467ca6 MOV	%R8,-0x110(%RBP)

0x467cad MOV	0x10(%RDI),%R9

0x467cb1 MOV	0x8(%RDI),%RAX

0x467cb5 MOV	(%RDI),%RDI

0x467cb8 MOV	%R9,-0x60(%RBP)

0x467cbc MOV	%RAX,-0x40(%RBP)

0x467cc0 MOV	%RDI,-0x118(%RBP)

0x467cc7 TEST	%RBX,%RBX

0x467cca JNE	46872c

0x467cd0 TEST	%R12,%R12

0x467cd3 JNE	468236

0x467cd9 XOR	%EBX,%EBX

0x467cdb XOR	%R12D,%R12D

0x467cde MOV	%R11,-0xb8(%RBP)

0x467ce5 MOV	%R10,-0x90(%RBP)

0x467cec VMOVSD	%XMM0,-0x88(%RBP)

0x467cf4 CALL	555090 <hypre_GetThreadNum>

0x467cf9 MOV	%RAX,-0x70(%RBP)

0x467cfd CALL	555080 <hypre_NumActiveThreads>

0x467d02 MOV	%RAX,%RSI

0x467d05 MOV	-0x50(%RBP),%RAX

0x467d09 MOV	-0x70(%RBP),%R10

0x467d0d CQTO

0x467d0f IDIV	%RSI

0x467d12 MOV	-0x58(%RBP),%R8

0x467d16 MOV	-0x50(%RBP),%RCX

0x467d1a MOV	0x8(%R8),%R9

0x467d1e VMOVSD	-0x88(%RBP),%XMM0

0x467d26 MOV	%R10,%R11

0x467d29 DEC	%RSI

0x467d2c ADD	%R9,%RCX

0x467d2f IMUL	%RAX,%R11

0x467d33 ADD	%R11,%RAX

0x467d36 ADD	%R9,%RAX

0x467d39 CMP	%RSI,%R10

0x467d3c CMOVNE	%RAX,%RCX

0x467d40 LEA	(%R9,%R11,1),%RDI

0x467d44 CMP	%RDI,%RCX

0x467d47 MOV	-0x90(%RBP),%R10

0x467d4e MOV	-0xb8(%RBP),%R11

0x467d55 JLE	46855d

0x467d5b MOV	-0xc0(%RBP),%R8

0x467d62 VMOVQ	0xf2e06(%RIP),%XMM5

0x467d6a LEA	(%R8,%RDI,8),%RSI

0x467d6e LEA	(%R8,%RCX,8),%R9

0x467d72 MOV	%RSI,-0x58(%RBP)

0x467d76 MOV	%R9,-0xf8(%RBP)

0x467d7d VXORPD	%XMM4,%XMM4,%XMM4

0x467d81 NOPL	(%RAX)

(621) 0x467d88 MOV	-0x58(%RBP),%RAX

(621) 0x467d8c MOV	-0xe0(%RBP),%R9

(621) 0x467d93 MOV	(%RAX),%RDX

(621) 0x467d96 MOV	-0xd0(%RBP),%RDI

(621) 0x467d9d LEA	(,%RDX,8),%RSI

(621) 0x467da5 LEA	(%R9,%RSI,1),%RAX

(621) 0x467da9 LEA	0x8(%RSI),%R8

(621) 0x467dad MOV	(%RDI,%RDX,8),%RCX

(621) 0x467db1 MOV	0x8(%R9,%RSI,1),%R9

(621) 0x467db6 MOV	%R8,-0x50(%RBP)

(621) 0x467dba MOV	(%RAX),%R8

(621) 0x467dbd ADD	%RCX,%R9

(621) 0x467dc0 SUB	%R8,%R9

(621) 0x467dc3 MOV	%RAX,-0x70(%RBP)

(621) 0x467dc7 CMP	%R9,%RCX

(621) 0x467dca JGE	467f06

(621) 0x467dd0 MOV	-0x108(%RBP),%RDI

(621) 0x467dd7 MOV	0x8(%RDI),%R8

(621) 0x467ddb LEA	(%R8,%R9,8),%RDI

(621) 0x467ddf LEA	(%R8,%RCX,8),%RCX

(621) 0x467de3 MOV	%RDI,%RAX

(621) 0x467de6 SUB	%RCX,%RAX

(621) 0x467de9 SUB	$0x8,%RAX

(621) 0x467ded SHR	$0x3,%RAX

(621) 0x467df1 INC	%RAX

(621) 0x467df4 AND	$0x7,%EAX

(621) 0x467df7 JE	467e8f

(621) 0x467dfd CMP	$0x1,%RAX

(621) 0x467e01 JE	467e7b

(621) 0x467e03 CMP	$0x2,%RAX

(621) 0x467e07 JE	467e6c

(621) 0x467e09 CMP	$0x3,%RAX

(621) 0x467e0d JE	467e5d

(621) 0x467e0f CMP	$0x4,%RAX

(621) 0x467e13 JE	467e4e

(621) 0x467e15 CMP	$0x5,%RAX

(621) 0x467e19 JE	467e3f

(621) 0x467e1b CMP	$0x6,%RAX

(621) 0x467e1f JE	467e30

(621) 0x467e21 MOV	(%RCX),%R9

(621) 0x467e24 ADD	$0x8,%RCX

(621) 0x467e28 MOV	(%R15,%R9,8),%R8

(621) 0x467e2c MOV	%RDX,(%R12,%R8,8)

(621) 0x467e30 MOV	(%RCX),%RAX

(621) 0x467e33 ADD	$0x8,%RCX

(621) 0x467e37 MOV	(%R15,%RAX,8),%R9

(621) 0x467e3b MOV	%RDX,(%R12,%R9,8)

(621) 0x467e3f MOV	(%RCX),%R8

(621) 0x467e42 ADD	$0x8,%RCX

(621) 0x467e46 MOV	(%R15,%R8,8),%RAX

(621) 0x467e4a MOV	%RDX,(%R12,%RAX,8)

(621) 0x467e4e MOV	(%RCX),%R9

(621) 0x467e51 ADD	$0x8,%RCX

(621) 0x467e55 MOV	(%R15,%R9,8),%R8

(621) 0x467e59 MOV	%RDX,(%R12,%R8,8)

(621) 0x467e5d MOV	(%RCX),%RAX

(621) 0x467e60 ADD	$0x8,%RCX

(621) 0x467e64 MOV	(%R15,%RAX,8),%R9

(621) 0x467e68 MOV	%RDX,(%R12,%R9,8)

(621) 0x467e6c MOV	(%RCX),%R8

(621) 0x467e6f ADD	$0x8,%RCX

(621) 0x467e73 MOV	(%R15,%R8,8),%RAX

(621) 0x467e77 MOV	%RDX,(%R12,%RAX,8)

(621) 0x467e7b MOV	(%RCX),%R9

(621) 0x467e7e ADD	$0x8,%RCX

(621) 0x467e82 MOV	(%R15,%R9,8),%R8

(621) 0x467e86 MOV	%RDX,(%R12,%R8,8)

(621) 0x467e8a CMP	%RCX,%RDI

(621) 0x467e8d JE	467eff

(621) 0x467e8f MOV	-0x50(%RBP),%R9

  (630) 0x467e93 MOV	(%RCX),%RAX

  (630) 0x467e96 ADD	$0x40,%RCX

  (630) 0x467e9a MOV	(%R15,%RAX,8),%R8

  (630) 0x467e9e MOV	%RDX,(%R12,%R8,8)

  (630) 0x467ea2 MOV	-0x38(%RCX),%RAX

  (630) 0x467ea6 MOV	(%R15,%RAX,8),%R8

  (630) 0x467eaa MOV	%RDX,(%R12,%R8,8)

  (630) 0x467eae MOV	-0x30(%RCX),%RAX

  (630) 0x467eb2 MOV	(%R15,%RAX,8),%R8

  (630) 0x467eb6 MOV	%RDX,(%R12,%R8,8)

  (630) 0x467eba MOV	-0x28(%RCX),%RAX

  (630) 0x467ebe MOV	(%R15,%RAX,8),%R8

  (630) 0x467ec2 MOV	%RDX,(%R12,%R8,8)

  (630) 0x467ec6 MOV	-0x20(%RCX),%RAX

  (630) 0x467eca MOV	(%R15,%RAX,8),%R8

  (630) 0x467ece MOV	%RDX,(%R12,%R8,8)

  (630) 0x467ed2 MOV	-0x18(%RCX),%RAX

  (630) 0x467ed6 MOV	(%R15,%RAX,8),%R8

  (630) 0x467eda MOV	%RDX,(%R12,%R8,8)

  (630) 0x467ede MOV	-0x10(%RCX),%RAX

  (630) 0x467ee2 MOV	(%R15,%RAX,8),%R8

  (630) 0x467ee6 MOV	%RDX,(%R12,%R8,8)

  (630) 0x467eea MOV	-0x8(%RCX),%RAX

  (630) 0x467eee MOV	(%R15,%RAX,8),%R8

  (630) 0x467ef2 MOV	%RDX,(%R12,%R8,8)

  (630) 0x467ef6 CMP	%RCX,%RDI

  (630) 0x467ef9 JNE	467e93

(621) 0x467efb MOV	%R9,-0x50(%RBP)

(621) 0x467eff MOV	-0x70(%RBP),%RCX

(621) 0x467f03 MOV	(%RCX),%R8

(621) 0x467f06 MOV	-0xf0(%RBP),%RDI

(621) 0x467f0d MOV	-0x50(%RBP),%RCX

(621) 0x467f11 LEA	(%RDI,%RSI,1),%R9

(621) 0x467f15 MOV	(%R9),%RAX

(621) 0x467f18 VXORPD	%XMM1,%XMM1,%XMM1

(621) 0x467f1c MOV	%RAX,-0x88(%RBP)

(621) 0x467f23 ADD	%RCX,%RDI

(621) 0x467f26 INC	%RAX

(621) 0x467f29 MOV	%R9,-0x90(%RBP)

(621) 0x467f30 VMOVAPD	%XMM1,%XMM2

(621) 0x467f34 CMP	(%RDI),%RAX

(621) 0x467f37 JGE	467ff4

(621) 0x467f3d CMPQ	$0x1,-0x40(%RBP)

(621) 0x467f42 MOV	%RBX,-0x88(%RBP)

(621) 0x467f49 JE	468580

(621) 0x467f4f MOV	%R13,-0xc0(%RBP)

(621) 0x467f56 MOV	%R10,-0xb8(%RBP)

(621) 0x467f5d MOV	-0x60(%RBP),%R9

(621) 0x467f61 MOV	-0x118(%RBP),%R10

(621) 0x467f68 NOPL	(%RAX,%RAX,1)

  (629) 0x467f70 MOV	(%R11,%RAX,8),%RCX

  (629) 0x467f74 CMPQ	$-0x3,(%R10,%RCX,8)

  (629) 0x467f79 JE	467f8e

  (629) 0x467f7b MOV	(%R9,%RSI,1),%R13

  (629) 0x467f7f CMP	%R13,(%R9,%RCX,8)

  (629) 0x467f83 JNE	467f8e

  (629) 0x467f85 MOV	-0x38(%RBP),%RBX

  (629) 0x467f89 VADDSD	(%RBX,%RAX,8),%XMM1,%XMM1

  (629) 0x467f8e CMP	$-0x1,%RCX

  (629) 0x467f92 JE	467fd7

  (629) 0x467f94 CMP	(%R12,%RCX,8),%RDX

  (629) 0x467f98 JNE	467fd7

  (629) 0x467f9a MOV	-0x38(%RBP),%R13

  (629) 0x467f9e LEA	(,%R8,8),%RBX

  (629) 0x467fa6 VMOVSD	(%R13,%RAX,8),%XMM6

  (629) 0x467fad MOV	-0x80(%RBP),%R13

  (629) 0x467fb1 VADDSD	%XMM6,%XMM2,%XMM2

  (629) 0x467fb5 VMOVSD	%XMM6,(%R13,%R8,8)

  (629) 0x467fbc MOV	-0x98(%RBP),%R13

  (629) 0x467fc3 INC	%R8

  (629) 0x467fc6 MOV	(%R13,%RCX,8),%RCX

  (629) 0x467fcb MOV	-0xb0(%RBP),%R13

  (629) 0x467fd2 MOV	%RCX,(%R13,%RBX,1)

  (629) 0x467fd7 INC	%RAX

  (629) 0x467fda CMP	%RAX,(%RDI)

  (629) 0x467fdd JG	467f70

(621) 0x467fdf MOV	-0x88(%RBP),%RBX

(621) 0x467fe6 MOV	-0xb8(%RBP),%R10

(621) 0x467fed MOV	-0xc0(%RBP),%R13

(621) 0x467ff4 MOV	-0xd8(%RBP),%R9

(621) 0x467ffb MOV	-0xc8(%RBP),%RAX

(621) 0x468002 MOV	%R9,%RDI

(621) 0x468005 MOV	(%RAX,%RDX,8),%RCX

(621) 0x468009 ADD	%RSI,%RDI

(621) 0x46800c MOV	0x8(%R9,%RSI,1),%RAX

(621) 0x468011 MOV	%RDI,-0x88(%RBP)

(621) 0x468018 MOV	(%RDI),%RDI

(621) 0x46801b ADD	%RCX,%RAX

(621) 0x46801e SUB	%RDI,%RAX

(621) 0x468021 CMP	%RAX,%RCX

(621) 0x468024 JGE	468163

(621) 0x46802a MOV	-0x100(%RBP),%RDI

(621) 0x468031 MOV	0x8(%RDI),%R9

(621) 0x468035 LEA	(%R9,%RAX,8),%RDI

(621) 0x468039 LEA	(%R9,%RCX,8),%RCX

(621) 0x46803d MOV	%RDI,%RAX

(621) 0x468040 SUB	%RCX,%RAX

(621) 0x468043 SUB	$0x8,%RAX

(621) 0x468047 SHR	$0x3,%RAX

(621) 0x46804b INC	%RAX

(621) 0x46804e AND	$0x7,%EAX

(621) 0x468051 JE	4680e9

(621) 0x468057 CMP	$0x1,%RAX

(621) 0x46805b JE	4680d5

(621) 0x46805d CMP	$0x2,%RAX

(621) 0x468061 JE	4680c6

(621) 0x468063 CMP	$0x3,%RAX

(621) 0x468067 JE	4680b7

(621) 0x468069 CMP	$0x4,%RAX

(621) 0x46806d JE	4680a8

(621) 0x46806f CMP	$0x5,%RAX

(621) 0x468073 JE	468099

(621) 0x468075 CMP	$0x6,%RAX

(621) 0x468079 JE	46808a

(621) 0x46807b MOV	(%RCX),%R9

(621) 0x46807e ADD	$0x8,%RCX

(621) 0x468082 MOV	(%R14,%R9,8),%RAX

(621) 0x468086 MOV	%RDX,(%RBX,%RAX,8)

(621) 0x46808a MOV	(%RCX),%R9

(621) 0x46808d ADD	$0x8,%RCX

(621) 0x468091 MOV	(%R14,%R9,8),%RAX

(621) 0x468095 MOV	%RDX,(%RBX,%RAX,8)

(621) 0x468099 MOV	(%RCX),%R9

(621) 0x46809c ADD	$0x8,%RCX

(621) 0x4680a0 MOV	(%R14,%R9,8),%RAX

(621) 0x4680a4 MOV	%RDX,(%RBX,%RAX,8)

(621) 0x4680a8 MOV	(%RCX),%R9

(621) 0x4680ab ADD	$0x8,%RCX

(621) 0x4680af MOV	(%R14,%R9,8),%RAX

(621) 0x4680b3 MOV	%RDX,(%RBX,%RAX,8)

(621) 0x4680b7 MOV	(%RCX),%R9

(621) 0x4680ba ADD	$0x8,%RCX

(621) 0x4680be MOV	(%R14,%R9,8),%RAX

(621) 0x4680c2 MOV	%RDX,(%RBX,%RAX,8)

(621) 0x4680c6 MOV	(%RCX),%R9

(621) 0x4680c9 ADD	$0x8,%RCX

(621) 0x4680cd MOV	(%R14,%R9,8),%RAX

(621) 0x4680d1 MOV	%RDX,(%RBX,%RAX,8)

(621) 0x4680d5 MOV	(%RCX),%R9

(621) 0x4680d8 ADD	$0x8,%RCX

(621) 0x4680dc MOV	(%R14,%R9,8),%RAX

(621) 0x4680e0 MOV	%RDX,(%RBX,%RAX,8)

(621) 0x4680e4 CMP	%RCX,%RDI

(621) 0x4680e7 JE	468159

(621) 0x4680e9 MOV	-0x50(%RBP),%R9

  (627) 0x4680ed MOV	(%RCX),%RAX

  (627) 0x4680f0 ADD	$0x40,%RCX

  (627) 0x4680f4 MOV	(%R14,%RAX,8),%RAX

  (627) 0x4680f8 MOV	%RDX,(%RBX,%RAX,8)

  (627) 0x4680fc MOV	-0x38(%RCX),%RAX

  (627) 0x468100 MOV	(%R14,%RAX,8),%RAX

  (627) 0x468104 MOV	%RDX,(%RBX,%RAX,8)

  (627) 0x468108 MOV	-0x30(%RCX),%RAX

  (627) 0x46810c MOV	(%R14,%RAX,8),%RAX

  (627) 0x468110 MOV	%RDX,(%RBX,%RAX,8)

  (627) 0x468114 MOV	-0x28(%RCX),%RAX

  (627) 0x468118 MOV	(%R14,%RAX,8),%RAX

  (627) 0x46811c MOV	%RDX,(%RBX,%RAX,8)

  (627) 0x468120 MOV	-0x20(%RCX),%RAX

  (627) 0x468124 MOV	(%R14,%RAX,8),%RAX

  (627) 0x468128 MOV	%RDX,(%RBX,%RAX,8)

  (627) 0x46812c MOV	-0x18(%RCX),%RAX

  (627) 0x468130 MOV	(%R14,%RAX,8),%RAX

  (627) 0x468134 MOV	%RDX,(%RBX,%RAX,8)

  (627) 0x468138 MOV	-0x10(%RCX),%RAX

  (627) 0x46813c MOV	(%R14,%RAX,8),%RAX

  (627) 0x468140 MOV	%RDX,(%RBX,%RAX,8)

  (627) 0x468144 MOV	-0x8(%RCX),%RAX

  (627) 0x468148 MOV	(%R14,%RAX,8),%RAX

  (627) 0x46814c MOV	%RDX,(%RBX,%RAX,8)

  (627) 0x468150 CMP	%RCX,%RDI

  (627) 0x468153 JNE	4680ed

(621) 0x468155 MOV	%R9,-0x50(%RBP)

(621) 0x468159 MOV	-0x88(%RBP),%RCX

(621) 0x468160 MOV	(%RCX),%RDI

(621) 0x468163 MOV	-0xe8(%RBP),%RCX

(621) 0x46816a MOV	-0x50(%RBP),%R9

(621) 0x46816e MOV	(%RCX,%RDX,8),%RAX

(621) 0x468172 ADD	%RCX,%R9

(621) 0x468175 CMP	(%R9),%RAX

(621) 0x468178 JGE	4686b0

(621) 0x46817e CMPQ	$0,-0x110(%RBP)

(621) 0x468186 JE	468608

(621) 0x46818c MOV	%R8,-0xc0(%RBP)

(621) 0x468193 MOV	%R14,-0x50(%RBP)

(621) 0x468197 MOV	%R11,-0xb8(%RBP)

(621) 0x46819e MOV	-0x120(%RBP),%R8

(621) 0x4681a5 JMP	468213

0x4681a7 NOPW	(%RAX,%RAX,1)

  (626) 0x4681b0 MOV	-0x68(%RBP),%R11

  (626) 0x4681b4 MOV	-0x60(%RBP),%R14

  (626) 0x4681b8 MOV	(%R11,%RCX,8),%R11

  (626) 0x4681bc CMP	%R11,(%R14,%RSI,1)

  (626) 0x4681c0 JE	46822a

  (626) 0x4681c2 CMP	$-0x1,%RCX

  (626) 0x4681c6 JE	468207

  (626) 0x4681c8 CMP	(%RBX,%RCX,8),%RDX

  (626) 0x4681cc JNE	468207

  (626) 0x4681ce MOV	-0x48(%RBP),%R11

  (626) 0x4681d2 LEA	(,%RDI,8),%R14

  (626) 0x4681da VMOVSD	(%R11,%RAX,8),%XMM7

  (626) 0x4681e0 MOV	-0x78(%RBP),%R11

  (626) 0x4681e4 VADDSD	%XMM7,%XMM2,%XMM2

  (626) 0x4681e8 VMOVSD	%XMM7,(%R11,%RDI,8)

  (626) 0x4681ee MOV	-0xa0(%RBP),%R11

  (626) 0x4681f5 INC	%RDI

  (626) 0x4681f8 MOV	(%R11,%RCX,8),%RCX

  (626) 0x4681fc MOV	-0xa8(%RBP),%R11

  (626) 0x468203 MOV	%RCX,(%R11,%R14,1)

  (626) 0x468207 INC	%RAX

  (626) 0x46820a CMP	%RAX,(%R9)

  (626) 0x46820d JLE	4682d0

  (626) 0x468213 MOV	(%R13,%RAX,8),%R14

  (626) 0x468218 MOV	(%R8,%R14,8),%RCX

  (626) 0x46821c CMPQ	$-0x3,(%R10,%RCX,8)

  (626) 0x468221 JE	4681c2

  (626) 0x468223 CMPQ	$0x1,-0x40(%RBP)

  (626) 0x468228 JNE	4681b0

  (626) 0x46822a MOV	-0x48(%RBP),%R14

  (626) 0x46822e VADDSD	(%R14,%RAX,8),%XMM1,%XMM1

  (626) 0x468234 JMP	4681c2

0x468236 MOV	%R12,%RDI

0x468239 MOV	$0x8,%ESI

0x46823e MOV	%R11,-0xb8(%RBP)

0x468245 MOV	%R10,-0x90(%RBP)

0x46824c MOV	%R12,-0x70(%RBP)

0x468250 VMOVSD	%XMM0,-0x88(%RBP)

0x468258 CALL	5523b0 <hypre_CAlloc>

0x46825d MOV	-0x70(%RBP),%RCX

0x468261 VMOVSD	-0x88(%RBP),%XMM0

0x468269 MOV	-0x90(%RBP),%R10

0x468270 MOV	-0xb8(%RBP),%R11

0x468277 MOV	%RAX,%RBX

0x46827a XOR	%R12D,%R12D

0x46827d TEST	%RCX,%RCX

0x468280 JLE	467cde

0x468286 LEA	(,%RCX,8),%RDX

0x46828e MOV	$0xff,%ESI

0x468293 MOV	%RBX,%RDI

0x468296 MOV	%R11,-0x90(%RBP)

0x46829d MOV	%R10,-0x88(%RBP)

0x4682a4 VMOVSD	%XMM0,-0x70(%RBP)

0x4682a9 CALL	4110a0 <memset@plt>

0x4682ae VMOVSD	-0x70(%RBP),%XMM0

0x4682b3 MOV	-0x88(%RBP),%R10

0x4682ba MOV	-0x90(%RBP),%R11

0x4682c1 JMP	467cde

0x4682c6 NOPW	%CS:(%RAX,%RAX,1)

(621) 0x4682d0 MOV	-0x50(%RBP),%R14

(621) 0x4682d4 MOV	-0xb8(%RBP),%R11

(621) 0x4682db MOV	-0xc0(%RBP),%R8

(621) 0x4682e2 MOV	-0x88(%RBP),%RDX

(621) 0x4682e9 MOV	(%RDX),%R9

(621) 0x4682ec MOV	-0x90(%RBP),%RAX

(621) 0x4682f3 MOV	-0x38(%RBP),%RSI

(621) 0x4682f7 MOV	(%RAX),%RCX

(621) 0x4682fa VMULSD	(%RSI,%RCX,8),%XMM2,%XMM10

(621) 0x4682ff VCOMISD	%XMM4,%XMM10

(621) 0x468303 JE	46830e

(621) 0x468305 VXORPD	%XMM5,%XMM1,%XMM11

(621) 0x468309 VDIVSD	%XMM10,%XMM11,%XMM0

(621) 0x46830e MOV	-0x70(%RBP),%RDX

(621) 0x468312 MOV	(%RDX),%RAX

(621) 0x468315 CMP	%R8,%RAX

(621) 0x468318 JGE	46841f

(621) 0x46831e MOV	-0x80(%RBP),%RCX

(621) 0x468322 LEA	(%RCX,%R8,8),%R8

(621) 0x468326 LEA	(%RCX,%RAX,8),%RDX

(621) 0x46832a MOV	%R8,%RSI

(621) 0x46832d SUB	%RDX,%RSI

(621) 0x468330 SUB	$0x8,%RSI

(621) 0x468334 SHR	$0x3,%RSI

(621) 0x468338 INC	%RSI

(621) 0x46833b AND	$0x7,%ESI

(621) 0x46833e JE	4683c8

(621) 0x468344 CMP	$0x1,%RSI

(621) 0x468348 JE	4683b6

(621) 0x46834a CMP	$0x2,%RSI

(621) 0x46834e JE	4683a9

(621) 0x468350 CMP	$0x3,%RSI

(621) 0x468354 JE	46839c

(621) 0x468356 CMP	$0x4,%RSI

(621) 0x46835a JE	46838f

(621) 0x46835c CMP	$0x5,%RSI

(621) 0x468360 JE	468382

(621) 0x468362 CMP	$0x6,%RSI

(621) 0x468366 JE	468375

(621) 0x468368 VMULSD	(%RDX),%XMM0,%XMM12

(621) 0x46836c ADD	$0x8,%RDX

(621) 0x468370 VMOVSD	%XMM12,-0x8(%RDX)

(621) 0x468375 VMULSD	(%RDX),%XMM0,%XMM13

(621) 0x468379 ADD	$0x8,%RDX

(621) 0x46837d VMOVSD	%XMM13,-0x8(%RDX)

(621) 0x468382 VMULSD	(%RDX),%XMM0,%XMM14

(621) 0x468386 ADD	$0x8,%RDX

(621) 0x46838a VMOVSD	%XMM14,-0x8(%RDX)

(621) 0x46838f VMULSD	(%RDX),%XMM0,%XMM15

(621) 0x468393 ADD	$0x8,%RDX

(621) 0x468397 VMOVSD	%XMM15,-0x8(%RDX)

(621) 0x46839c VMULSD	(%RDX),%XMM0,%XMM1

(621) 0x4683a0 ADD	$0x8,%RDX

(621) 0x4683a4 VMOVSD	%XMM1,-0x8(%RDX)

(621) 0x4683a9 VMULSD	(%RDX),%XMM0,%XMM3

(621) 0x4683ad ADD	$0x8,%RDX

(621) 0x4683b1 VMOVSD	%XMM3,-0x8(%RDX)

(621) 0x4683b6 VMULSD	(%RDX),%XMM0,%XMM2

(621) 0x4683ba ADD	$0x8,%RDX

(621) 0x4683be VMOVSD	%XMM2,-0x8(%RDX)

(621) 0x4683c3 CMP	%R8,%RDX

(621) 0x4683c6 JE	46841f

  (623) 0x4683c8 VMULSD	(%RDX),%XMM0,%XMM6

  (623) 0x4683cc VMULSD	0x8(%RDX),%XMM0,%XMM7

  (623) 0x4683d1 VMULSD	0x10(%RDX),%XMM0,%XMM8

  (623) 0x4683d6 VMULSD	0x18(%RDX),%XMM0,%XMM9

  (623) 0x4683db VMULSD	0x20(%RDX),%XMM0,%XMM10

  (623) 0x4683e0 VMULSD	0x28(%RDX),%XMM0,%XMM11

  (623) 0x4683e5 VMULSD	0x30(%RDX),%XMM0,%XMM12

  (623) 0x4683ea VMULSD	0x38(%RDX),%XMM0,%XMM13

  (623) 0x4683ef VMOVSD	%XMM6,(%RDX)

  (623) 0x4683f3 VMOVSD	%XMM7,0x8(%RDX)

  (623) 0x4683f8 VMOVSD	%XMM8,0x10(%RDX)

  (623) 0x4683fd VMOVSD	%XMM9,0x18(%RDX)

  (623) 0x468402 VMOVSD	%XMM10,0x20(%RDX)

  (623) 0x468407 VMOVSD	%XMM11,0x28(%RDX)

  (623) 0x46840c VMOVSD	%XMM12,0x30(%RDX)

  (623) 0x468411 VMOVSD	%XMM13,0x38(%RDX)

  (623) 0x468416 ADD	$0x40,%RDX

  (623) 0x46841a CMP	%R8,%RDX

  (623) 0x46841d JNE	4683c8

(621) 0x46841f CMP	%R9,%RDI

(621) 0x468422 JLE	468547

(621) 0x468428 MOV	-0x78(%RBP),%RCX

(621) 0x46842c LEA	(%RCX,%RDI,8),%RDI

(621) 0x468430 LEA	(%RCX,%R9,8),%R9

(621) 0x468434 MOV	%RDI,%RAX

(621) 0x468437 SUB	%R9,%RAX

(621) 0x46843a SUB	$0x8,%RAX

(621) 0x46843e SHR	$0x3,%RAX

(621) 0x468442 INC	%RAX

(621) 0x468445 AND	$0x7,%EAX

(621) 0x468448 JE	4684e0

(621) 0x46844e CMP	$0x1,%RAX

(621) 0x468452 JE	4684cc

(621) 0x468454 CMP	$0x2,%RAX

(621) 0x468458 JE	4684bd

(621) 0x46845a CMP	$0x3,%RAX

(621) 0x46845e JE	4684ae

(621) 0x468460 CMP	$0x4,%RAX

(621) 0x468464 JE	46849f

(621) 0x468466 CMP	$0x5,%RAX

(621) 0x46846a JE	468490

(621) 0x46846c CMP	$0x6,%RAX

(621) 0x468470 JE	468481

(621) 0x468472 VMULSD	(%R9),%XMM0,%XMM14

(621) 0x468477 ADD	$0x8,%R9

(621) 0x46847b VMOVSD	%XMM14,-0x8(%R9)

(621) 0x468481 VMULSD	(%R9),%XMM0,%XMM15

(621) 0x468486 ADD	$0x8,%R9

(621) 0x46848a VMOVSD	%XMM15,-0x8(%R9)

(621) 0x468490 VMULSD	(%R9),%XMM0,%XMM1

(621) 0x468495 ADD	$0x8,%R9

(621) 0x468499 VMOVSD	%XMM1,-0x8(%R9)

(621) 0x46849f VMULSD	(%R9),%XMM0,%XMM3

(621) 0x4684a4 ADD	$0x8,%R9

(621) 0x4684a8 VMOVSD	%XMM3,-0x8(%R9)

(621) 0x4684ae VMULSD	(%R9),%XMM0,%XMM2

(621) 0x4684b3 ADD	$0x8,%R9

(621) 0x4684b7 VMOVSD	%XMM2,-0x8(%R9)

(621) 0x4684bd VMULSD	(%R9),%XMM0,%XMM6

(621) 0x4684c2 ADD	$0x8,%R9

(621) 0x4684c6 VMOVSD	%XMM6,-0x8(%R9)

(621) 0x4684cc VMULSD	(%R9),%XMM0,%XMM7

(621) 0x4684d1 ADD	$0x8,%R9

(621) 0x4684d5 VMOVSD	%XMM7,-0x8(%R9)

(621) 0x4684db CMP	%R9,%RDI

(621) 0x4684de JE	468547

  (622) 0x4684e0 VMULSD	(%R9),%XMM0,%XMM8

  (622) 0x4684e5 VMULSD	0x8(%R9),%XMM0,%XMM9

  (622) 0x4684eb VMULSD	0x10(%R9),%XMM0,%XMM10

  (622) 0x4684f1 VMULSD	0x18(%R9),%XMM0,%XMM11

  (622) 0x4684f7 VMULSD	0x20(%R9),%XMM0,%XMM12

  (622) 0x4684fd VMULSD	0x28(%R9),%XMM0,%XMM13

  (622) 0x468503 VMULSD	0x30(%R9),%XMM0,%XMM14

  (622) 0x468509 VMULSD	0x38(%R9),%XMM0,%XMM15

  (622) 0x46850f VMOVSD	%XMM8,(%R9)

  (622) 0x468514 VMOVSD	%XMM9,0x8(%R9)

  (622) 0x46851a VMOVSD	%XMM10,0x10(%R9)

  (622) 0x468520 VMOVSD	%XMM11,0x18(%R9)

  (622) 0x468526 VMOVSD	%XMM12,0x20(%R9)

  (622) 0x46852c VMOVSD	%XMM13,0x28(%R9)

  (622) 0x468532 VMOVSD	%XMM14,0x30(%R9)

  (622) 0x468538 VMOVSD	%XMM15,0x38(%R9)

  (622) 0x46853e ADD	$0x40,%R9

  (622) 0x468542 CMP	%R9,%RDI

  (622) 0x468545 JNE	4684e0

(621) 0x468547 ADDQ	$0x8,-0x58(%RBP)

(621) 0x46854c MOV	-0x58(%RBP),%RDX

(621) 0x468550 CMP	%RDX,-0xf8(%RBP)

(621) 0x468557 JNE	467d88

0x46855d MOV	%R12,%RDI

0x468560 CALL	552440 <hypre_Free>

0x468565 ADD	$0xf8,%RSP

0x46856c MOV	%RBX,%RDI

0x46856f POP	%RBX

0x468570 POP	%R12

0x468572 POP	%R13

0x468574 POP	%R14

0x468576 POP	%R15

0x468578 POP	%RBP

0x468579 JMP	552440

0x46857e XCHG	%AX,%AX

(621) 0x468580 MOV	%RSI,-0xb8(%RBP)

(621) 0x468587 MOV	-0x118(%RBP),%RSI

(621) 0x46858e XCHG	%AX,%AX

  (628) 0x468590 MOV	(%R11,%RAX,8),%RCX

  (628) 0x468594 CMPQ	$-0x3,(%RSI,%RCX,8)

  (628) 0x468599 JE	4685a4

  (628) 0x46859b MOV	-0x38(%RBP),%RBX

  (628) 0x46859f VADDSD	(%RBX,%RAX,8),%XMM1,%XMM1

  (628) 0x4685a4 CMP	$-0x1,%RCX

  (628) 0x4685a8 JE	4685e9

  (628) 0x4685aa CMP	(%R12,%RCX,8),%RDX

  (628) 0x4685ae JNE	4685e9

  (628) 0x4685b0 MOV	-0x38(%RBP),%R9

  (628) 0x4685b4 LEA	(,%R8,8),%RBX

  (628) 0x4685bc VMOVSD	(%R9,%RAX,8),%XMM3

  (628) 0x4685c2 MOV	-0x80(%RBP),%R9

  (628) 0x4685c6 VADDSD	%XMM3,%XMM2,%XMM2

  (628) 0x4685ca VMOVSD	%XMM3,(%R9,%R8,8)

  (628) 0x4685d0 MOV	-0x98(%RBP),%R9

  (628) 0x4685d7 INC	%R8

  (628) 0x4685da MOV	(%R9,%RCX,8),%RCX

  (628) 0x4685de MOV	-0xb0(%RBP),%R9

  (628) 0x4685e5 MOV	%RCX,(%R9,%RBX,1)

  (628) 0x4685e9 INC	%RAX

  (628) 0x4685ec CMP	%RAX,(%RDI)

  (628) 0x4685ef JG	468590

(621) 0x4685f1 MOV	-0x88(%RBP),%RBX

(621) 0x4685f8 MOV	-0xb8(%RBP),%RSI

(621) 0x4685ff JMP	467ff4

0x468604 NOPL	(%RAX)

(621) 0x468608 CMPQ	$0x1,-0x40(%RBP)

(621) 0x46860d JE	4686b8

(621) 0x468613 MOV	%R14,-0x50(%RBP)

(621) 0x468617 MOV	%R8,-0xb8(%RBP)

(621) 0x46861e XCHG	%AX,%AX

  (625) 0x468620 MOV	(%R13,%RAX,8),%RCX

  (625) 0x468625 CMPQ	$-0x3,(%R10,%RCX,8)

  (625) 0x46862a JE	468648

  (625) 0x46862c MOV	-0x60(%RBP),%R8

  (625) 0x468630 MOV	-0x68(%RBP),%R14

  (625) 0x468634 MOV	(%R8,%RSI,1),%R8

  (625) 0x468638 CMP	%R8,(%R14,%RCX,8)

  (625) 0x46863c JNE	468648

  (625) 0x46863e MOV	-0x48(%RBP),%R14

  (625) 0x468642 VADDSD	(%R14,%RAX,8),%XMM1,%XMM1

  (625) 0x468648 CMP	$-0x1,%RCX

  (625) 0x46864c JE	46868e

  (625) 0x46864e CMP	(%RBX,%RCX,8),%RDX

  (625) 0x468652 JNE	46868e

  (625) 0x468654 MOV	-0x48(%RBP),%R8

  (625) 0x468658 LEA	(,%RDI,8),%R14

  (625) 0x468660 VMOVSD	(%R8,%RAX,8),%XMM9

  (625) 0x468666 MOV	-0x78(%RBP),%R8

  (625) 0x46866a VADDSD	%XMM9,%XMM2,%XMM2

  (625) 0x46866f VMOVSD	%XMM9,(%R8,%RDI,8)

  (625) 0x468675 MOV	-0xa0(%RBP),%R8

  (625) 0x46867c INC	%RDI

  (625) 0x46867f MOV	(%R8,%RCX,8),%RCX

  (625) 0x468683 MOV	-0xa8(%RBP),%R8

  (625) 0x46868a MOV	%RCX,(%R8,%R14,1)

  (625) 0x46868e INC	%RAX

  (625) 0x468691 CMP	%RAX,(%R9)

  (625) 0x468694 JG	468620

(621) 0x468696 MOV	-0x50(%RBP),%R14

(621) 0x46869a MOV	-0xb8(%RBP),%R8

(621) 0x4686a1 JMP	4682e2

0x4686a6 NOPW	%CS:(%RAX,%RAX,1)

(621) 0x4686b0 MOV	%RDI,%R9

(621) 0x4686b3 JMP	4682ec

(621) 0x4686b8 MOV	%R8,-0x50(%RBP)

(621) 0x4686bc NOPL	(%RAX)

  (624) 0x4686c0 MOV	(%R13,%RAX,8),%RCX

  (624) 0x4686c5 CMPQ	$-0x3,(%R10,%RCX,8)

  (624) 0x4686ca JE	4686d5

  (624) 0x4686cc MOV	-0x48(%RBP),%RSI

  (624) 0x4686d0 VADDSD	(%RSI,%RAX,8),%XMM1,%XMM1

  (624) 0x4686d5 CMP	$-0x1,%RCX

  (624) 0x4686d9 JE	46871b

  (624) 0x4686db CMP	(%RBX,%RCX,8),%RDX

  (624) 0x4686df JNE	46871b

  (624) 0x4686e1 MOV	-0x48(%RBP),%R8

  (624) 0x4686e5 LEA	(,%RDI,8),%RSI

  (624) 0x4686ed VMOVSD	(%R8,%RAX,8),%XMM8

  (624) 0x4686f3 MOV	-0x78(%RBP),%R8

  (624) 0x4686f7 VADDSD	%XMM8,%XMM2,%XMM2

  (624) 0x4686fc VMOVSD	%XMM8,(%R8,%RDI,8)

  (624) 0x468702 MOV	-0xa0(%RBP),%R8

  (624) 0x468709 INC	%RDI

  (624) 0x46870c MOV	(%R8,%RCX,8),%RCX

  (624) 0x468710 MOV	-0xa8(%RBP),%R8

  (624) 0x468717 MOV	%RCX,(%R8,%RSI,1)

  (624) 0x46871b INC	%RAX

  (624) 0x46871e CMP	%RAX,(%R9)

  (624) 0x468721 JG	4686c0

(621) 0x468723 MOV	-0x50(%RBP),%R8

(621) 0x468727 JMP	4682e2

0x46872c MOV	%RBX,%RDI

0x46872f MOV	$0x8,%ESI

0x468734 MOV	%R11,-0xf8(%RBP)

0x46873b MOV	%R12,-0xb8(%RBP)

0x468742 MOV	%R10,-0x90(%RBP)

0x468749 MOV	%RBX,-0x70(%RBP)

0x46874d VMOVSD	%XMM0,-0x88(%RBP)

0x468755 CALL	5523b0 <hypre_CAlloc>

0x46875a MOV	-0xb8(%RBP),%RBX

0x468761 MOV	-0x70(%RBP),%RDX

0x468765 TEST	%RBX,%RBX

0x468768 VMOVSD	-0x88(%RBP),%XMM0

0x468770 MOV	-0x90(%RBP),%R10

0x468777 MOV	-0xf8(%RBP),%R11

0x46877e MOV	%RAX,%R12

0x468781 JNE	4687cc

0x468783 XOR	%EBX,%EBX

0x468785 TEST	%RDX,%RDX

0x468788 JLE	467cde

0x46878e SAL	$0x3,%RDX

0x468792 MOV	$0xff,%ESI

0x468797 MOV	%R12,%RDI

0x46879a MOV	%R11,-0x90(%RBP)

0x4687a1 MOV	%R10,-0x88(%RBP)

0x4687a8 VMOVSD	%XMM0,-0x70(%RBP)

0x4687ad XOR	%EBX,%EBX

0x4687af CALL	4110a0 <memset@plt>

0x4687b4 VMOVSD	-0x70(%RBP),%XMM0

0x4687b9 MOV	-0x88(%RBP),%R10

0x4687c0 MOV	-0x90(%RBP),%R11

0x4687c7 JMP	467cde

0x4687cc MOV	%RBX,%RDI

0x4687cf MOV	$0x8,%ESI

0x4687d4 MOV	%R11,-0xf8(%RBP)

0x4687db MOV	%R10,-0xb8(%RBP)

0x4687e2 MOV	%RDX,-0x90(%RBP)

0x4687e9 MOV	%RBX,-0x70(%RBP)

0x4687ed VMOVSD	%XMM0,-0x88(%RBP)

0x4687f5 CALL	5523b0 <hypre_CAlloc>

0x4687fa MOV	-0x90(%RBP),%RDX

0x468801 MOV	-0x70(%RBP),%RCX

0x468805 TEST	%RDX,%RDX

0x468808 VMOVSD	-0x88(%RBP),%XMM0

0x468810 MOV	-0xb8(%RBP),%R10

0x468817 MOV	-0xf8(%RBP),%R11

0x46881e MOV	%RAX,%RBX

0x468821 JLE	46827d

0x468827 SAL	$0x3,%RDX

0x46882b MOV	$0xff,%ESI

0x468830 MOV	%R12,%RDI

0x468833 MOV	%R11,-0xb8(%RBP)

0x46883a MOV	%RCX,-0x90(%RBP)

0x468841 MOV	%R10,-0x88(%RBP)

0x468848 VMOVSD	%XMM0,-0x70(%RBP)

0x46884d CALL	4110a0 <memset@plt>

0x468852 VMOVSD	-0x70(%RBP),%XMM0

0x468857 MOV	-0x88(%RBP),%R10

0x46885e MOV	-0x90(%RBP),%RCX

0x468865 MOV	-0xb8(%RBP),%R11

0x46886c JMP	46827d

0x468871 NOPW	%CS:(%RAX,%RAX,1)

0x46887c NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○97.74	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.26	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1584-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 37.33 to 5.33 cycles (7.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 37.33 to 5.00 cycles (7.47x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CAlloc: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1589
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1586
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1589
hypre_Free: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1662
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1596
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1597
memset@plt: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1593
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1591
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1591

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 528 bytes. The binary function is storing 440 bytes.

General properties

nb instructions	211
nb uops	224
loop length	1088
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	30

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	37.33 cycles
front end	37.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.90	6.80	24.00	24.00	35.00	6.80	6.70	35.00	35.00	35.00	6.80	24.00
cycles	6.90	7.80	24.00	24.00	35.00	6.80	6.70	35.00	35.00	35.00	6.80	24.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	37.33
Dispatch	35.00
DIV/SQRT	10.00
Overall L1	37.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	4%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 37.33 cycles. At this rate:

7% of peak load performance is reached (14.14 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (11.79 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 37.33 to 35.00 cycles (1.07x speedup).

ASM code

In the binary file, the address of the function is: 467b70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xf8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0xf8(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xf0(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xe0(%RDI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xd8(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xd0(%RDI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xc8(%RDI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xc0(%RDI),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xb8(%RDI),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb0(%RDI),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xe8(%RDI),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R12,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x90(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x80(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RDI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x68(%RDI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xa8(%RDI),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x58(%RDI),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x60(%RDI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RDI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R8,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RDI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa0(%RDI),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x98(%RDI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RDI),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x50(%RDI),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x48(%RDI),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RDI),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RDI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x118(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %RBX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 46872c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xbbc>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 468236 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6c6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R11,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 555090 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 555080 <hypre_NumActiveThreads>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RSI	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOV -0x58(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x88(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R10,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %RAX,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R11,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R9,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RSI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVNE %RAX,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
LEA (%R9,%R11,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x90(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xb8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JLE 46855d <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9ed>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xc0(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVQ 0xf2e06(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%R8,%RDI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%RCX,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R11,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x88(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x90(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xb8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 467cde <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x16e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%RCX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4110a0 <memset@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x70(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x88(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x90(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 467cde <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x16e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 552440 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0xf8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 552440 <hypre_Free>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R11,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0xb8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x70(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RBX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
VMOVSD -0x88(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x90(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xf8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 4687cc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xc5c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 467cde <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x16e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 4110a0 <memset@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x70(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x88(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x90(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 467cde <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x16e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R11,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x90(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
VMOVSD -0x88(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xb8(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xf8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 46827d <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x70d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4110a0 <memset@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x70(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x88(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x90(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xb8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 46827d <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x70d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1584-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 37.33 to 5.33 cycles (7.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CAlloc: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1589
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1586
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1589
hypre_Free: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1662
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1596
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1597
memset@plt: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1593
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1591
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1591

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 528 bytes. The binary function is storing 440 bytes.

General properties

nb instructions	211
nb uops	224
loop length	1088
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	30

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	37.33 cycles
front end	37.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.90	6.80	24.00	24.00	35.00	6.80	6.70	35.00	35.00	35.00	6.80	24.00
cycles	6.90	7.80	24.00	24.00	35.00	6.80	6.70	35.00	35.00	35.00	6.80	24.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	37.33
Dispatch	35.00
DIV/SQRT	10.00
Overall L1	37.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	4%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 37.33 cycles. At this rate:

7% of peak load performance is reached (14.14 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (11.79 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 467b70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xf8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0xf8(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xf0(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xe0(%RDI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xd8(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xd0(%RDI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xc8(%RDI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xc0(%RDI),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xb8(%RDI),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb0(%RDI),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xe8(%RDI),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R12,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x90(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x80(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RDI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x68(%RDI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xa8(%RDI),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x58(%RDI),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x60(%RDI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RDI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R8,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RDI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa0(%RDI),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x98(%RDI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RDI),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x50(%RDI),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x48(%RDI),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RDI),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RDI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x118(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %RBX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 46872c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xbbc>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 468236 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6c6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R11,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 555090 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 555080 <hypre_NumActiveThreads>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RSI	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOV -0x58(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x88(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R10,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %RAX,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R11,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R9,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RSI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVNE %RAX,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
LEA (%R9,%R11,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0x90(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xb8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JLE 46855d <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9ed>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xc0(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVQ 0xf2e06(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%R8,%RDI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%RCX,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R11,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x88(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x90(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xb8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 467cde <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x16e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%RCX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4110a0 <memset@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x70(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x88(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x90(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 467cde <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x16e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 552440 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0xf8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 552440 <hypre_Free>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R11,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0xb8(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x70(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RBX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
VMOVSD -0x88(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x90(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xf8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 4687cc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xc5c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 467cde <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x16e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 4110a0 <memset@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x70(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x88(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x90(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 467cde <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x16e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R11,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x90(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
VMOVSD -0x88(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xb8(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xf8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 46827d <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x70d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM0,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4110a0 <memset@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x70(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x88(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x90(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xb8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 46827d <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x70d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass._omp_fn.9–	0.44	0.19
▼Loop 621 - par_multi_interp.c:1593-1660 - exec–	0.06	0.02
○Loop 628 - par_multi_interp.c:1618-1628 - exec	0.37	0.14
○Loop 624 - par_multi_interp.c:1639-1652 - exec	0.00	0.00
○Loop 625 - par_multi_interp.c:1639-1652 - exec	0.00	0.00
○Loop 627 - par_multi_interp.c:1633-1636 - exec	0.00	0.00
○Loop 622 - par_multi_interp.c:1659-1660 - exec	0.00	0.00
○Loop 623 - par_multi_interp.c:1657-1658 - exec	0.00	0.00
○Loop 626 - par_multi_interp.c:1639-1652 - exec	0.00	0.00
○Loop 629 - par_multi_interp.c:1618-1628 - exec	0.00	0.00
○Loop 630 - par_multi_interp.c:1612-1615 - exec	0.00	0.00

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