OV - exec - Function hypre_BoomerAMGBuildMultipass._omp

	Function: hypre_BoomerAMGBuildMultipass._omp_fn.10	Module: exec	Source: par_multi_interp.c:1737-1881 [...]	Coverage (incl. loops): 1.46% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1737 - 1881

--------------------------------------------------------------------------------

1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd)

[...]

1746:              tmp_marker = NULL;

1747:              if (n_fine)

1748:              {    tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1749:              tmp_marker_offd = NULL;

1750:              if (num_cols_offd)

1751:              {    tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1752:              tmp_array = NULL;

1753:              if (n_coarse)

1754:              {    tmp_array = hypre_CTAlloc(HYPRE_Int,n_coarse); }

1755:              tmp_array_offd = NULL;

1756:              if (new_num_cols_offd > n_coarse_offd)

1757:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd); }

1758:              else

1759:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,n_coarse_offd);}

1760:              for (i=0; i < n_fine; i++)

1761:              {    tmp_marker[i] = -1; }

1762:              for (i=0; i < num_cols_offd; i++)

1763:              {    tmp_marker_offd[i] = -1; }

1764:

1765:              /* Compute this thread's range of pass_length */

1766:              my_thread_num = hypre_GetThreadNum();

1767:              num_threads = hypre_NumActiveThreads();

1768:              thread_start = pass_pointer[pass] + (pass_length/num_threads)*my_thread_num;

1769:              if (my_thread_num == num_threads-1)

1770:              {  thread_stop = pass_pointer[pass] + pass_length; }

1771:              else

1772:              {  thread_stop = pass_pointer[pass] + (pass_length/num_threads)*(my_thread_num+1); }

1773:

1774:              for (i=thread_start; i < thread_stop; i++)

1775:              {

1776:                 i1 = pass_array[i];

1777:                 sum_C = 0;

1778:                 sum_N = 0;

1779:                 j_start = P_diag_start[i1];

1780:                 j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1781:                 cnt = P_diag_i[i1];

1782:                 for (j=j_start; j < j_end; j++)

1783:                 {

1784:                    k1 = P_diag_pass[pass][j];

1785:                tmp_array[k1] = cnt;

1786:                P_diag_data[cnt] = 0;

1787:                P_diag_j[cnt++] = k1;

1788:                 }

1789:                 j_start = P_offd_start[i1];

1790:                 j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1791:                 cnt_offd = P_offd_i[i1];

1792:                 for (j=j_start; j < j_end; j++)

1793:                 {

1794:                    k1 = P_offd_pass[pass][j];

1795:                tmp_array_offd[k1] = cnt_offd;

1796:                P_offd_data[cnt_offd] = 0;

1797:                P_offd_j[cnt_offd++] = k1;

1798:                 }

1799:                 for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1800:                 {

1801:                j1 = S_diag_j[j];

1802:                if (assigned[j1] == pass-1)

1803:                   tmp_marker[j1] = i1;

1804:                 }

1805:                 for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1806:                 {

1807:                j1 = S_offd_j[j];

1808:                if (assigned_offd[j1] == pass-1)

1809:                   tmp_marker_offd[j1] = i1;

1810:                 }

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

1838:                    }

1839:                 }

1840:                 for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1841:                 {

1842:                if (col_offd_S_to_A)

1843:                   j1 = map_A_to_S[A_offd_j[j]];

1844:                else

1845:                   j1 = A_offd_j[j];

1846:

1847:                if (j1 > -1 && tmp_marker_offd[j1] == i1)

1848:                {

1849:                   j_start = Pext_start[j1];

1850:                   j_end = j_start+Pext_i[j1+1];

1851:                   for (k=j_start; k < j_end; k++)

1852:                   {

1853:                  k1 = Pext_pass[pass][k];

1854:                      alfa = A_offd_data[j]*Pext_data[k];

1855:                  if (k1 < 0)

1856:                         P_diag_data[tmp_array[-k1-1]] += alfa;

1857:                  else

1858:                         P_offd_data[tmp_array_offd[k1]] += alfa;

1859:                      sum_C += alfa;

1860:                      sum_N += alfa;

1861:                       }

1862:                    }

1863:                    else

1864:                    {

1865:                       if (CF_marker_offd[j1] != -3 &&

1866:                 (num_functions == 1 || dof_func_offd[j1] == dof_func[i1]))

1867:                  sum_N += A_offd_data[j];

1868:                    }

1869:                 }

1870:                 diagonal = A_diag_data[A_diag_i[i1]];

1871:                 if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1872:

1873:                 for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++)

1874:                P_diag_data[j] *= alfa;

1875:                 for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++)

1876:                P_offd_data[j] *= alfa;

1877:              }

1878:              hypre_TFree(tmp_marker);

1879:              hypre_TFree(tmp_marker_offd);

1880:              hypre_TFree(tmp_array);

1881:              hypre_TFree(tmp_array_offd);

0x466670 PUSH	%RBP

0x466671 MOV	%RDI,%RAX

0x466674 MOV	%RSP,%RBP

0x466677 PUSH	%R15

0x466679 PUSH	%R14

0x46667b PUSH	%R13

0x46667d PUSH	%R12

0x46667f PUSH	%RBX

0x466680 SUB	$0x168,%RSP

0x466687 MOV	0x148(%RDI),%RDI

0x46668e MOV	0x138(%RAX),%RDX

0x466695 MOV	0x130(%RAX),%RCX

0x46669c MOV	0x128(%RAX),%RBX

0x4666a3 MOV	0x108(%RAX),%RSI

0x4666aa MOV	0x100(%RAX),%R9

0x4666b1 MOV	0xf8(%RAX),%R10

0x4666b8 MOV	%RDI,-0x48(%RBP)

0x4666bc MOV	0x110(%RAX),%RDI

0x4666c3 MOV	%RDX,-0x108(%RBP)

0x4666ca MOV	%RCX,-0x58(%RBP)

0x4666ce MOV	%RBX,-0x60(%RBP)

0x4666d2 MOV	%RSI,-0xa8(%RBP)

0x4666d9 MOV	%R9,-0x90(%RBP)

0x4666e0 MOV	0x140(%RAX),%R8

0x4666e7 MOV	0x120(%RAX),%RDX

0x4666ee MOV	0x118(%RAX),%RCX

0x4666f5 MOV	%RDI,-0x38(%RBP)

0x4666f9 MOV	%R10,-0x178(%RBP)

0x466700 MOV	0xf0(%RAX),%R11

0x466707 MOV	0xe8(%RAX),%R12

0x46670e MOV	0xd8(%RAX),%R14

0x466715 MOV	0xd0(%RAX),%R15

0x46671c MOV	0xc8(%RAX),%RBX

0x466723 MOV	0xe0(%RAX),%R13

0x46672a MOV	0xc0(%RAX),%RSI

0x466731 MOV	0xb8(%RAX),%R9

0x466738 MOV	0xb0(%RAX),%R10

0x46673f MOV	%R11,-0x188(%RBP)

0x466746 MOV	%R12,-0x148(%RBP)

0x46674d MOV	0xa8(%RAX),%R11

0x466754 MOV	0x98(%RAX),%R12

0x46675b MOV	%R14,-0x110(%RBP)

0x466762 MOV	%R15,-0x118(%RBP)

0x466769 MOV	0x80(%RAX),%R14

0x466770 MOV	0x68(%RAX),%R15

0x466774 MOV	%RBX,-0x98(%RBP)

0x46677b MOV	0x60(%RAX),%RBX

0x46677f MOV	%R13,-0x150(%RBP)

0x466786 MOV	%RSI,-0xe0(%RBP)

0x46678d MOV	%R9,-0xa0(%RBP)

0x466794 MOV	%R10,-0x158(%RBP)

0x46679b MOV	%R11,-0x180(%RBP)

0x4667a2 MOV	%R12,-0xb8(%RBP)

0x4667a9 MOV	%R14,-0xc0(%RBP)

0x4667b0 MOV	%R15,-0x68(%RBP)

0x4667b4 MOV	0xa0(%RAX),%R10

0x4667bb MOV	0x90(%RAX),%R11

0x4667c2 MOV	0x88(%RAX),%R13

0x4667c9 MOV	0x78(%RAX),%R12

0x4667cd MOV	0x70(%RAX),%R14

0x4667d1 MOV	%RBX,-0x120(%RBP)

0x4667d8 MOV	0x58(%RAX),%RSI

0x4667dc MOV	0x50(%RAX),%R9

0x4667e0 MOV	0x48(%RAX),%R15

0x4667e4 MOV	0x40(%RAX),%RBX

0x4667e8 MOV	%RSI,-0x70(%RBP)

0x4667ec MOV	%R9,-0x128(%RBP)

0x4667f3 MOV	0x38(%RAX),%RSI

0x4667f7 MOV	0x30(%RAX),%R9

0x4667fb MOV	%R15,-0x160(%RBP)

0x466802 MOV	0x28(%RAX),%R15

0x466806 MOV	%RBX,-0x130(%RBP)

0x46680d MOV	%RSI,-0x168(%RBP)

0x466814 MOV	0x20(%RAX),%RBX

0x466818 MOV	0x18(%RAX),%RSI

0x46681c MOV	%R9,-0x170(%RBP)

0x466823 MOV	%R15,-0x138(%RBP)

0x46682a MOV	0x10(%RAX),%R9

0x46682e MOV	0x8(%RAX),%R15

0x466832 MOV	(%RAX),%RAX

0x466835 MOV	%RBX,-0xc8(%RBP)

0x46683c MOV	%RSI,-0xe8(%RBP)

0x466843 MOV	%R9,-0x88(%RBP)

0x46684a MOV	%R15,-0x50(%RBP)

0x46684e MOV	%RAX,-0x80(%RBP)

0x466852 TEST	%RDI,%RDI

0x466855 JNE	467b01

0x46685b MOVQ	$0,-0x40(%RBP)

0x466863 TEST	%R14,%R14

0x466866 JNE	467a95

0x46686c MOVQ	$0,-0x78(%RBP)

0x466874 TEST	%RCX,%RCX

0x466877 JNE	467a38

0x46687d XOR	%R15D,%R15D

0x466880 CMP	%RDX,%R8

0x466883 JLE	467a15

0x466889 MOV	%R11,-0xd8(%RBP)

0x466890 MOV	%R10,-0xd0(%RBP)

0x466897 VMOVSD	%XMM2,-0xb0(%RBP)

0x46689f MOV	$0x8,%ESI

0x4668a4 MOV	%R8,%RDI

0x4668a7 CALL	5523b0 <hypre_CAlloc>

0x4668ac CMPQ	$0,-0x38(%RBP)

0x4668b1 VMOVSD	-0xb0(%RBP),%XMM2

0x4668b9 MOV	-0xd0(%RBP),%RDI

0x4668c0 MOV	-0xd8(%RBP),%RSI

0x4668c7 MOV	%RAX,%RBX

0x4668ca JLE	46690e

0x4668cc MOV	-0x38(%RBP),%RDX

0x4668d0 MOV	%RDI,-0xd0(%RBP)

0x4668d7 MOV	-0x40(%RBP),%RDI

0x4668db MOV	%RSI,-0xd8(%RBP)

0x4668e2 SAL	$0x3,%RDX

0x4668e6 MOV	$0xff,%ESI

0x4668eb VMOVSD	%XMM2,-0xb0(%RBP)

0x4668f3 CALL	4110a0 <memset@plt>

0x4668f8 VMOVSD	-0xb0(%RBP),%XMM2

0x466900 MOV	-0xd0(%RBP),%RDI

0x466907 MOV	-0xd8(%RBP),%RSI

0x46690e TEST	%R14,%R14

0x466911 JLE	46694f

0x466913 MOV	%RDI,-0xb0(%RBP)

0x46691a MOV	-0x78(%RBP),%RDI

0x46691e MOV	%RSI,-0xd0(%RBP)

0x466925 LEA	(,%R14,8),%RDX

0x46692d MOV	$0xff,%ESI

0x466932 VMOVSD	%XMM2,-0x38(%RBP)

0x466937 CALL	4110a0 <memset@plt>

0x46693c VMOVSD	-0x38(%RBP),%XMM2

0x466941 MOV	-0xb0(%RBP),%RDI

0x466948 MOV	-0xd0(%RBP),%RSI

0x46694f MOV	%RSI,-0xd8(%RBP)

0x466956 MOV	%RDI,-0xd0(%RBP)

0x46695d VMOVSD	%XMM2,-0x38(%RBP)

0x466962 CALL	555090 <hypre_GetThreadNum>

0x466967 MOV	%RAX,%R14

0x46696a CALL	555080 <hypre_NumActiveThreads>

0x46696f MOV	%RAX,%R9

0x466972 MOV	-0x98(%RBP),%RDX

0x466979 MOV	-0xa8(%RBP),%RAX

0x466980 MOV	%R14,%R10

0x466983 MOV	(%RDX,%RAX,8),%RCX

0x466987 LEA	(,%RAX,8),%R8

0x46698f MOV	-0x48(%RBP),%RAX

0x466993 MOV	-0x48(%RBP),%R11

0x466997 CQTO

0x466999 IDIV	%R9

0x46699c MOV	%R8,-0xb0(%RBP)

0x4669a3 VMOVSD	-0x38(%RBP),%XMM12

0x4669a8 ADD	%RCX,%R11

0x4669ab DEC	%R9

0x4669ae MOV	%R11,%RSI

0x4669b1 MOV	-0xd8(%RBP),%R11

0x4669b8 IMUL	%RAX,%R10

0x4669bc ADD	%R10,%RAX

0x4669bf ADD	%RCX,%RAX

0x4669c2 CMP	%R9,%R14

0x4669c5 CMOVNE	%RAX,%RSI

0x4669c9 LEA	(%RCX,%R10,1),%RDI

0x4669cd CMP	%RDI,%RSI

0x4669d0 MOV	-0xd0(%RBP),%R10

0x4669d7 JLE	4676c6

0x4669dd MOV	-0xe0(%RBP),%R14

0x4669e4 VMOVQ	0xf4184(%RIP),%XMM4

0x4669ec LEA	(%R14,%RSI,8),%R8

0x4669f0 LEA	(%R14,%RDI,8),%R9

0x4669f4 MOV	%R8,-0x140(%RBP)

0x4669fb MOV	-0xa8(%RBP),%R14

0x466a02 MOV	%R9,-0x98(%RBP)

0x466a09 MOV	%R15,%R9

0x466a0c MOV	-0xe8(%RBP),%R15

0x466a13 DEC	%R14

0x466a16 VXORPD	%XMM3,%XMM3,%XMM3

0x466a1a NOPW	(%RAX,%RAX,1)

(609) 0x466a20 MOV	-0x98(%RBP),%RCX

(609) 0x466a27 MOV	-0xc0(%RBP),%R8

(609) 0x466a2e MOV	(%RCX),%RDI

(609) 0x466a31 MOV	-0x118(%RBP),%RDX

(609) 0x466a38 LEA	(,%RDI,8),%RAX

(609) 0x466a40 LEA	0x8(%RAX),%RSI

(609) 0x466a44 LEA	(%R8,%RSI,1),%RCX

(609) 0x466a48 MOV	%RAX,-0x48(%RBP)

(609) 0x466a4c MOV	(%RDX,%RDI,8),%RDX

(609) 0x466a50 ADD	%R8,%RAX

(609) 0x466a53 MOV	(%RCX),%R8

(609) 0x466a56 MOV	%RAX,-0xd8(%RBP)

(609) 0x466a5d MOV	(%RAX),%RAX

(609) 0x466a60 ADD	%RDX,%R8

(609) 0x466a63 SUB	%RAX,%R8

(609) 0x466a66 MOV	%RCX,-0xd0(%RBP)

(609) 0x466a6d CMP	%R8,%RDX

(609) 0x466a70 JGE	466c66

(609) 0x466a76 MOV	%RAX,%RCX

(609) 0x466a79 SUB	%RDX,%RCX

(609) 0x466a7c SUB	%RAX,%RDX

(609) 0x466a7f MOV	%RDX,-0x38(%RBP)

(609) 0x466a83 ADD	%R8,%RCX

(609) 0x466a86 MOV	-0xb0(%RBP),%RDX

(609) 0x466a8d MOV	-0x150(%RBP),%R8

(609) 0x466a94 MOV	(%R8,%RDX,1),%R8

(609) 0x466a98 MOV	-0x38(%RBP),%RDX

(609) 0x466a9c LEA	(%R8,%RDX,8),%RDX

(609) 0x466aa0 MOV	%RCX,%R8

(609) 0x466aa3 SUB	%RAX,%R8

(609) 0x466aa6 AND	$0x7,%R8D

(609) 0x466aaa JE	466b8d

(609) 0x466ab0 CMP	$0x1,%R8

(609) 0x466ab4 JE	466b6c

(609) 0x466aba CMP	$0x2,%R8

(609) 0x466abe JE	466b54

(609) 0x466ac4 CMP	$0x3,%R8

(609) 0x466ac8 JE	466b3c

(609) 0x466aca CMP	$0x4,%R8

(609) 0x466ace JE	466b24

(609) 0x466ad0 CMP	$0x5,%R8

(609) 0x466ad4 JE	466b0c

(609) 0x466ad6 CMP	$0x6,%R8

(609) 0x466ada JE	466af4

(609) 0x466adc MOV	(%RDX,%RAX,8),%R8

(609) 0x466ae0 MOV	%RAX,(%R9,%R8,8)

(609) 0x466ae4 MOVQ	$0,(%R12,%RAX,8)

(609) 0x466aec INC	%RAX

(609) 0x466aef MOV	%R8,-0x8(%R13,%RAX,8)

(609) 0x466af4 MOV	(%RDX,%RAX,8),%R8

(609) 0x466af8 MOV	%RAX,(%R9,%R8,8)

(609) 0x466afc MOVQ	$0,(%R12,%RAX,8)

(609) 0x466b04 INC	%RAX

(609) 0x466b07 MOV	%R8,-0x8(%R13,%RAX,8)

(609) 0x466b0c MOV	(%RDX,%RAX,8),%R8

(609) 0x466b10 MOV	%RAX,(%R9,%R8,8)

(609) 0x466b14 MOVQ	$0,(%R12,%RAX,8)

(609) 0x466b1c INC	%RAX

(609) 0x466b1f MOV	%R8,-0x8(%R13,%RAX,8)

(609) 0x466b24 MOV	(%RDX,%RAX,8),%R8

(609) 0x466b28 MOV	%RAX,(%R9,%R8,8)

(609) 0x466b2c MOVQ	$0,(%R12,%RAX,8)

(609) 0x466b34 INC	%RAX

(609) 0x466b37 MOV	%R8,-0x8(%R13,%RAX,8)

(609) 0x466b3c MOV	(%RDX,%RAX,8),%R8

(609) 0x466b40 MOV	%RAX,(%R9,%R8,8)

(609) 0x466b44 MOVQ	$0,(%R12,%RAX,8)

(609) 0x466b4c INC	%RAX

(609) 0x466b4f MOV	%R8,-0x8(%R13,%RAX,8)

(609) 0x466b54 MOV	(%RDX,%RAX,8),%R8

(609) 0x466b58 MOV	%RAX,(%R9,%R8,8)

(609) 0x466b5c MOVQ	$0,(%R12,%RAX,8)

(609) 0x466b64 INC	%RAX

(609) 0x466b67 MOV	%R8,-0x8(%R13,%RAX,8)

(609) 0x466b6c MOV	(%RDX,%RAX,8),%R8

(609) 0x466b70 MOV	%RAX,(%R9,%R8,8)

(609) 0x466b74 MOVQ	$0,(%R12,%RAX,8)

(609) 0x466b7c INC	%RAX

(609) 0x466b7f MOV	%R8,-0x8(%R13,%RAX,8)

(609) 0x466b84 CMP	%RCX,%RAX

(609) 0x466b87 JE	466c66

(609) 0x466b8d MOV	%RBX,-0x38(%RBP)

  (620) 0x466b91 MOV	(%RDX,%RAX,8),%RBX

  (620) 0x466b95 LEA	0x1(%RAX),%R8

  (620) 0x466b99 MOV	%RAX,(%R9,%RBX,8)

  (620) 0x466b9d MOVQ	$0,(%R12,%RAX,8)

  (620) 0x466ba5 MOV	%RBX,-0x8(%R13,%R8,8)

  (620) 0x466baa MOV	(%RDX,%R8,8),%RBX

  (620) 0x466bae MOV	%R8,(%R9,%RBX,8)

  (620) 0x466bb2 MOVQ	$0,(%R12,%R8,8)

  (620) 0x466bba LEA	0x2(%RAX),%R8

  (620) 0x466bbe MOV	%RBX,-0x8(%R13,%R8,8)

  (620) 0x466bc3 MOV	(%RDX,%R8,8),%RBX

  (620) 0x466bc7 MOV	%R8,(%R9,%RBX,8)

  (620) 0x466bcb MOVQ	$0,(%R12,%R8,8)

  (620) 0x466bd3 LEA	0x3(%RAX),%R8

  (620) 0x466bd7 MOV	%RBX,-0x8(%R13,%R8,8)

  (620) 0x466bdc MOV	(%RDX,%R8,8),%RBX

  (620) 0x466be0 MOV	%R8,(%R9,%RBX,8)

  (620) 0x466be4 MOVQ	$0,(%R12,%R8,8)

  (620) 0x466bec LEA	0x4(%RAX),%R8

  (620) 0x466bf0 MOV	%RBX,-0x8(%R13,%R8,8)

  (620) 0x466bf5 MOV	(%RDX,%R8,8),%RBX

  (620) 0x466bf9 MOV	%R8,(%R9,%RBX,8)

  (620) 0x466bfd MOVQ	$0,(%R12,%R8,8)

  (620) 0x466c05 LEA	0x5(%RAX),%R8

  (620) 0x466c09 MOV	%RBX,-0x8(%R13,%R8,8)

  (620) 0x466c0e MOV	(%RDX,%R8,8),%RBX

  (620) 0x466c12 MOV	%R8,(%R9,%RBX,8)

  (620) 0x466c16 MOVQ	$0,(%R12,%R8,8)

  (620) 0x466c1e LEA	0x6(%RAX),%R8

  (620) 0x466c22 MOV	%RBX,-0x8(%R13,%R8,8)

  (620) 0x466c27 MOV	(%RDX,%R8,8),%RBX

  (620) 0x466c2b MOV	%R8,(%R9,%RBX,8)

  (620) 0x466c2f MOVQ	$0,(%R12,%R8,8)

  (620) 0x466c37 LEA	0x7(%RAX),%R8

  (620) 0x466c3b MOV	%RBX,-0x8(%R13,%R8,8)

  (620) 0x466c40 ADD	$0x8,%RAX

  (620) 0x466c44 MOV	(%RDX,%R8,8),%RBX

  (620) 0x466c48 MOV	%R8,(%R9,%RBX,8)

  (620) 0x466c4c MOVQ	$0,(%R12,%R8,8)

  (620) 0x466c54 MOV	%RBX,-0x8(%R13,%RAX,8)

  (620) 0x466c59 CMP	%RCX,%RAX

  (620) 0x466c5c JNE	466b91

(609) 0x466c62 MOV	-0x38(%RBP),%RBX

(609) 0x466c66 MOV	-0x110(%RBP),%RAX

(609) 0x466c6d MOV	-0x48(%RBP),%R8

(609) 0x466c71 MOV	(%RAX,%RDI,8),%RDX

(609) 0x466c75 MOV	-0xb8(%RBP),%RAX

(609) 0x466c7c LEA	(%RAX,%RSI,1),%RCX

(609) 0x466c80 ADD	%R8,%RAX

(609) 0x466c83 MOV	(%RCX),%R8

(609) 0x466c86 MOV	%RAX,-0xe8(%RBP)

(609) 0x466c8d MOV	(%RAX),%RAX

(609) 0x466c90 ADD	%RDX,%R8

(609) 0x466c93 SUB	%RAX,%R8

(609) 0x466c96 MOV	%RCX,-0xe0(%RBP)

(609) 0x466c9d CMP	%R8,%RDX

(609) 0x466ca0 JGE	466e96

(609) 0x466ca6 MOV	%RAX,%RCX

(609) 0x466ca9 SUB	%RDX,%RCX

(609) 0x466cac SUB	%RAX,%RDX

(609) 0x466caf MOV	%RDX,-0x38(%RBP)

(609) 0x466cb3 ADD	%R8,%RCX

(609) 0x466cb6 MOV	-0xb0(%RBP),%RDX

(609) 0x466cbd MOV	-0x148(%RBP),%R8

(609) 0x466cc4 MOV	(%R8,%RDX,1),%R8

(609) 0x466cc8 MOV	-0x38(%RBP),%RDX

(609) 0x466ccc LEA	(%R8,%RDX,8),%RDX

(609) 0x466cd0 MOV	%RCX,%R8

(609) 0x466cd3 SUB	%RAX,%R8

(609) 0x466cd6 AND	$0x7,%R8D

(609) 0x466cda JE	466dbd

(609) 0x466ce0 CMP	$0x1,%R8

(609) 0x466ce4 JE	466d9c

(609) 0x466cea CMP	$0x2,%R8

(609) 0x466cee JE	466d84

(609) 0x466cf4 CMP	$0x3,%R8

(609) 0x466cf8 JE	466d6c

(609) 0x466cfa CMP	$0x4,%R8

(609) 0x466cfe JE	466d54

(609) 0x466d00 CMP	$0x5,%R8

(609) 0x466d04 JE	466d3c

(609) 0x466d06 CMP	$0x6,%R8

(609) 0x466d0a JE	466d24

(609) 0x466d0c MOV	(%RDX,%RAX,8),%R8

(609) 0x466d10 MOV	%RAX,(%RBX,%R8,8)

(609) 0x466d14 MOVQ	$0,(%R11,%RAX,8)

(609) 0x466d1c INC	%RAX

(609) 0x466d1f MOV	%R8,-0x8(%R10,%RAX,8)

(609) 0x466d24 MOV	(%RDX,%RAX,8),%R8

(609) 0x466d28 MOV	%RAX,(%RBX,%R8,8)

(609) 0x466d2c MOVQ	$0,(%R11,%RAX,8)

(609) 0x466d34 INC	%RAX

(609) 0x466d37 MOV	%R8,-0x8(%R10,%RAX,8)

(609) 0x466d3c MOV	(%RDX,%RAX,8),%R8

(609) 0x466d40 MOV	%RAX,(%RBX,%R8,8)

(609) 0x466d44 MOVQ	$0,(%R11,%RAX,8)

(609) 0x466d4c INC	%RAX

(609) 0x466d4f MOV	%R8,-0x8(%R10,%RAX,8)

(609) 0x466d54 MOV	(%RDX,%RAX,8),%R8

(609) 0x466d58 MOV	%RAX,(%RBX,%R8,8)

(609) 0x466d5c MOVQ	$0,(%R11,%RAX,8)

(609) 0x466d64 INC	%RAX

(609) 0x466d67 MOV	%R8,-0x8(%R10,%RAX,8)

(609) 0x466d6c MOV	(%RDX,%RAX,8),%R8

(609) 0x466d70 MOV	%RAX,(%RBX,%R8,8)

(609) 0x466d74 MOVQ	$0,(%R11,%RAX,8)

(609) 0x466d7c INC	%RAX

(609) 0x466d7f MOV	%R8,-0x8(%R10,%RAX,8)

(609) 0x466d84 MOV	(%RDX,%RAX,8),%R8

(609) 0x466d88 MOV	%RAX,(%RBX,%R8,8)

(609) 0x466d8c MOVQ	$0,(%R11,%RAX,8)

(609) 0x466d94 INC	%RAX

(609) 0x466d97 MOV	%R8,-0x8(%R10,%RAX,8)

(609) 0x466d9c MOV	(%RDX,%RAX,8),%R8

(609) 0x466da0 MOV	%RAX,(%RBX,%R8,8)

(609) 0x466da4 MOVQ	$0,(%R11,%RAX,8)

(609) 0x466dac INC	%RAX

(609) 0x466daf MOV	%R8,-0x8(%R10,%RAX,8)

(609) 0x466db4 CMP	%RCX,%RAX

(609) 0x466db7 JE	466e96

(609) 0x466dbd MOV	%R9,-0x38(%RBP)

  (619) 0x466dc1 MOV	(%RDX,%RAX,8),%R9

  (619) 0x466dc5 LEA	0x1(%RAX),%R8

  (619) 0x466dc9 MOV	%RAX,(%RBX,%R9,8)

  (619) 0x466dcd MOVQ	$0,(%R11,%RAX,8)

  (619) 0x466dd5 MOV	%R9,-0x8(%R10,%R8,8)

  (619) 0x466dda MOV	(%RDX,%R8,8),%R9

  (619) 0x466dde MOV	%R8,(%RBX,%R9,8)

  (619) 0x466de2 MOVQ	$0,(%R11,%R8,8)

  (619) 0x466dea LEA	0x2(%RAX),%R8

  (619) 0x466dee MOV	%R9,-0x8(%R10,%R8,8)

  (619) 0x466df3 MOV	(%RDX,%R8,8),%R9

  (619) 0x466df7 MOV	%R8,(%RBX,%R9,8)

  (619) 0x466dfb MOVQ	$0,(%R11,%R8,8)

  (619) 0x466e03 LEA	0x3(%RAX),%R8

  (619) 0x466e07 MOV	%R9,-0x8(%R10,%R8,8)

  (619) 0x466e0c MOV	(%RDX,%R8,8),%R9

  (619) 0x466e10 MOV	%R8,(%RBX,%R9,8)

  (619) 0x466e14 MOVQ	$0,(%R11,%R8,8)

  (619) 0x466e1c LEA	0x4(%RAX),%R8

  (619) 0x466e20 MOV	%R9,-0x8(%R10,%R8,8)

  (619) 0x466e25 MOV	(%RDX,%R8,8),%R9

  (619) 0x466e29 MOV	%R8,(%RBX,%R9,8)

  (619) 0x466e2d MOVQ	$0,(%R11,%R8,8)

  (619) 0x466e35 LEA	0x5(%RAX),%R8

  (619) 0x466e39 MOV	%R9,-0x8(%R10,%R8,8)

  (619) 0x466e3e MOV	(%RDX,%R8,8),%R9

  (619) 0x466e42 MOV	%R8,(%RBX,%R9,8)

  (619) 0x466e46 MOVQ	$0,(%R11,%R8,8)

  (619) 0x466e4e LEA	0x6(%RAX),%R8

  (619) 0x466e52 MOV	%R9,-0x8(%R10,%R8,8)

  (619) 0x466e57 MOV	(%RDX,%R8,8),%R9

  (619) 0x466e5b MOV	%R8,(%RBX,%R9,8)

  (619) 0x466e5f MOVQ	$0,(%R11,%R8,8)

  (619) 0x466e67 LEA	0x7(%RAX),%R8

  (619) 0x466e6b MOV	%R9,-0x8(%R10,%R8,8)

  (619) 0x466e70 ADD	$0x8,%RAX

  (619) 0x466e74 MOV	(%RDX,%R8,8),%R9

  (619) 0x466e78 MOV	%R8,(%RBX,%R9,8)

  (619) 0x466e7c MOVQ	$0,(%R11,%R8,8)

  (619) 0x466e84 MOV	%R9,-0x8(%R10,%RAX,8)

  (619) 0x466e89 CMP	%RCX,%RAX

  (619) 0x466e8c JNE	466dc1

(609) 0x466e92 MOV	-0x38(%RBP),%R9

(609) 0x466e96 MOV	-0x128(%RBP),%RCX

(609) 0x466e9d LEA	(%RCX,%RSI,1),%R8

(609) 0x466ea1 MOV	(%RCX,%RDI,8),%RAX

(609) 0x466ea5 MOV	(%R8),%RCX

(609) 0x466ea8 CMP	%RCX,%RAX

(609) 0x466eab JGE	466ee2

(609) 0x466ead MOV	%RSI,-0x38(%RBP)

(609) 0x466eb1 NOPW	%CS:(%RAX,%RAX,1)

(609) 0x466ebc NOPL	(%RAX)

  (618) 0x466ec0 MOV	-0x70(%RBP),%RSI

  (618) 0x466ec4 MOV	(%RSI,%RAX,8),%RDX

  (618) 0x466ec8 MOV	-0x60(%RBP),%RSI

  (618) 0x466ecc CMP	%R14,(%RSI,%RDX,8)

  (618) 0x466ed0 JE	4670e8

  (618) 0x466ed6 INC	%RAX

  (618) 0x466ed9 CMP	%RCX,%RAX

  (618) 0x466edc JL	466ec0

(609) 0x466ede MOV	-0x38(%RBP),%RSI

(609) 0x466ee2 MOV	-0x120(%RBP),%R8

(609) 0x466ee9 ADD	%R8,%RSI

(609) 0x466eec MOV	(%R8,%RDI,8),%RAX

(609) 0x466ef0 MOV	(%RSI),%RCX

(609) 0x466ef3 CMP	%RCX,%RAX

(609) 0x466ef6 JGE	466f1e

(609) 0x466ef8 NOPL	(%RAX,%RAX,1)

  (617) 0x466f00 MOV	-0x68(%RBP),%RDX

  (617) 0x466f04 MOV	-0x58(%RBP),%R8

  (617) 0x466f08 MOV	(%RDX,%RAX,8),%RDX

  (617) 0x466f0c CMP	%R14,(%R8,%RDX,8)

  (617) 0x466f10 JE	467108

  (617) 0x466f16 INC	%RAX

  (617) 0x466f19 CMP	%RCX,%RAX

  (617) 0x466f1c JL	466f00

(609) 0x466f1e MOV	-0x138(%RBP),%RSI

(609) 0x466f25 MOV	-0x48(%RBP),%RDX

(609) 0x466f29 MOV	(%RSI,%RDI,8),%R8

(609) 0x466f2d MOV	0x8(%RSI,%RDX,1),%RDX

(609) 0x466f32 LEA	0x1(%R8),%RAX

(609) 0x466f36 CMP	%RDX,%RAX

(609) 0x466f39 JGE	4679ec

(609) 0x466f3f MOV	-0x170(%RBP),%RCX

(609) 0x466f46 SAL	$0x3,%RAX

(609) 0x466f4a LEA	(%RCX,%RAX,1),%RSI

(609) 0x466f4e MOV	%RSI,-0xa8(%RBP)

(609) 0x466f55 MOV	-0xc8(%RBP),%RSI

(609) 0x466f5c LEA	(%RCX,%RDX,8),%RDX

(609) 0x466f60 VXORPD	%XMM0,%XMM0,%XMM0

(609) 0x466f64 ADD	%RSI,%RAX

(609) 0x466f67 MOV	%RDX,-0x38(%RBP)

(609) 0x466f6b MOV	%R15,-0xf0(%RBP)

(609) 0x466f72 MOV	%R8,-0xf8(%RBP)

(609) 0x466f79 MOV	%R14,-0x100(%RBP)

(609) 0x466f80 MOV	-0xa8(%RBP),%RSI

(609) 0x466f87 VMOVAPD	%XMM0,%XMM1

(609) 0x466f8b JMP	466fb3

0x466f8d NOPL	(%RAX)

  (614) 0x466f90 MOV	-0x88(%RBP),%RDX

  (614) 0x466f97 MOV	-0x48(%RBP),%R8

  (614) 0x466f9b MOV	(%RDX,%RCX,8),%RCX

  (614) 0x466f9f CMP	%RCX,(%RDX,%R8,1)

  (614) 0x466fa3 JE	466fde

  (614) 0x466fa5 ADD	$0x8,%RSI

  (614) 0x466fa9 ADD	$0x8,%RAX

  (614) 0x466fad CMP	%RSI,-0x38(%RBP)

  (614) 0x466fb1 JE	466ff0

  (614) 0x466fb3 MOV	(%RSI),%RCX

  (614) 0x466fb6 MOV	-0x40(%RBP),%R15

  (614) 0x466fba LEA	(,%RCX,8),%R8

  (614) 0x466fc2 CMP	(%R15,%RCX,8),%RDI

  (614) 0x466fc6 JE	467128

  (614) 0x466fcc MOV	-0x80(%RBP),%R14

  (614) 0x466fd0 CMPQ	$-0x3,(%R14,%RCX,8)

  (614) 0x466fd5 JE	466fa5

  (614) 0x466fd7 CMPQ	$0x1,-0x50(%RBP)

  (614) 0x466fdc JNE	466f90

  (614) 0x466fde ADD	$0x8,%RSI

  (614) 0x466fe2 VADDSD	(%RAX),%XMM0,%XMM0

  (614) 0x466fe6 ADD	$0x8,%RAX

  (614) 0x466fea CMP	%RSI,-0x38(%RBP)

  (614) 0x466fee JNE	466fb3

(609) 0x466ff0 MOV	-0xf0(%RBP),%R15

(609) 0x466ff7 MOV	-0xf8(%RBP),%R8

(609) 0x466ffe MOV	-0x100(%RBP),%R14

(609) 0x467005 MOV	-0x130(%RBP),%RCX

(609) 0x46700c MOV	-0x48(%RBP),%RAX

(609) 0x467010 MOV	(%RCX,%RDI,8),%RDX

(609) 0x467014 MOV	0x8(%RCX,%RAX,1),%RCX

(609) 0x467019 CMP	%RCX,%RDX

(609) 0x46701c JGE	467438

(609) 0x467022 MOV	-0x160(%RBP),%RAX

(609) 0x467029 SAL	$0x3,%RDX

(609) 0x46702d LEA	(%RAX,%RDX,1),%RSI

(609) 0x467031 MOV	%RSI,-0x38(%RBP)

(609) 0x467035 MOV	-0x168(%RBP),%RSI

(609) 0x46703c MOV	%R10,-0xf0(%RBP)

(609) 0x467043 ADD	%RSI,%RDX

(609) 0x467046 MOV	%R13,-0xf8(%RBP)

(609) 0x46704d LEA	(%RAX,%RCX,8),%RSI

(609) 0x467051 MOV	%R8,-0x100(%RBP)

(609) 0x467058 MOV	%R14,%RAX

(609) 0x46705b MOV	-0x158(%RBP),%R14

(609) 0x467062 JMP	46709a

0x467064 NOPL	(%RAX)

  (612) 0x467068 MOV	-0x88(%RBP),%R10

  (612) 0x46706f MOV	-0x48(%RBP),%R13

  (612) 0x467073 MOV	-0xa0(%RBP),%RCX

  (612) 0x46707a MOV	(%R10,%R13,1),%R10

  (612) 0x46707e CMP	%R10,(%RCX,%R8,1)

  (612) 0x467082 JE	4670dc

  (612) 0x467084 ADDQ	$0x8,-0x38(%RBP)

  (612) 0x467089 ADD	$0x8,%RDX

  (612) 0x46708d MOV	-0x38(%RBP),%RCX

  (612) 0x467091 CMP	%RCX,%RSI

  (612) 0x467094 JE	467420

  (612) 0x46709a MOV	-0x38(%RBP),%R13

  (612) 0x46709e MOV	(%R13),%RCX

  (612) 0x4670a2 TEST	%R15,%R15

  (612) 0x4670a5 JE	4670b2

  (612) 0x4670a7 MOV	-0x90(%RBP),%R10

  (612) 0x4670ae MOV	(%R10,%RCX,8),%RCX

  (612) 0x4670b2 LEA	(,%RCX,8),%R8

  (612) 0x4670ba TEST	%RCX,%RCX

  (612) 0x4670bd JS	4670ce

  (612) 0x4670bf MOV	-0x78(%RBP),%R13

  (612) 0x4670c3 CMP	(%R13,%RCX,8),%RDI

  (612) 0x4670c8 JE	467700

  (612) 0x4670ce CMPQ	$-0x3,(%R14,%R8,1)

  (612) 0x4670d3 JE	467084

  (612) 0x4670d5 CMPQ	$0x1,-0x50(%RBP)

  (612) 0x4670da JNE	467068

  (612) 0x4670dc VADDSD	(%RDX),%XMM0,%XMM0

  (612) 0x4670e0 JMP	467084

0x4670e2 NOPW	(%RAX,%RAX,1)

  (618) 0x4670e8 MOV	-0x40(%RBP),%RCX

  (618) 0x4670ec INC	%RAX

  (618) 0x4670ef MOV	%RDI,(%RCX,%RDX,8)

  (618) 0x4670f3 MOV	(%R8),%RCX

  (618) 0x4670f6 CMP	%RAX,%RCX

  (618) 0x4670f9 JG	466ec0

(609) 0x4670ff JMP	466ede

0x467104 NOPL	(%RAX)

  (617) 0x467108 MOV	-0x78(%RBP),%RCX

  (617) 0x46710c INC	%RAX

  (617) 0x46710f MOV	%RDI,(%RCX,%RDX,8)

  (617) 0x467113 MOV	(%RSI),%RCX

  (617) 0x467116 CMP	%RAX,%RCX

  (617) 0x467119 JG	466f00

(609) 0x46711f JMP	466f1e

0x467124 NOPL	(%RAX)

  (614) 0x467128 MOV	-0xc0(%RBP),%R15

  (614) 0x46712f MOV	(%R15,%RCX,8),%RDX

  (614) 0x467133 MOV	0x8(%R15,%R8,1),%R15

  (614) 0x467138 CMP	%R15,%RDX

  (614) 0x46713b JGE	4672aa

  (614) 0x467141 MOV	%R15,%R14

  (614) 0x467144 SUB	%RDX,%R14

  (614) 0x467147 AND	$0x3,%R14D

  (614) 0x46714b JE	4671ee

  (614) 0x467151 CMP	$0x1,%R14

  (614) 0x467155 JE	4671b7

  (614) 0x467157 CMP	$0x2,%R14

  (614) 0x46715b JE	467189

  (614) 0x46715d VMOVSD	(%RAX),%XMM5

  (614) 0x467161 MOV	(%R13,%RDX,8),%R14

  (614) 0x467166 VMULSD	(%R12,%RDX,8),%XMM5,%XMM6

  (614) 0x46716c MOV	(%R9,%R14,8),%R14

  (614) 0x467170 INC	%RDX

  (614) 0x467173 LEA	(%R12,%R14,8),%R14

  (614) 0x467177 VADDSD	(%R14),%XMM6,%XMM7

  (614) 0x46717c VADDSD	%XMM6,%XMM1,%XMM1

  (614) 0x467180 VADDSD	%XMM6,%XMM0,%XMM0

  (614) 0x467184 VMOVSD	%XMM7,(%R14)

  (614) 0x467189 VMOVSD	(%RAX),%XMM8

  (614) 0x46718d MOV	(%R13,%RDX,8),%R14

  (614) 0x467192 VMULSD	(%R12,%RDX,8),%XMM8,%XMM9

  (614) 0x467198 MOV	(%R9,%R14,8),%R14

  (614) 0x46719c INC	%RDX

  (614) 0x46719f LEA	(%R12,%R14,8),%R14

  (614) 0x4671a3 VADDSD	(%R14),%XMM9,%XMM10

  (614) 0x4671a8 VADDSD	%XMM9,%XMM1,%XMM1

  (614) 0x4671ad VADDSD	%XMM9,%XMM0,%XMM0

  (614) 0x4671b2 VMOVSD	%XMM10,(%R14)

  (614) 0x4671b7 VMOVSD	(%RAX),%XMM11

  (614) 0x4671bb MOV	(%R13,%RDX,8),%R14

  (614) 0x4671c0 VMULSD	(%R12,%RDX,8),%XMM11,%XMM12

  (614) 0x4671c6 MOV	(%R9,%R14,8),%R14

  (614) 0x4671ca INC	%RDX

  (614) 0x4671cd LEA	(%R12,%R14,8),%R14

  (614) 0x4671d1 VADDSD	(%R14),%XMM12,%XMM13

  (614) 0x4671d6 VADDSD	%XMM12,%XMM1,%XMM1

  (614) 0x4671db VADDSD	%XMM12,%XMM0,%XMM0

  (614) 0x4671e0 VMOVSD	%XMM13,(%R14)

  (614) 0x4671e5 CMP	%R15,%RDX

  (614) 0x4671e8 JE	4672aa

    (616) 0x4671ee VMOVSD	(%RAX),%XMM14

    (616) 0x4671f2 MOV	(%R13,%RDX,8),%R14

    (616) 0x4671f7 VMULSD	(%R12,%RDX,8),%XMM14,%XMM15

    (616) 0x4671fd MOV	(%R9,%R14,8),%R14

    (616) 0x467201 LEA	(%R12,%R14,8),%R14

    (616) 0x467205 VADDSD	(%R14),%XMM15,%XMM2

    (616) 0x46720a VADDSD	%XMM15,%XMM1,%XMM6

    (616) 0x46720f VADDSD	%XMM15,%XMM0,%XMM7

    (616) 0x467214 VMOVSD	%XMM2,(%R14)

    (616) 0x467219 VMOVSD	(%RAX),%XMM5

    (616) 0x46721d MOV	0x8(%R13,%RDX,8),%R14

    (616) 0x467222 VMULSD	0x8(%R12,%RDX,8),%XMM5,%XMM8

    (616) 0x467229 MOV	(%R9,%R14,8),%R14

    (616) 0x46722d LEA	(%R12,%R14,8),%R14

    (616) 0x467231 VADDSD	(%R14),%XMM8,%XMM9

    (616) 0x467236 VADDSD	%XMM8,%XMM6,%XMM10

    (616) 0x46723b VADDSD	%XMM8,%XMM7,%XMM11

    (616) 0x467240 VMOVSD	%XMM9,(%R14)

    (616) 0x467245 VMOVSD	(%RAX),%XMM12

    (616) 0x467249 MOV	0x10(%R13,%RDX,8),%R14

    (616) 0x46724e VMULSD	0x10(%R12,%RDX,8),%XMM12,%XMM13

    (616) 0x467255 MOV	(%R9,%R14,8),%R14

    (616) 0x467259 LEA	(%R12,%R14,8),%R14

    (616) 0x46725d VADDSD	(%R14),%XMM13,%XMM1

    (616) 0x467262 VADDSD	%XMM13,%XMM10,%XMM14

    (616) 0x467267 VADDSD	%XMM13,%XMM11,%XMM0

    (616) 0x46726c VMOVSD	%XMM1,(%R14)

    (616) 0x467271 VMOVSD	(%RAX),%XMM15

    (616) 0x467275 MOV	0x18(%R13,%RDX,8),%R14

    (616) 0x46727a VMULSD	0x18(%R12,%RDX,8),%XMM15,%XMM12

    (616) 0x467281 MOV	(%R9,%R14,8),%R14

    (616) 0x467285 ADD	$0x4,%RDX

    (616) 0x467289 LEA	(%R12,%R14,8),%R14

    (616) 0x46728d VADDSD	(%R14),%XMM12,%XMM2

    (616) 0x467292 VADDSD	%XMM12,%XMM14,%XMM1

    (616) 0x467297 VADDSD	%XMM12,%XMM0,%XMM0

    (616) 0x46729c VMOVSD	%XMM2,(%R14)

    (616) 0x4672a1 CMP	%R15,%RDX

    (616) 0x4672a4 JNE	4671ee

  (614) 0x4672aa MOV	-0xb8(%RBP),%R15

  (614) 0x4672b1 MOV	(%R15,%RCX,8),%RDX

  (614) 0x4672b5 MOV	0x8(%R15,%R8,1),%R8

  (614) 0x4672ba CMP	%R8,%RDX

  (614) 0x4672bd JGE	466fa5

  (614) 0x4672c3 MOV	%R8,%RCX

  (614) 0x4672c6 SUB	%RDX,%RCX

  (614) 0x4672c9 AND	$0x3,%ECX

  (614) 0x4672cc JE	467366

  (614) 0x4672d2 CMP	$0x1,%RCX

  (614) 0x4672d6 JE	467332

  (614) 0x4672d8 CMP	$0x2,%RCX

  (614) 0x4672dc JE	467307

  (614) 0x4672de VMOVSD	(%RAX),%XMM6

  (614) 0x4672e2 MOV	(%R10,%RDX,8),%R14

  (614) 0x4672e6 VMULSD	(%R11,%RDX,8),%XMM6,%XMM7

  (614) 0x4672ec MOV	(%RBX,%R14,8),%R15

  (614) 0x4672f0 INC	%RDX

  (614) 0x4672f3 LEA	(%R11,%R15,8),%RCX

  (614) 0x4672f7 VADDSD	(%RCX),%XMM7,%XMM5

  (614) 0x4672fb VADDSD	%XMM7,%XMM1,%XMM1

  (614) 0x4672ff VADDSD	%XMM7,%XMM0,%XMM0

  (614) 0x467303 VMOVSD	%XMM5,(%RCX)

  (614) 0x467307 VMOVSD	(%RAX),%XMM8

  (614) 0x46730b MOV	(%R10,%RDX,8),%R14

  (614) 0x46730f VMULSD	(%R11,%RDX,8),%XMM8,%XMM9

  (614) 0x467315 MOV	(%RBX,%R14,8),%R15

  (614) 0x467319 INC	%RDX

  (614) 0x46731c LEA	(%R11,%R15,8),%RCX

  (614) 0x467320 VADDSD	(%RCX),%XMM9,%XMM10

  (614) 0x467324 VADDSD	%XMM9,%XMM1,%XMM1

  (614) 0x467329 VADDSD	%XMM9,%XMM0,%XMM0

  (614) 0x46732e VMOVSD	%XMM10,(%RCX)

  (614) 0x467332 VMOVSD	(%RAX),%XMM11

  (614) 0x467336 MOV	(%R10,%RDX,8),%R14

  (614) 0x46733a VMULSD	(%R11,%RDX,8),%XMM11,%XMM12

  (614) 0x467340 MOV	(%RBX,%R14,8),%R15

  (614) 0x467344 INC	%RDX

  (614) 0x467347 LEA	(%R11,%R15,8),%RCX

  (614) 0x46734b VADDSD	(%RCX),%XMM12,%XMM13

  (614) 0x46734f VADDSD	%XMM12,%XMM1,%XMM1

  (614) 0x467354 VADDSD	%XMM12,%XMM0,%XMM0

  (614) 0x467359 VMOVSD	%XMM13,(%RCX)

  (614) 0x46735d CMP	%R8,%RDX

  (614) 0x467360 JE	466fa5

    (615) 0x467366 VMOVSD	(%RAX),%XMM12

    (615) 0x46736a MOV	(%R10,%RDX,8),%R14

    (615) 0x46736e VMULSD	(%R11,%RDX,8),%XMM12,%XMM14

    (615) 0x467374 MOV	(%RBX,%R14,8),%R15

    (615) 0x467378 MOV	0x8(%R10,%RDX,8),%R14

    (615) 0x46737d LEA	(%R11,%R15,8),%RCX

    (615) 0x467381 MOV	(%RBX,%R14,8),%R15

    (615) 0x467385 VADDSD	(%RCX),%XMM14,%XMM15

    (615) 0x467389 MOV	0x10(%R10,%RDX,8),%R14

    (615) 0x46738e VADDSD	%XMM14,%XMM1,%XMM1

    (615) 0x467393 VMOVSD	%XMM15,(%RCX)

    (615) 0x467397 VMOVSD	(%RAX),%XMM2

    (615) 0x46739b LEA	(%R11,%R15,8),%RCX

    (615) 0x46739f VMULSD	0x8(%R11,%RDX,8),%XMM2,%XMM6

    (615) 0x4673a6 MOV	(%RBX,%R14,8),%R15

    (615) 0x4673aa VADDSD	%XMM14,%XMM0,%XMM0

    (615) 0x4673af MOV	0x18(%R10,%RDX,8),%R14

    (615) 0x4673b4 VADDSD	(%RCX),%XMM6,%XMM7

    (615) 0x4673b8 VADDSD	%XMM6,%XMM1,%XMM8

    (615) 0x4673bc VADDSD	%XMM6,%XMM0,%XMM9

    (615) 0x4673c0 VMOVSD	%XMM7,(%RCX)

    (615) 0x4673c4 VMOVSD	(%RAX),%XMM5

    (615) 0x4673c8 LEA	(%R11,%R15,8),%RCX

    (615) 0x4673cc VMULSD	0x10(%R11,%RDX,8),%XMM5,%XMM10

    (615) 0x4673d3 MOV	(%RBX,%R14,8),%R15

    (615) 0x4673d7 VADDSD	(%RCX),%XMM10,%XMM11

    (615) 0x4673db VADDSD	%XMM10,%XMM8,%XMM13

    (615) 0x4673e0 VADDSD	%XMM10,%XMM9,%XMM14

    (615) 0x4673e5 VMOVSD	%XMM11,(%RCX)

    (615) 0x4673e9 VMOVSD	(%RAX),%XMM12

    (615) 0x4673ed LEA	(%R11,%R15,8),%RCX

    (615) 0x4673f1 VMULSD	0x18(%R11,%RDX,8),%XMM12,%XMM12

    (615) 0x4673f8 ADD	$0x4,%RDX

    (615) 0x4673fc VADDSD	(%RCX),%XMM12,%XMM15

    (615) 0x467400 VADDSD	%XMM12,%XMM13,%XMM1

    (615) 0x467405 VADDSD	%XMM12,%XMM14,%XMM0

    (615) 0x46740a VMOVSD	%XMM15,(%RCX)

    (615) 0x46740e CMP	%R8,%RDX

    (615) 0x467411 JNE	467366

  (614) 0x467417 JMP	466fa5

0x46741c NOPL	(%RAX)

(609) 0x467420 MOV	-0xf0(%RBP),%R10

(609) 0x467427 MOV	-0xf8(%RBP),%R13

(609) 0x46742e MOV	-0x100(%RBP),%R8

(609) 0x467435 MOV	%RAX,%R14

(609) 0x467438 MOV	-0xc8(%RBP),%RDI

(609) 0x46743f VMULSD	(%RDI,%R8,8),%XMM1,%XMM9

(609) 0x467445 VCOMISD	%XMM3,%XMM9

(609) 0x467449 JE	467454

(609) 0x46744b VXORPD	%XMM4,%XMM0,%XMM10

(609) 0x46744f VDIVSD	%XMM9,%XMM10,%XMM12

(609) 0x467454 MOV	-0xd8(%RBP),%R8

(609) 0x46745b MOV	-0xd0(%RBP),%RDX

(609) 0x467462 MOV	(%R8),%RAX

(609) 0x467465 MOV	(%RDX),%RSI

(609) 0x467468 CMP	%RSI,%RAX

(609) 0x46746b JGE	46756f

(609) 0x467471 LEA	(%R12,%RSI,8),%RCX

(609) 0x467475 LEA	(%R12,%RAX,8),%RDI

(609) 0x467479 MOV	%RCX,%R8

(609) 0x46747c SUB	%RDI,%R8

(609) 0x46747f SUB	$0x8,%R8

(609) 0x467483 SHR	$0x3,%R8

(609) 0x467487 INC	%R8

(609) 0x46748a AND	$0x7,%R8D

(609) 0x46748e JE	467518

(609) 0x467494 CMP	$0x1,%R8

(609) 0x467498 JE	467506

(609) 0x46749a CMP	$0x2,%R8

(609) 0x46749e JE	4674f9

(609) 0x4674a0 CMP	$0x3,%R8

(609) 0x4674a4 JE	4674ec

(609) 0x4674a6 CMP	$0x4,%R8

(609) 0x4674aa JE	4674df

(609) 0x4674ac CMP	$0x5,%R8

(609) 0x4674b0 JE	4674d2

(609) 0x4674b2 CMP	$0x6,%R8

(609) 0x4674b6 JE	4674c5

(609) 0x4674b8 VMULSD	(%RDI),%XMM12,%XMM5

(609) 0x4674bc ADD	$0x8,%RDI

(609) 0x4674c0 VMOVSD	%XMM5,-0x8(%RDI)

(609) 0x4674c5 VMULSD	(%RDI),%XMM12,%XMM11

(609) 0x4674c9 ADD	$0x8,%RDI

(609) 0x4674cd VMOVSD	%XMM11,-0x8(%RDI)

(609) 0x4674d2 VMULSD	(%RDI),%XMM12,%XMM13

(609) 0x4674d6 ADD	$0x8,%RDI

(609) 0x4674da VMOVSD	%XMM13,-0x8(%RDI)

(609) 0x4674df VMULSD	(%RDI),%XMM12,%XMM14

(609) 0x4674e3 ADD	$0x8,%RDI

(609) 0x4674e7 VMOVSD	%XMM14,-0x8(%RDI)

(609) 0x4674ec VMULSD	(%RDI),%XMM12,%XMM15

(609) 0x4674f0 ADD	$0x8,%RDI

(609) 0x4674f4 VMOVSD	%XMM15,-0x8(%RDI)

(609) 0x4674f9 VMULSD	(%RDI),%XMM12,%XMM2

(609) 0x4674fd ADD	$0x8,%RDI

(609) 0x467501 VMOVSD	%XMM2,-0x8(%RDI)

(609) 0x467506 VMULSD	(%RDI),%XMM12,%XMM6

(609) 0x46750a ADD	$0x8,%RDI

(609) 0x46750e VMOVSD	%XMM6,-0x8(%RDI)

(609) 0x467513 CMP	%RCX,%RDI

(609) 0x467516 JE	46756f

  (611) 0x467518 VMULSD	(%RDI),%XMM12,%XMM7

  (611) 0x46751c VMULSD	0x8(%RDI),%XMM12,%XMM1

  (611) 0x467521 VMULSD	0x10(%RDI),%XMM12,%XMM0

  (611) 0x467526 VMULSD	0x18(%RDI),%XMM12,%XMM8

  (611) 0x46752b VMULSD	0x20(%RDI),%XMM12,%XMM9

  (611) 0x467530 VMULSD	0x28(%RDI),%XMM12,%XMM10

  (611) 0x467535 VMULSD	0x30(%RDI),%XMM12,%XMM5

  (611) 0x46753a VMULSD	0x38(%RDI),%XMM12,%XMM11

  (611) 0x46753f VMOVSD	%XMM7,(%RDI)

  (611) 0x467543 VMOVSD	%XMM1,0x8(%RDI)

  (611) 0x467548 VMOVSD	%XMM0,0x10(%RDI)

  (611) 0x46754d VMOVSD	%XMM8,0x18(%RDI)

  (611) 0x467552 VMOVSD	%XMM9,0x20(%RDI)

  (611) 0x467557 VMOVSD	%XMM10,0x28(%RDI)

  (611) 0x46755c VMOVSD	%XMM5,0x30(%RDI)

  (611) 0x467561 VMOVSD	%XMM11,0x38(%RDI)

  (611) 0x467566 ADD	$0x40,%RDI

  (611) 0x46756a CMP	%RCX,%RDI

  (611) 0x46756d JNE	467518

(609) 0x46756f MOV	-0xe8(%RBP),%RAX

(609) 0x467576 MOV	-0xe0(%RBP),%RDX

(609) 0x46757d MOV	(%RAX),%RSI

(609) 0x467580 MOV	(%RDX),%RDI

(609) 0x467583 CMP	%RDI,%RSI

(609) 0x467586 JGE	4676a7

(609) 0x46758c LEA	(%R11,%RDI,8),%RCX

(609) 0x467590 LEA	(%R11,%RSI,8),%R8

(609) 0x467594 MOV	%RCX,%RAX

(609) 0x467597 SUB	%R8,%RAX

(609) 0x46759a SUB	$0x8,%RAX

(609) 0x46759e SHR	$0x3,%RAX

(609) 0x4675a2 INC	%RAX

(609) 0x4675a5 AND	$0x7,%EAX

(609) 0x4675a8 JE	467640

(609) 0x4675ae CMP	$0x1,%RAX

(609) 0x4675b2 JE	46762c

(609) 0x4675b4 CMP	$0x2,%RAX

(609) 0x4675b8 JE	46761d

(609) 0x4675ba CMP	$0x3,%RAX

(609) 0x4675be JE	46760e

(609) 0x4675c0 CMP	$0x4,%RAX

(609) 0x4675c4 JE	4675ff

(609) 0x4675c6 CMP	$0x5,%RAX

(609) 0x4675ca JE	4675f0

(609) 0x4675cc CMP	$0x6,%RAX

(609) 0x4675d0 JE	4675e1

(609) 0x4675d2 VMULSD	(%R8),%XMM12,%XMM13

(609) 0x4675d7 ADD	$0x8,%R8

(609) 0x4675db VMOVSD	%XMM13,-0x8(%R8)

(609) 0x4675e1 VMULSD	(%R8),%XMM12,%XMM14

(609) 0x4675e6 ADD	$0x8,%R8

(609) 0x4675ea VMOVSD	%XMM14,-0x8(%R8)

(609) 0x4675f0 VMULSD	(%R8),%XMM12,%XMM15

(609) 0x4675f5 ADD	$0x8,%R8

(609) 0x4675f9 VMOVSD	%XMM15,-0x8(%R8)

(609) 0x4675ff VMULSD	(%R8),%XMM12,%XMM2

(609) 0x467604 ADD	$0x8,%R8

(609) 0x467608 VMOVSD	%XMM2,-0x8(%R8)

(609) 0x46760e VMULSD	(%R8),%XMM12,%XMM6

(609) 0x467613 ADD	$0x8,%R8

(609) 0x467617 VMOVSD	%XMM6,-0x8(%R8)

(609) 0x46761d VMULSD	(%R8),%XMM12,%XMM7

(609) 0x467622 ADD	$0x8,%R8

(609) 0x467626 VMOVSD	%XMM7,-0x8(%R8)

(609) 0x46762c VMULSD	(%R8),%XMM12,%XMM1

(609) 0x467631 ADD	$0x8,%R8

(609) 0x467635 VMOVSD	%XMM1,-0x8(%R8)

(609) 0x46763b CMP	%R8,%RCX

(609) 0x46763e JE	4676a7

  (610) 0x467640 VMULSD	(%R8),%XMM12,%XMM0

  (610) 0x467645 VMULSD	0x8(%R8),%XMM12,%XMM8

  (610) 0x46764b VMULSD	0x10(%R8),%XMM12,%XMM9

  (610) 0x467651 VMULSD	0x18(%R8),%XMM12,%XMM10

  (610) 0x467657 VMULSD	0x20(%R8),%XMM12,%XMM5

  (610) 0x46765d VMULSD	0x28(%R8),%XMM12,%XMM11

  (610) 0x467663 VMULSD	0x30(%R8),%XMM12,%XMM13

  (610) 0x467669 VMULSD	0x38(%R8),%XMM12,%XMM14

  (610) 0x46766f VMOVSD	%XMM0,(%R8)

  (610) 0x467674 VMOVSD	%XMM8,0x8(%R8)

  (610) 0x46767a VMOVSD	%XMM9,0x10(%R8)

  (610) 0x467680 VMOVSD	%XMM10,0x18(%R8)

  (610) 0x467686 VMOVSD	%XMM5,0x20(%R8)

  (610) 0x46768c VMOVSD	%XMM11,0x28(%R8)

  (610) 0x467692 VMOVSD	%XMM13,0x30(%R8)

  (610) 0x467698 VMOVSD	%XMM14,0x38(%R8)

  (610) 0x46769e ADD	$0x40,%R8

  (610) 0x4676a2 CMP	%R8,%RCX

  (610) 0x4676a5 JNE	467640

(609) 0x4676a7 ADDQ	$0x8,-0x98(%RBP)

(609) 0x4676af MOV	-0x98(%RBP),%RSI

(609) 0x4676b6 CMP	%RSI,-0x140(%RBP)

(609) 0x4676bd JNE	466a20

0x4676c3 MOV	%R9,%R15

0x4676c6 MOV	-0x40(%RBP),%RDI

0x4676ca CALL	552440 <hypre_Free>

0x4676cf MOV	-0x78(%RBP),%RDI

0x4676d3 CALL	552440 <hypre_Free>

0x4676d8 MOV	%R15,%RDI

0x4676db CALL	552440 <hypre_Free>

0x4676e0 ADD	$0x168,%RSP

0x4676e7 MOV	%RBX,%RDI

0x4676ea POP	%RBX

0x4676eb POP	%R12

0x4676ed POP	%R13

0x4676ef POP	%R14

0x4676f1 POP	%R15

0x4676f3 POP	%RBP

0x4676f4 JMP	552440

0x4676f9 NOPL	(%RAX)

  (612) 0x467700 MOV	-0x180(%RBP),%R13

  (612) 0x467707 MOV	-0x178(%RBP),%R10

  (612) 0x46770e MOV	(%R13,%RCX,8),%RCX

  (612) 0x467713 MOV	0x8(%R10,%R8,1),%R10

  (612) 0x467718 ADD	%RCX,%R10

  (612) 0x46771b MOV	%R10,-0xa8(%RBP)

  (612) 0x467722 CMP	%R10,%RCX

  (612) 0x467725 JGE	467084

  (612) 0x46772b MOV	-0x188(%RBP),%R8

  (612) 0x467732 MOV	-0xb0(%RBP),%R13

  (612) 0x467739 SUB	%RCX,%R10

  (612) 0x46773c MOV	(%R8,%R13,1),%R8

  (612) 0x467740 AND	$0x3,%R10D

  (612) 0x467744 JE	467825

  (612) 0x46774a CMP	$0x1,%R10

  (612) 0x46774e JE	4677d8

  (612) 0x467754 CMP	$0x2,%R10

  (612) 0x467758 JE	467798

  (612) 0x46775a VMOVSD	(%RDX),%XMM2

  (612) 0x46775e MOV	-0x108(%RBP),%R13

  (612) 0x467765 MOV	(%R8,%RCX,8),%R10

  (612) 0x467769 VMULSD	(%R13,%RCX,8),%XMM2,%XMM6

  (612) 0x467770 TEST	%R10,%R10

  (612) 0x467773 JS	4679f9

  (612) 0x467779 MOV	(%RBX,%R10,8),%R10

  (612) 0x46777d LEA	(%R11,%R10,8),%R13

  (612) 0x467781 VADDSD	(%R13),%XMM6,%XMM7

  (612) 0x467787 VMOVSD	%XMM7,(%R13)

  (612) 0x46778d VADDSD	%XMM6,%XMM1,%XMM1

  (612) 0x467791 VADDSD	%XMM6,%XMM0,%XMM0

  (612) 0x467795 INC	%RCX

  (612) 0x467798 VMOVSD	(%RDX),%XMM9

  (612) 0x46779c MOV	-0x108(%RBP),%R13

  (612) 0x4677a3 MOV	(%R8,%RCX,8),%R10

  (612) 0x4677a7 VMULSD	(%R13,%RCX,8),%XMM9,%XMM10

  (612) 0x4677ae TEST	%R10,%R10

  (612) 0x4677b1 JS	4679d0

  (612) 0x4677b7 MOV	(%RBX,%R10,8),%R10

  (612) 0x4677bb LEA	(%R11,%R10,8),%R13

  (612) 0x4677bf VADDSD	(%R13),%XMM10,%XMM5

  (612) 0x4677c5 VMOVSD	%XMM5,(%R13)

  (612) 0x4677cb VADDSD	%XMM10,%XMM1,%XMM1

  (612) 0x4677d0 VADDSD	%XMM10,%XMM0,%XMM0

  (612) 0x4677d5 INC	%RCX

  (612) 0x4677d8 VMOVSD	(%RDX),%XMM13

  (612) 0x4677dc MOV	-0x108(%RBP),%R13

  (612) 0x4677e3 MOV	(%R8,%RCX,8),%R10

  (612) 0x4677e7 VMULSD	(%R13,%RCX,8),%XMM13,%XMM12

  (612) 0x4677ee TEST	%R10,%R10

  (612) 0x4677f1 JS	4679a0

  (612) 0x4677f7 MOV	(%RBX,%R10,8),%R10

  (612) 0x4677fb LEA	(%R11,%R10,8),%R13

  (612) 0x4677ff VADDSD	(%R13),%XMM12,%XMM14

  (612) 0x467805 VMOVSD	%XMM14,(%R13)

  (612) 0x46780b INC	%RCX

  (612) 0x46780e VADDSD	%XMM12,%XMM1,%XMM1

  (612) 0x467813 VADDSD	%XMM12,%XMM0,%XMM0

  (612) 0x467818 CMP	%RCX,-0xa8(%RBP)

  (612) 0x46781f JE	467084

  (612) 0x467825 MOV	%R14,-0x190(%RBP)

  (612) 0x46782c MOV	-0x108(%RBP),%R13

  (612) 0x467833 JMP	46790e

0x467838 NOPL	(%RAX,%RAX,1)

    (613) 0x467840 MOV	(%RBX,%R14,8),%R10

    (613) 0x467844 LEA	(%R11,%R10,8),%R14

    (613) 0x467848 VADDSD	(%R14),%XMM2,%XMM6

    (613) 0x46784d VMOVSD	%XMM6,(%R14)

    (613) 0x467852 INC	%RCX

    (613) 0x467855 VMOVSD	(%RDX),%XMM8

    (613) 0x467859 MOV	(%R8,%RCX,8),%R10

    (613) 0x46785d VMULSD	(%R13,%RCX,8),%XMM8,%XMM9

    (613) 0x467864 VADDSD	%XMM2,%XMM1,%XMM1

    (613) 0x467868 VADDSD	%XMM2,%XMM0,%XMM0

    (613) 0x46786c TEST	%R10,%R10

    (613) 0x46786f JS	467980

    (613) 0x467875 MOV	(%RBX,%R10,8),%R14

    (613) 0x467879 LEA	(%R11,%R14,8),%R10

    (613) 0x46787d VADDSD	(%R10),%XMM9,%XMM10

    (613) 0x467882 VMOVSD	%XMM10,(%R10)

    (613) 0x467887 LEA	0x1(%RCX),%R14

    (613) 0x46788b VMOVSD	(%RDX),%XMM14

    (613) 0x46788f MOV	(%R8,%R14,8),%R10

    (613) 0x467893 VMULSD	(%R13,%R14,8),%XMM14,%XMM15

    (613) 0x46789a VADDSD	%XMM9,%XMM1,%XMM11

    (613) 0x46789f VADDSD	%XMM9,%XMM0,%XMM13

    (613) 0x4678a4 TEST	%R10,%R10

    (613) 0x4678a7 JS	467960

    (613) 0x4678ad MOV	(%RBX,%R10,8),%R14

    (613) 0x4678b1 LEA	(%R11,%R14,8),%R10

    (613) 0x4678b5 VADDSD	(%R10),%XMM15,%XMM12

    (613) 0x4678ba VMOVSD	%XMM12,(%R10)

    (613) 0x4678bf LEA	0x2(%RCX),%R14

    (613) 0x4678c3 VMOVSD	(%RDX),%XMM1

    (613) 0x4678c7 MOV	(%R8,%R14,8),%R10

    (613) 0x4678cb VMULSD	(%R13,%R14,8),%XMM1,%XMM12

    (613) 0x4678d2 VADDSD	%XMM15,%XMM11,%XMM6

    (613) 0x4678d7 VADDSD	%XMM15,%XMM13,%XMM7

    (613) 0x4678dc TEST	%R10,%R10

    (613) 0x4678df JS	467940

    (613) 0x4678e1 MOV	(%RBX,%R10,8),%R14

    (613) 0x4678e5 LEA	(%R11,%R14,8),%R10

    (613) 0x4678e9 VADDSD	(%R10),%XMM12,%XMM0

    (613) 0x4678ee VMOVSD	%XMM0,(%R10)

    (613) 0x4678f3 ADD	$0x3,%RCX

    (613) 0x4678f7 VADDSD	%XMM12,%XMM6,%XMM1

    (613) 0x4678fc VADDSD	%XMM12,%XMM7,%XMM0

    (613) 0x467901 CMP	%RCX,-0xa8(%RBP)

    (613) 0x467908 JE	4679c0

    (613) 0x46790e VMOVSD	(%RDX),%XMM12

    (613) 0x467912 MOV	(%R8,%RCX,8),%R14

    (613) 0x467916 VMULSD	(%R13,%RCX,8),%XMM12,%XMM2

    (613) 0x46791d TEST	%R14,%R14

    (613) 0x467920 JNS	467840

    (613) 0x467926 NOT	%R14

    (613) 0x467929 MOV	(%R9,%R14,8),%R10

    (613) 0x46792d LEA	(%R12,%R10,8),%R14

    (613) 0x467931 VADDSD	(%R14),%XMM2,%XMM7

    (613) 0x467936 VMOVSD	%XMM7,(%R14)

    (613) 0x46793b JMP	467852

    (613) 0x467940 NOT	%R10

    (613) 0x467943 MOV	(%R9,%R10,8),%R14

    (613) 0x467947 LEA	(%R12,%R14,8),%R10

    (613) 0x46794b VADDSD	(%R10),%XMM12,%XMM8

    (613) 0x467950 VMOVSD	%XMM8,(%R10)

    (613) 0x467955 JMP	4678f3

0x467957 NOPW	(%RAX,%RAX,1)

    (613) 0x467960 NOT	%R10

    (613) 0x467963 MOV	(%R9,%R10,8),%R14

    (613) 0x467967 LEA	(%R12,%R14,8),%R10

    (613) 0x46796b VADDSD	(%R10),%XMM15,%XMM2

    (613) 0x467970 VMOVSD	%XMM2,(%R10)

    (613) 0x467975 JMP	4678bf

0x46797a NOPW	(%RAX,%RAX,1)

    (613) 0x467980 NOT	%R10

    (613) 0x467983 MOV	(%R9,%R10,8),%R14

    (613) 0x467987 LEA	(%R12,%R14,8),%R10

    (613) 0x46798b VADDSD	(%R10),%XMM9,%XMM5

    (613) 0x467990 VMOVSD	%XMM5,(%R10)

    (613) 0x467995 JMP	467887

0x46799a NOPW	(%RAX,%RAX,1)

  (612) 0x4679a0 NOT	%R10

  (612) 0x4679a3 MOV	(%R9,%R10,8),%R10

  (612) 0x4679a7 LEA	(%R12,%R10,8),%R13

  (612) 0x4679ab VADDSD	(%R13),%XMM12,%XMM15

  (612) 0x4679b1 VMOVSD	%XMM15,(%R13)

  (612) 0x4679b7 JMP	46780b

0x4679bc NOPL	(%RAX)

  (612) 0x4679c0 MOV	-0x190(%RBP),%R14

  (612) 0x4679c7 JMP	467084

0x4679cc NOPL	(%RAX)

  (612) 0x4679d0 NOT	%R10

  (612) 0x4679d3 MOV	(%R9,%R10,8),%R10

  (612) 0x4679d7 LEA	(%R12,%R10,8),%R13

  (612) 0x4679db VADDSD	(%R13),%XMM10,%XMM11

  (612) 0x4679e1 VMOVSD	%XMM11,(%R13)

  (612) 0x4679e7 JMP	4677cb

(609) 0x4679ec VXORPD	%XMM0,%XMM0,%XMM0

(609) 0x4679f0 VMOVAPD	%XMM0,%XMM1

(609) 0x4679f4 JMP	467005

  (612) 0x4679f9 NOT	%R10

  (612) 0x4679fc MOV	(%R9,%R10,8),%R10

  (612) 0x467a00 LEA	(%R12,%R10,8),%R13

  (612) 0x467a04 VADDSD	(%R13),%XMM6,%XMM8

  (612) 0x467a0a VMOVSD	%XMM8,(%R13)

  (612) 0x467a10 JMP	46778d

0x467a15 MOV	%R11,-0xd8(%RBP)

0x467a1c MOV	%R10,-0xd0(%RBP)

0x467a23 VMOVSD	%XMM2,-0xb0(%RBP)

0x467a2b MOV	$0x8,%ESI

0x467a30 MOV	%RDX,%RDI

0x467a33 JMP	4668a7

0x467a38 MOV	$0x8,%ESI

0x467a3d MOV	%RCX,%RDI

0x467a40 MOV	%R11,-0xf8(%RBP)

0x467a47 MOV	%R10,-0xf0(%RBP)

0x467a4e MOV	%RDX,-0xd8(%RBP)

0x467a55 MOV	%R8,-0xd0(%RBP)

0x467a5c VMOVSD	%XMM2,-0xb0(%RBP)

0x467a64 CALL	5523b0 <hypre_CAlloc>

0x467a69 MOV	%RAX,%R15

0x467a6c VMOVSD	-0xb0(%RBP),%XMM2

0x467a74 MOV	-0xd0(%RBP),%R8

0x467a7b MOV	-0xd8(%RBP),%RDX

0x467a82 MOV	-0xf0(%RBP),%R10

0x467a89 MOV	-0xf8(%RBP),%R11

0x467a90 JMP	466880

0x467a95 MOV	$0x8,%ESI

0x467a9a MOV	%R14,%RDI

0x467a9d MOV	%R11,-0x100(%RBP)

0x467aa4 MOV	%R10,-0xf8(%RBP)

0x467aab MOV	%RCX,-0xf0(%RBP)

0x467ab2 MOV	%RDX,-0xd8(%RBP)

0x467ab9 MOV	%R8,-0xd0(%RBP)

0x467ac0 VMOVSD	%XMM2,-0xb0(%RBP)

0x467ac8 CALL	5523b0 <hypre_CAlloc>

0x467acd MOV	%RAX,-0x78(%RBP)

0x467ad1 VMOVSD	-0xb0(%RBP),%XMM2

0x467ad9 MOV	-0xd0(%RBP),%R8

0x467ae0 MOV	-0xd8(%RBP),%RDX

0x467ae7 MOV	-0xf0(%RBP),%RCX

0x467aee MOV	-0xf8(%RBP),%R10

0x467af5 MOV	-0x100(%RBP),%R11

0x467afc JMP	466874

0x467b01 MOV	$0x8,%ESI

0x467b06 MOV	%R11,-0xf8(%RBP)

0x467b0d MOV	%R10,-0xf0(%RBP)

0x467b14 MOV	%RCX,-0xd8(%RBP)

0x467b1b MOV	%RDX,-0xd0(%RBP)

0x467b22 MOV	%R8,-0xb0(%RBP)

0x467b29 VMOVSD	%XMM2,-0x78(%RBP)

0x467b2e CALL	5523b0 <hypre_CAlloc>

0x467b33 MOV	%RAX,-0x40(%RBP)

0x467b37 VMOVSD	-0x78(%RBP),%XMM2

0x467b3c MOV	-0xb0(%RBP),%R8

0x467b43 MOV	-0xd0(%RBP),%RDX

0x467b4a MOV	-0xd8(%RBP),%RCX

0x467b51 MOV	-0xf0(%RBP),%R10

0x467b58 MOV	-0xf8(%RBP),%R11

0x467b5f JMP	466863

0x467b64 NOPW	%CS:(%RAX,%RAX,1)

0x467b6f NOP

Coverage (%)	Name	Source Location	Module
○97.65	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.35	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1746-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 45.67 to 4.33 cycles (10.54x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 45.67 to 5.03 cycles (9.08x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CAlloc: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1757
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1754
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1751
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1748
hypre_Free: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1878
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1879
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1880
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1766
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1767
memset@plt: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1761
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1763

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1768

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1768

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 688 bytes. The binary function is storing 584 bytes.

General properties

nb instructions	259
nb uops	274
loop length	1414
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	43

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	45.67 cycles
front end	45.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.80	6.80	30.67	30.67	45.00	6.80	6.80	45.00	45.00	45.00	6.80	30.67
cycles	6.80	8.00	30.67	30.67	45.00	6.80	6.80	45.00	45.00	45.00	6.80	30.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	45.67
Dispatch	45.00
DIV/SQRT	10.00
Overall L1	45.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 45.67 cycles. At this rate:

7% of peak load performance is reached (15.07 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (12.79 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 466670

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x168,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x148(%RDI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x138(%RAX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x130(%RAX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x128(%RAX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x108(%RAX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x100(%RAX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xf8(%RAX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x110(%RAX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x140(%RAX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x120(%RAX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x118(%RAX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x178(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xf0(%RAX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xe8(%RAX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xd8(%RAX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xd0(%RAX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xc8(%RAX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xe0(%RAX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xc0(%RAX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb8(%RAX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xb0(%RAX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,-0x188(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0x148(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa8(%RAX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x98(%RAX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R14,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,-0x118(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x80(%RAX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x68(%RAX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RBX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%RAX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R13,-0x150(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x158(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x180(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa0(%RAX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x90(%RAX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RAX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x78(%RAX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x70(%RAX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x58(%RAX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x50(%RAX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x48(%RAX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x40(%RAX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RSI,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x128(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RAX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RAX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R15,-0x160(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RAX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RBX,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0x168(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RAX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RAX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,-0x170(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,-0x138(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RAX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RAX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %RDI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 467b01 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1491>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %R14,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 467a95 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1425>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 467a38 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x13c8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CMP %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 467a15 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x13a5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R11,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM2,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CMPQ $0,-0x38(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
VMOVSD -0xb0(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xd0(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xd8(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 46690e <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x29e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x38(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x40(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM2,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4110a0 <memset@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0xb0(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xd0(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xd8(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %R14,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 46694f <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x2df>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x78(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%R14,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM2,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4110a0 <memset@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x38(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xb0(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xd0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM2,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 555090 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 555080 <hypre_NumActiveThreads>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x98(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xa8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX,%RAX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RAX,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %R9	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOV %R8,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x38(%RBP),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
DEC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R11,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0xd8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
IMUL %RAX,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVNE %RAX,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
LEA (%RCX,%R10,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0xd0(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JLE 4676c6 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1056>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xe0(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVQ 0xf4184(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%R14,%RSI,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R14,%RDI,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xa8(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0xe8(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
DEC %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x40(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 552440 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x78(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 552440 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 552440 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x168,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 552440 <hypre_Free>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM2,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4668a7 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x237>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM2,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVSD -0xb0(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xd0(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xd8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf0(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 466880 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x210>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM2,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0xb0(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xd0(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xd8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf8(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x100(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 466874 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x204>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R11,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM2,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x78(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xb0(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xd0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xd8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf0(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 466863 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1f3>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1746-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CAlloc: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1757
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1754
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1751
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1748
hypre_Free: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1878
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1879
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1880
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1766
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1767
memset@plt: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1761
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1763

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1768

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1768

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 688 bytes. The binary function is storing 584 bytes.

General properties

nb instructions	259
nb uops	274
loop length	1414
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	43

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	45.67 cycles
front end	45.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.80	6.80	30.67	30.67	45.00	6.80	6.80	45.00	45.00	45.00	6.80	30.67
cycles	6.80	8.00	30.67	30.67	45.00	6.80	6.80	45.00	45.00	45.00	6.80	30.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	45.67
Dispatch	45.00
DIV/SQRT	10.00
Overall L1	45.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 45.67 cycles. At this rate:

7% of peak load performance is reached (15.07 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (12.79 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 466670

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x168,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x148(%RDI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x138(%RAX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x130(%RAX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x128(%RAX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x108(%RAX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x100(%RAX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xf8(%RAX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x110(%RAX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x140(%RAX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x120(%RAX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x118(%RAX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x178(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xf0(%RAX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xe8(%RAX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xd8(%RAX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xd0(%RAX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xc8(%RAX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xe0(%RAX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xc0(%RAX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb8(%RAX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xb0(%RAX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,-0x188(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0x148(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa8(%RAX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x98(%RAX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R14,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,-0x118(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x80(%RAX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x68(%RAX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RBX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%RAX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R13,-0x150(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x158(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x180(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xa0(%RAX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x90(%RAX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RAX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x78(%RAX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x70(%RAX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x58(%RAX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x50(%RAX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x48(%RAX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x40(%RAX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RSI,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x128(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RAX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RAX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R15,-0x160(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RAX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RBX,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0x168(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RAX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RAX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,-0x170(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,-0x138(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RAX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x8(%RAX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RBX,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %RDI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 467b01 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1491>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %R14,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 467a95 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1425>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 467a38 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x13c8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CMP %RDX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 467a15 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x13a5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R11,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM2,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CMPQ $0,-0x38(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
VMOVSD -0xb0(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xd0(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xd8(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 46690e <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x29e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x38(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x40(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SAL $0x3,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM2,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4110a0 <memset@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0xb0(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xd0(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xd8(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %R14,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JLE 46694f <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x2df>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x78(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%R14,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM2,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4110a0 <memset@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSD -0x38(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xb0(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xd0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM2,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 555090 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 555080 <hypre_NumActiveThreads>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x98(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xa8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX,%RAX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RAX,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %R9	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOV %R8,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x38(%RBP),%XMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
DEC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R11,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0xd8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
IMUL %RAX,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R9,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVNE %RAX,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
LEA (%RCX,%R10,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV -0xd0(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JLE 4676c6 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1056>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xe0(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVQ 0xf4184(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%R14,%RSI,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R14,%RDI,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xa8(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0xe8(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
DEC %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x40(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 552440 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x78(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 552440 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 552440 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
ADD $0x168,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 552440 <hypre_Free>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM2,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 4668a7 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x237>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM2,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVSD -0xb0(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xd0(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xd8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf0(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 466880 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x210>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM2,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0xb0(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xd0(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xd8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf8(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x100(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 466874 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x204>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R11,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM2,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD -0x78(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xb0(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xd0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xd8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf0(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf8(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 466863 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1f3>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass._omp_fn.10–	1.46	0.63
▼Loop 609 - par_multi_interp.c:1774-1876 - exec–	0.19	0.07
▼Loop 614 - par_multi_interp.c:1811-1837 - exec–	0.82	0.31
○Loop 616 - par_multi_interp.c:1816-1822 - exec	0.00	0.01
○Loop 615 - par_multi_interp.c:1824-1830 - exec	0.00	0.00
○Loop 618 - par_multi_interp.c:1799-1803 - exec	0.45	0.17
▼Loop 612 - par_multi_interp.c:1840-1867 - exec–	0.00	0.01
○Loop 613 - par_multi_interp.c:1851-1860 - exec	0.00	0.00
○Loop 617 - par_multi_interp.c:1805-1809 - exec	0.00	0.01
○Loop 620 - par_multi_interp.c:1782-1787 - exec	0.00	0.00
○Loop 619 - par_multi_interp.c:1792-1797 - exec	0.00	0.00
○Loop 611 - par_multi_interp.c:1873-1874 - exec	0.00	0.00
○Loop 610 - par_multi_interp.c:1875-1876 - exec	0.00	0.00

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