OV - exec - Function hypre_BoomerAMGBuildMultipass._omp

	Function: hypre_BoomerAMGBuildMultipass._omp_fn.5	Module: exec	Source: par_multi_interp.c:891-1134 [...]	Coverage (incl. loops): 1.74% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 891 - 1134

--------------------------------------------------------------------------------

891:       #pragma omp parallel private(i,my_thread_num,num_threads,thread_start,thread_stop,cnt_nz,cnt_nz_offd,i1,j,j1,j_start,j_end,k1,k,P_marker,P_marker_offd)

[...]

900:           my_thread_num = hypre_GetThreadNum();

901:           num_threads = hypre_NumActiveThreads();

902:           thread_start = (pass_length/num_threads)*my_thread_num;

903:           if (my_thread_num == num_threads-1)

904:           {  thread_stop = pass_length; }

905:           else

906:           {  thread_stop = (pass_length/num_threads)*(my_thread_num+1); }

907:           thread_start += pass_pointer[pass];

908:           thread_stop += pass_pointer[pass];

909:

910:           /* Local initializations */

911:           cnt_nz = 0;

912:           cnt_nz_offd = 0;

913:

914:           /* This block of code is to go to the top of the parallel region starting before

915:            * the loop over num_passes. */

916:           P_marker = hypre_CTAlloc(HYPRE_Int, n_coarse); /* marks points to see if they're counted */

917:           for (i=0; i < n_coarse; i++)

918:           {   P_marker[i] = -1; }

919:           if (new_num_cols_offd == local_index+1)

920:           {

921:              P_marker_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd);

922:              for (i=0; i < new_num_cols_offd; i++)

923:              {   P_marker_offd[i] = -1; }

924:           }

925:           else if (n_coarse_offd)

926:           {

927:              P_marker_offd = hypre_CTAlloc(HYPRE_Int, n_coarse_offd);

[...]

939:           for (i=thread_start; i < thread_stop; i++)

940:           {

941:              i1 = pass_array[i];

942:              P_diag_start[i1] = cnt_nz;

943:              P_offd_start[i1] = cnt_nz_offd;

944:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

945:              {

946:                 j1 = S_diag_j[j];

947:                 if (assigned[j1] == pass-1)

948:                 {

949:                    j_start = P_diag_start[j1];

950:                    j_end = j_start+P_diag_i[j1+1];

951:                    for (k=j_start; k < j_end; k++)

952:                    {

953:                       k1 = P_diag_pass[pass-1][k];

954:                       if (P_marker[k1] != i1)

955:                       {

956:                          cnt_nz++;

957:                          P_diag_i[i1+1]++;

958:                          P_marker[k1] = i1;

959:                       }

960:                    }

961:                    j_start = P_offd_start[j1];

962:                    j_end = j_start+P_offd_i[j1+1];

963:                    for (k=j_start; k < j_end; k++)

964:                    {

965:                       k1 = P_offd_pass[pass-1][k];

966:                       if (P_marker_offd[k1] != i1)

967:                       {

968:                          cnt_nz_offd++;

969:                          P_offd_i[i1+1]++;

970:                          P_marker_offd[k1] = i1;

[...]

976:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

977:              {

978:                 j1 = S_offd_j[j];

979:                 if (assigned_offd[j1] == pass-1)

980:                 {

981:                    j_start = Pext_start[j1];

982:                    j_end = j_start+Pext_i[j1+1];

983:                    for (k=j_start; k < j_end; k++)

984:                    {

985:                       k1 = Pext_pass[pass][k];

986:                       if (k1 < 0)

987:                       {

988:                          if (P_marker[-k1-1] != i1)

989:                          {

990:                             cnt_nz++;

991:                             P_diag_i[i1+1]++;

992:                             P_marker[-k1-1] = i1;

993:                          }

994:                       }

995:                       else if (P_marker_offd[k1] != i1)

996:                       {

997:                          cnt_nz_offd++;

998:                          P_offd_i[i1+1]++;

999:                          P_marker_offd[k1] = i1;

[...]

1008:           if(my_thread_num == 0)

1009:           {   max_num_threads[0] = num_threads; }

1010:           cnt_nz_offd_per_thread[my_thread_num] = cnt_nz_offd;

1011:           cnt_nz_per_thread[my_thread_num] = cnt_nz;

1012: #ifdef HYPRE_USING_OPENMP

1013: #pragma omp barrier

1014: #endif

1015:           if(my_thread_num == 0)

1016:           {

1017:               for(i = 1; i < max_num_threads[0]; i++)

1018:               {

1019:                   cnt_nz_offd_per_thread[i] += cnt_nz_offd_per_thread[i-1];

1020:                   cnt_nz_per_thread[i] += cnt_nz_per_thread[i-1];

1021:               }

1022:           }

1023: #ifdef HYPRE_USING_OPENMP

1024: #pragma omp barrier

1025: #endif

1026:           if(my_thread_num > 0)

1027:           {

1028:               /* update this thread's section of P_diag_start and P_offd_start

1029:                * with the num of nz's counted by previous threads */

1030:               for (i=thread_start; i < thread_stop; i++)

1031:                {

1032:                    i1 = pass_array[i];

1033:                    P_diag_start[i1] += cnt_nz_per_thread[my_thread_num-1];

1034:                    P_offd_start[i1] += cnt_nz_offd_per_thread[my_thread_num-1];

[...]

1040:               cnt_nz = cnt_nz_per_thread[max_num_threads[0]-1];

1041:               cnt_nz_offd = cnt_nz_offd_per_thread[max_num_threads[0]-1];

1042:

1043:               /* Updated total nz count */

1044:               total_nz += cnt_nz;

1045:               total_nz_offd += cnt_nz_offd;

1046:

1047:               /* Allocate P_diag_pass and P_offd_pass for all threads */

1048:               P_diag_pass[pass] = hypre_CTAlloc(HYPRE_Int, cnt_nz);

1049:               if (cnt_nz_offd)

1050:                  P_offd_pass[pass] = hypre_CTAlloc(HYPRE_Int, cnt_nz_offd);

1051:               else if (num_procs > 1)

1052:                  P_offd_pass[pass] = NULL;

1053:           }

1054: #ifdef HYPRE_USING_OPENMP

1055: #pragma omp barrier

1056: #endif

1057:

1058:           /* offset cnt_nz and cnt_nz_offd to point to the starting

1059:            * point in P_diag_pass and P_offd_pass for each thread */

1060:           if(my_thread_num > 0)

1061:           {

1062:               cnt_nz = cnt_nz_per_thread[my_thread_num-1];

1063:               cnt_nz_offd = cnt_nz_offd_per_thread[my_thread_num-1];

1064:           }

1065:           else

1066:           {

1067:               cnt_nz = 0;

1068:               cnt_nz_offd = 0;

1069:           }

1070:

1071:           /* Set P_diag_pass and P_offd_pass */

1072:           for (i=thread_start; i < thread_stop; i++)

1073:           {

1074:              i1 = pass_array[i];

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

1100:                       }

1101:                    }

1102:                 }

1103:              }

1104:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1105:              {

1106:                 j1 = S_offd_j[j];

1107:                 if (assigned_offd[j1] == pass-1)

1108:                 {

1109:                    j_start = Pext_start[j1];

1110:                    j_end = j_start+Pext_i[j1+1];

1111:                    for (k=j_start; k < j_end; k++)

1112:                    {

1113:                       k1 = Pext_pass[pass][k];

1114:                       if (k1 < 0)

1115:                       {

1116:                          if (P_marker[-k1-1] != -i1-1)

1117:                          {

1118:                             P_diag_pass[pass][cnt_nz++] = -k1-1;

1119:                             P_marker[-k1-1] = -i1-1;

1120:                          }

1121:                       }

1122:                       else if (P_marker_offd[k1] != -i1-1)

1123:                       {

1124:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1125:                          P_marker_offd[k1] = -i1-1;

[...]

1132:           hypre_TFree(P_marker);

1133:           if ( (n_coarse_offd) || (new_num_cols_offd  == local_index+1) )

1134:           {    hypre_TFree(P_marker_offd); }

0x4621d0 PUSH	%RBP

0x4621d1 MOV	%RDI,%RAX

0x4621d4 MOV	%RSP,%RBP

0x4621d7 PUSH	%R15

0x4621d9 PUSH	%R14

0x4621db PUSH	%R13

0x4621dd PUSH	%R12

0x4621df PUSH	%RBX

0x4621e0 SUB	$0x128,%RSP

0x4621e7 MOV	0xe0(%RDI),%R8

0x4621ee MOV	0xd8(%RDI),%R10

0x4621f5 MOV	0xc0(%RAX),%RDX

0x4621fc MOV	0xa0(%RAX),%RCX

0x462203 MOV	0x98(%RAX),%RSI

0x46220a MOV	0x90(%RAX),%R9

0x462211 MOV	%RDI,-0x148(%RBP)

0x462218 MOV	0xd0(%RDI),%RDI

0x46221f MOV	0xc8(%RAX),%R14

0x462226 MOV	0x88(%RAX),%R12

0x46222d MOV	%R8,-0x70(%RBP)

0x462231 MOV	%R10,-0x68(%RBP)

0x462235 MOV	%RDI,-0x120(%RBP)

0x46223c MOV	%RDX,-0x118(%RBP)

0x462243 MOV	%RCX,-0xd8(%RBP)

0x46224a MOV	%RSI,-0x48(%RBP)

0x46224e MOV	%R9,-0x108(%RBP)

0x462255 MOV	0xb8(%RAX),%RBX

0x46225c MOV	0x80(%RAX),%R11

0x462263 MOV	0x70(%RAX),%R15

0x462267 MOV	0x68(%RAX),%R8

0x46226b MOV	0x60(%RAX),%R10

0x46226f MOV	0x58(%RAX),%RDI

0x462273 MOV	0x50(%RAX),%RDX

0x462277 MOV	0x48(%RAX),%RCX

0x46227b MOV	0x38(%RAX),%RSI

0x46227f MOV	0x30(%RAX),%R9

0x462283 MOV	%R11,-0xf0(%RBP)

0x46228a MOV	%R15,-0x98(%RBP)

0x462291 MOV	0x28(%RAX),%R11

0x462295 MOV	0x40(%RAX),%R15

0x462299 MOV	%R8,-0xa8(%RBP)

0x4622a0 MOV	%R10,-0xe0(%RBP)

0x4622a7 MOV	0x20(%RAX),%R8

0x4622ab MOV	0x18(%RAX),%R10

0x4622af MOV	%RDI,-0xe8(%RBP)

0x4622b6 MOV	%RDX,-0x78(%RBP)

0x4622ba MOV	0x10(%RAX),%RDI

0x4622be MOV	0x8(%RAX),%RDX

0x4622c2 MOV	(%RAX),%RAX

0x4622c5 MOV	%RCX,-0x80(%RBP)

0x4622c9 MOV	%RSI,-0xb0(%RBP)

0x4622d0 MOV	%R9,-0xa0(%RBP)

0x4622d7 MOV	%R11,-0x58(%RBP)

0x4622db MOV	%R8,-0x60(%RBP)

0x4622df MOV	%R10,-0x50(%RBP)

0x4622e3 MOV	%RDI,-0xc8(%RBP)

0x4622ea MOV	%RDX,-0x40(%RBP)

0x4622ee MOV	%RAX,-0xd0(%RBP)

0x4622f5 CALL	555090 <hypre_GetThreadNum>

0x4622fa MOV	%RAX,-0x110(%RBP)

0x462301 CALL	555080 <hypre_NumActiveThreads>

0x462306 MOV	%RAX,%RSI

0x462309 MOV	%RAX,-0x150(%RBP)

0x462310 MOV	%R14,%RAX

0x462313 CQTO

0x462315 IDIV	%RSI

0x462318 MOV	-0x110(%RBP),%RCX

0x46231f MOV	-0xf0(%RBP),%R10

0x462326 MOV	(%R15,%R10,8),%R15

0x46232a MOV	%RCX,%R9

0x46232d LEA	-0x1(%RSI),%R11

0x462331 MOV	%R14,%R8

0x462334 MOV	$0x8,%ESI

0x462339 LEA	(,%R10,8),%R14

0x462341 IMUL	%RAX,%R9

0x462345 ADD	%R9,%RAX

0x462348 CMP	%R11,%RCX

0x46234b CMOVNE	%RAX,%R8

0x46234f LEA	(%R9,%R15,1),%RDI

0x462353 MOV	%RDI,-0x38(%RBP)

0x462357 ADD	%R8,%R15

0x46235a MOV	%R12,%RDI

0x46235d MOV	%R8,-0x100(%RBP)

0x462364 MOV	%R15,-0xb8(%RBP)

0x46236b MOV	%R9,-0xf8(%RBP)

0x462372 CALL	5523b0 <hypre_CAlloc>

0x462377 TEST	%R12,%R12

0x46237a MOV	-0x38(%RBP),%R11

0x46237e MOV	-0x68(%RBP),%R10

0x462382 MOV	-0x70(%RBP),%R8

0x462386 MOV	%RAX,%R15

0x462389 JLE	4623b8

0x46238b LEA	(,%R12,8),%RDX

0x462393 MOV	$0xff,%ESI

0x462398 MOV	%RAX,%RDI

0x46239b MOV	%R11,-0x70(%RBP)

0x46239f MOV	%R10,-0x68(%RBP)

0x4623a3 MOV	%R8,-0x38(%RBP)

0x4623a7 CALL	4110a0 <memset@plt>

0x4623ac MOV	-0x38(%RBP),%R8

0x4623b0 MOV	-0x68(%RBP),%R10

0x4623b4 MOV	-0x70(%RBP),%R11

0x4623b8 LEA	0x1(%RBX),%RBX

0x4623bc MOV	%RBX,-0x140(%RBP)

0x4623c3 CMP	%RBX,-0x118(%RBP)

0x4623ca JE	4637ae

0x4623d0 CMPQ	$0,-0x108(%RBP)

0x4623d8 JNE	463750

0x4623de MOV	-0xf0(%RBP),%RAX

0x4623e5 MOV	-0xf8(%RBP),%RDX

0x4623ec XOR	%ECX,%ECX

0x4623ee XOR	%EDI,%EDI

0x4623f0 LEA	-0x1(%RAX),%R9

0x4623f4 CMP	%RDX,-0x100(%RBP)

0x4623fb JLE	462c0e

0x462401 MOV	%R8,-0x128(%RBP)

0x462408 MOV	%R10,-0x130(%RBP)

0x46240f MOV	%R14,-0x70(%RBP)

0x462413 MOV	%R11,-0x138(%RBP)

0x46241a MOV	%R11,-0x68(%RBP)

0x46241e XCHG	%AX,%AX

(581) 0x462420 MOV	-0xb0(%RBP),%R14

(581) 0x462427 MOV	-0x68(%RBP),%R8

(581) 0x46242b MOV	-0x80(%RBP),%R10

(581) 0x46242f MOV	(%R14,%R8,8),%RAX

(581) 0x462433 MOV	-0x78(%RBP),%R11

(581) 0x462437 MOV	%RDI,(%R10,%RAX,8)

(581) 0x46243b MOV	%RCX,(%R11,%RAX,8)

(581) 0x46243f MOV	-0xd0(%RBP),%R12

(581) 0x462446 LEA	0x8(,%RAX,8),%RSI

(581) 0x46244e MOV	(%R12,%RAX,8),%RDX

(581) 0x462452 ADD	%RSI,%R12

(581) 0x462455 MOV	-0x60(%RBP),%RBX

(581) 0x462459 MOV	-0x58(%RBP),%R14

(581) 0x46245d MOV	(%R12),%R8

(581) 0x462461 MOV	%R12,-0x90(%RBP)

(581) 0x462468 LEA	(%RBX,%RSI,1),%R11

(581) 0x46246c LEA	(%R14,%RSI,1),%R10

(581) 0x462470 CMP	%R8,%RDX

(581) 0x462473 JGE	462927

(581) 0x462479 MOV	%RSI,-0xc0(%RBP)

(581) 0x462480 MOV	%R10,-0x38(%RBP)

(581) 0x462484 MOV	-0x48(%RBP),%R14

(581) 0x462488 JMP	4624ac

0x46248a NOPW	%CS:(%RAX,%RAX,1)

0x462495 NOPW	%CS:(%RAX,%RAX,1)

  (584) 0x4624a0 INC	%RDX

  (584) 0x4624a3 CMP	%R8,%RDX

  (584) 0x4624a6 JGE	462920

  (584) 0x4624ac MOV	-0x40(%RBP),%RSI

  (584) 0x4624b0 MOV	(%RSI,%RDX,8),%RSI

  (584) 0x4624b4 LEA	(,%RSI,8),%R12

  (584) 0x4624bc CMP	%R9,(%R14,%RSI,8)

  (584) 0x4624c0 JNE	4624a0

  (584) 0x4624c2 MOV	-0x80(%RBP),%R8

  (584) 0x4624c6 MOV	-0x60(%RBP),%RBX

  (584) 0x4624ca MOV	(%R8,%RSI,8),%R8

  (584) 0x4624ce MOV	0x8(%RBX,%R12,1),%R10

  (584) 0x4624d3 ADD	%R8,%R10

  (584) 0x4624d6 MOV	%R10,-0x88(%RBP)

  (584) 0x4624dd CMP	%R10,%R8

  (584) 0x4624e0 JGE	4626d8

  (584) 0x4624e6 MOV	-0x70(%RBP),%RBX

  (584) 0x4624ea MOV	-0xe8(%RBP),%R10

  (584) 0x4624f1 MOV	-0x8(%R10,%RBX,1),%R10

  (584) 0x4624f6 MOV	-0x88(%RBP),%RBX

  (584) 0x4624fd LEA	(%R10,%R8,8),%R8

  (584) 0x462501 LEA	(%R10,%RBX,8),%R10

  (584) 0x462505 MOV	%R10,-0x88(%RBP)

  (584) 0x46250c SUB	%R8,%R10

  (584) 0x46250f SUB	$0x8,%R10

  (584) 0x462513 SHR	$0x3,%R10

  (584) 0x462517 INC	%R10

  (584) 0x46251a AND	$0x7,%R10D

  (584) 0x46251e JE	46260c

  (584) 0x462524 CMP	$0x1,%R10

  (584) 0x462528 JE	4625e6

  (584) 0x46252e CMP	$0x2,%R10

  (584) 0x462532 JE	4625cd

  (584) 0x462538 CMP	$0x3,%R10

  (584) 0x46253c JE	4625b4

  (584) 0x46253e CMP	$0x4,%R10

  (584) 0x462542 JE	46259b

  (584) 0x462544 CMP	$0x5,%R10

  (584) 0x462548 JE	462582

  (584) 0x46254a CMP	$0x6,%R10

  (584) 0x46254e JE	462569

  (584) 0x462550 MOV	(%R8),%RBX

  (584) 0x462553 LEA	(%R15,%RBX,8),%R10

  (584) 0x462557 CMP	(%R10),%RAX

  (584) 0x46255a JE	462565

  (584) 0x46255c INCQ	(%R11)

  (584) 0x46255f MOV	%RAX,(%R10)

  (584) 0x462562 INC	%RDI

  (584) 0x462565 ADD	$0x8,%R8

  (584) 0x462569 MOV	(%R8),%RBX

  (584) 0x46256c LEA	(%R15,%RBX,8),%R10

  (584) 0x462570 CMP	(%R10),%RAX

  (584) 0x462573 JE	46257e

  (584) 0x462575 INCQ	(%R11)

  (584) 0x462578 MOV	%RAX,(%R10)

  (584) 0x46257b INC	%RDI

  (584) 0x46257e ADD	$0x8,%R8

  (584) 0x462582 MOV	(%R8),%RBX

  (584) 0x462585 LEA	(%R15,%RBX,8),%R10

  (584) 0x462589 CMP	(%R10),%RAX

  (584) 0x46258c JE	462597

  (584) 0x46258e INCQ	(%R11)

  (584) 0x462591 MOV	%RAX,(%R10)

  (584) 0x462594 INC	%RDI

  (584) 0x462597 ADD	$0x8,%R8

  (584) 0x46259b MOV	(%R8),%RBX

  (584) 0x46259e LEA	(%R15,%RBX,8),%R10

  (584) 0x4625a2 CMP	(%R10),%RAX

  (584) 0x4625a5 JE	4625b0

  (584) 0x4625a7 INCQ	(%R11)

  (584) 0x4625aa MOV	%RAX,(%R10)

  (584) 0x4625ad INC	%RDI

  (584) 0x4625b0 ADD	$0x8,%R8

  (584) 0x4625b4 MOV	(%R8),%RBX

  (584) 0x4625b7 LEA	(%R15,%RBX,8),%R10

  (584) 0x4625bb CMP	(%R10),%RAX

  (584) 0x4625be JE	4625c9

  (584) 0x4625c0 INCQ	(%R11)

  (584) 0x4625c3 MOV	%RAX,(%R10)

  (584) 0x4625c6 INC	%RDI

  (584) 0x4625c9 ADD	$0x8,%R8

  (584) 0x4625cd MOV	(%R8),%RBX

  (584) 0x4625d0 LEA	(%R15,%RBX,8),%R10

  (584) 0x4625d4 CMP	(%R10),%RAX

  (584) 0x4625d7 JE	4625e2

  (584) 0x4625d9 INCQ	(%R11)

  (584) 0x4625dc MOV	%RAX,(%R10)

  (584) 0x4625df INC	%RDI

  (584) 0x4625e2 ADD	$0x8,%R8

  (584) 0x4625e6 MOV	(%R8),%RBX

  (584) 0x4625e9 LEA	(%R15,%RBX,8),%R10

  (584) 0x4625ed CMP	(%R10),%RAX

  (584) 0x4625f0 JE	4625fb

  (584) 0x4625f2 INCQ	(%R11)

  (584) 0x4625f5 MOV	%RAX,(%R10)

  (584) 0x4625f8 INC	%RDI

  (584) 0x4625fb ADD	$0x8,%R8

  (584) 0x4625ff CMP	%R8,-0x88(%RBP)

  (584) 0x462606 JE	4626d8

  (584) 0x46260c MOV	-0x38(%RBP),%R10

    (586) 0x462610 MOV	(%R8),%RBX

    (586) 0x462613 LEA	(%R15,%RBX,8),%RBX

    (586) 0x462617 CMP	(%RBX),%RAX

    (586) 0x46261a JE	462625

    (586) 0x46261c INCQ	(%R11)

    (586) 0x46261f MOV	%RAX,(%RBX)

    (586) 0x462622 INC	%RDI

    (586) 0x462625 LEA	0x8(%R8),%RBX

    (586) 0x462629 MOV	0x8(%R8),%R8

    (586) 0x46262d LEA	(%R15,%R8,8),%R8

    (586) 0x462631 CMP	(%R8),%RAX

    (586) 0x462634 JE	46263f

    (586) 0x462636 INCQ	(%R11)

    (586) 0x462639 MOV	%RAX,(%R8)

    (586) 0x46263c INC	%RDI

    (586) 0x46263f MOV	0x8(%RBX),%R8

    (586) 0x462643 LEA	(%R15,%R8,8),%R8

    (586) 0x462647 CMP	(%R8),%RAX

    (586) 0x46264a JE	462655

    (586) 0x46264c INCQ	(%R11)

    (586) 0x46264f MOV	%RAX,(%R8)

    (586) 0x462652 INC	%RDI

    (586) 0x462655 MOV	0x10(%RBX),%R8

    (586) 0x462659 LEA	(%R15,%R8,8),%R8

    (586) 0x46265d CMP	(%R8),%RAX

    (586) 0x462660 JE	46266b

    (586) 0x462662 INCQ	(%R11)

    (586) 0x462665 MOV	%RAX,(%R8)

    (586) 0x462668 INC	%RDI

    (586) 0x46266b MOV	0x18(%RBX),%R8

    (586) 0x46266f LEA	(%R15,%R8,8),%R8

    (586) 0x462673 CMP	(%R8),%RAX

    (586) 0x462676 JE	462681

    (586) 0x462678 INCQ	(%R11)

    (586) 0x46267b MOV	%RAX,(%R8)

    (586) 0x46267e INC	%RDI

    (586) 0x462681 MOV	0x20(%RBX),%R8

    (586) 0x462685 LEA	(%R15,%R8,8),%R8

    (586) 0x462689 CMP	(%R8),%RAX

    (586) 0x46268c JE	462697

    (586) 0x46268e INCQ	(%R11)

    (586) 0x462691 MOV	%RAX,(%R8)

    (586) 0x462694 INC	%RDI

    (586) 0x462697 MOV	0x28(%RBX),%R8

    (586) 0x46269b LEA	(%R15,%R8,8),%R8

    (586) 0x46269f CMP	(%R8),%RAX

    (586) 0x4626a2 JE	4626ad

    (586) 0x4626a4 INCQ	(%R11)

    (586) 0x4626a7 MOV	%RAX,(%R8)

    (586) 0x4626aa INC	%RDI

    (586) 0x4626ad MOV	0x30(%RBX),%R8

    (586) 0x4626b1 LEA	(%R15,%R8,8),%R8

    (586) 0x4626b5 CMP	(%R8),%RAX

    (586) 0x4626b8 JE	4626c3

    (586) 0x4626ba INCQ	(%R11)

    (586) 0x4626bd MOV	%RAX,(%R8)

    (586) 0x4626c0 INC	%RDI

    (586) 0x4626c3 LEA	0x38(%RBX),%R8

    (586) 0x4626c7 CMP	%R8,-0x88(%RBP)

    (586) 0x4626ce JNE	462610

  (584) 0x4626d4 MOV	%R10,-0x38(%RBP)

  (584) 0x4626d8 MOV	-0x78(%RBP),%R10

  (584) 0x4626dc MOV	-0x58(%RBP),%RBX

  (584) 0x4626e0 MOV	(%R10,%RSI,8),%RSI

  (584) 0x4626e4 MOV	0x8(%RBX,%R12,1),%R12

  (584) 0x4626e9 ADD	%RSI,%R12

  (584) 0x4626ec CMP	%R12,%RSI

  (584) 0x4626ef JGE	462903

  (584) 0x4626f5 MOV	-0xe0(%RBP),%R8

  (584) 0x4626fc MOV	-0x70(%RBP),%R10

  (584) 0x462700 MOV	-0x8(%R8,%R10,1),%RBX

  (584) 0x462705 LEA	(%RBX,%R12,8),%R12

  (584) 0x462709 LEA	(%RBX,%RSI,8),%RSI

  (584) 0x46270d MOV	%R12,%R8

  (584) 0x462710 SUB	%RSI,%R8

  (584) 0x462713 SUB	$0x8,%R8

  (584) 0x462717 SHR	$0x3,%R8

  (584) 0x46271b INC	%R8

  (584) 0x46271e AND	$0x7,%R8D

  (584) 0x462722 JE	462833

  (584) 0x462728 CMP	$0x1,%R8

  (584) 0x46272c JE	46280c

  (584) 0x462732 CMP	$0x2,%R8

  (584) 0x462736 JE	4627ee

  (584) 0x46273c CMP	$0x3,%R8

  (584) 0x462740 JE	4627d0

  (584) 0x462746 CMP	$0x4,%R8

  (584) 0x46274a JE	4627b2

  (584) 0x46274c CMP	$0x5,%R8

  (584) 0x462750 JE	462794

  (584) 0x462752 CMP	$0x6,%R8

  (584) 0x462756 JE	462776

  (584) 0x462758 MOV	(%RSI),%R10

  (584) 0x46275b LEA	(%R13,%R10,8),%RBX

  (584) 0x462760 CMP	(%RBX),%RAX

  (584) 0x462763 JE	462772

  (584) 0x462765 MOV	-0x38(%RBP),%R8

  (584) 0x462769 INC	%RCX

  (584) 0x46276c INCQ	(%R8)

  (584) 0x46276f MOV	%RAX,(%RBX)

  (584) 0x462772 ADD	$0x8,%RSI

  (584) 0x462776 MOV	(%RSI),%R10

  (584) 0x462779 LEA	(%R13,%R10,8),%RBX

  (584) 0x46277e CMP	(%RBX),%RAX

  (584) 0x462781 JE	462790

  (584) 0x462783 MOV	-0x38(%RBP),%R8

  (584) 0x462787 INC	%RCX

  (584) 0x46278a INCQ	(%R8)

  (584) 0x46278d MOV	%RAX,(%RBX)

  (584) 0x462790 ADD	$0x8,%RSI

  (584) 0x462794 MOV	(%RSI),%R10

  (584) 0x462797 LEA	(%R13,%R10,8),%RBX

  (584) 0x46279c CMP	(%RBX),%RAX

  (584) 0x46279f JE	4627ae

  (584) 0x4627a1 MOV	-0x38(%RBP),%R8

  (584) 0x4627a5 INC	%RCX

  (584) 0x4627a8 INCQ	(%R8)

  (584) 0x4627ab MOV	%RAX,(%RBX)

  (584) 0x4627ae ADD	$0x8,%RSI

  (584) 0x4627b2 MOV	(%RSI),%R10

  (584) 0x4627b5 LEA	(%R13,%R10,8),%RBX

  (584) 0x4627ba CMP	(%RBX),%RAX

  (584) 0x4627bd JE	4627cc

  (584) 0x4627bf MOV	-0x38(%RBP),%R8

  (584) 0x4627c3 INC	%RCX

  (584) 0x4627c6 INCQ	(%R8)

  (584) 0x4627c9 MOV	%RAX,(%RBX)

  (584) 0x4627cc ADD	$0x8,%RSI

  (584) 0x4627d0 MOV	(%RSI),%R10

  (584) 0x4627d3 LEA	(%R13,%R10,8),%RBX

  (584) 0x4627d8 CMP	(%RBX),%RAX

  (584) 0x4627db JE	4627ea

  (584) 0x4627dd MOV	-0x38(%RBP),%R8

  (584) 0x4627e1 INC	%RCX

  (584) 0x4627e4 INCQ	(%R8)

  (584) 0x4627e7 MOV	%RAX,(%RBX)

  (584) 0x4627ea ADD	$0x8,%RSI

  (584) 0x4627ee MOV	(%RSI),%R10

  (584) 0x4627f1 LEA	(%R13,%R10,8),%RBX

  (584) 0x4627f6 CMP	(%RBX),%RAX

  (584) 0x4627f9 JE	462808

  (584) 0x4627fb MOV	-0x38(%RBP),%R8

  (584) 0x4627ff INC	%RCX

  (584) 0x462802 INCQ	(%R8)

  (584) 0x462805 MOV	%RAX,(%RBX)

  (584) 0x462808 ADD	$0x8,%RSI

  (584) 0x46280c MOV	(%RSI),%R10

  (584) 0x46280f LEA	(%R13,%R10,8),%RBX

  (584) 0x462814 CMP	(%RBX),%RAX

  (584) 0x462817 JE	462826

  (584) 0x462819 MOV	-0x38(%RBP),%R8

  (584) 0x46281d INC	%RCX

  (584) 0x462820 INCQ	(%R8)

  (584) 0x462823 MOV	%RAX,(%RBX)

  (584) 0x462826 ADD	$0x8,%RSI

  (584) 0x46282a CMP	%RSI,%R12

  (584) 0x46282d JE	462903

  (584) 0x462833 MOV	-0x38(%RBP),%R10

    (585) 0x462837 MOV	(%RSI),%RBX

    (585) 0x46283a LEA	(%R13,%RBX,8),%R8

    (585) 0x46283f CMP	(%R8),%RAX

    (585) 0x462842 JE	46284d

    (585) 0x462844 INCQ	(%R10)

    (585) 0x462847 MOV	%RAX,(%R8)

    (585) 0x46284a INC	%RCX

    (585) 0x46284d LEA	0x8(%RSI),%RBX

    (585) 0x462851 MOV	0x8(%RSI),%RSI

    (585) 0x462855 LEA	(%R13,%RSI,8),%R8

    (585) 0x46285a CMP	(%R8),%RAX

    (585) 0x46285d JE	462868

    (585) 0x46285f INCQ	(%R10)

    (585) 0x462862 MOV	%RAX,(%R8)

    (585) 0x462865 INC	%RCX

    (585) 0x462868 MOV	0x8(%RBX),%RSI

    (585) 0x46286c LEA	(%R13,%RSI,8),%R8

    (585) 0x462871 CMP	(%R8),%RAX

    (585) 0x462874 JE	46287f

    (585) 0x462876 INCQ	(%R10)

    (585) 0x462879 MOV	%RAX,(%R8)

    (585) 0x46287c INC	%RCX

    (585) 0x46287f MOV	0x10(%RBX),%RSI

    (585) 0x462883 LEA	(%R13,%RSI,8),%R8

    (585) 0x462888 CMP	(%R8),%RAX

    (585) 0x46288b JE	462896

    (585) 0x46288d INCQ	(%R10)

    (585) 0x462890 MOV	%RAX,(%R8)

    (585) 0x462893 INC	%RCX

    (585) 0x462896 MOV	0x18(%RBX),%RSI

    (585) 0x46289a LEA	(%R13,%RSI,8),%R8

    (585) 0x46289f CMP	(%R8),%RAX

    (585) 0x4628a2 JE	4628ad

    (585) 0x4628a4 INCQ	(%R10)

    (585) 0x4628a7 MOV	%RAX,(%R8)

    (585) 0x4628aa INC	%RCX

    (585) 0x4628ad MOV	0x20(%RBX),%RSI

    (585) 0x4628b1 LEA	(%R13,%RSI,8),%R8

    (585) 0x4628b6 CMP	(%R8),%RAX

    (585) 0x4628b9 JE	4628c4

    (585) 0x4628bb INCQ	(%R10)

    (585) 0x4628be MOV	%RAX,(%R8)

    (585) 0x4628c1 INC	%RCX

    (585) 0x4628c4 MOV	0x28(%RBX),%RSI

    (585) 0x4628c8 LEA	(%R13,%RSI,8),%R8

    (585) 0x4628cd CMP	(%R8),%RAX

    (585) 0x4628d0 JE	4628db

    (585) 0x4628d2 INCQ	(%R10)

    (585) 0x4628d5 MOV	%RAX,(%R8)

    (585) 0x4628d8 INC	%RCX

    (585) 0x4628db MOV	0x30(%RBX),%RSI

    (585) 0x4628df LEA	(%R13,%RSI,8),%R8

    (585) 0x4628e4 CMP	(%R8),%RAX

    (585) 0x4628e7 JE	4628f2

    (585) 0x4628e9 INCQ	(%R10)

    (585) 0x4628ec MOV	%RAX,(%R8)

    (585) 0x4628ef INC	%RCX

    (585) 0x4628f2 LEA	0x38(%RBX),%RSI

    (585) 0x4628f6 CMP	%RSI,%R12

    (585) 0x4628f9 JNE	462837

  (584) 0x4628ff MOV	%R10,-0x38(%RBP)

  (584) 0x462903 MOV	-0x90(%RBP),%R12

  (584) 0x46290a INC	%RDX

  (584) 0x46290d MOV	(%R12),%R8

  (584) 0x462911 CMP	%R8,%RDX

  (584) 0x462914 JL	4624ac

(581) 0x46291a NOPW	(%RAX,%RAX,1)

(581) 0x462920 MOV	-0xc0(%RBP),%RSI

(581) 0x462927 MOV	-0xc8(%RBP),%RBX

(581) 0x46292e MOV	-0x60(%RBP),%R11

(581) 0x462932 MOV	(%RBX,%RAX,8),%RDX

(581) 0x462936 ADD	%RSI,%RBX

(581) 0x462939 MOV	-0x58(%RBP),%R14

(581) 0x46293d MOV	(%RBX),%R8

(581) 0x462940 LEA	(%R11,%RSI,1),%R12

(581) 0x462944 LEA	(%R14,%RSI,1),%R10

(581) 0x462948 CMP	%R8,%RDX

(581) 0x46294b JGE	462be0

(581) 0x462951 MOV	%RBX,-0x90(%RBP)

(581) 0x462958 MOV	%R12,-0x88(%RBP)

(581) 0x46295f MOV	%R10,-0x38(%RBP)

(581) 0x462963 MOV	-0x50(%RBP),%R14

(581) 0x462967 MOV	-0xd8(%RBP),%RBX

(581) 0x46296e JMP	46298c

0x462970 NOPW	%CS:(%RAX,%RAX,1)

0x46297b NOPL	(%RAX,%RAX,1)

  (582) 0x462980 INC	%RDX

  (582) 0x462983 CMP	%R8,%RDX

  (582) 0x462986 JGE	462be0

  (582) 0x46298c MOV	(%R14,%RDX,8),%RSI

  (582) 0x462990 LEA	(,%RSI,8),%R12

  (582) 0x462998 CMP	%R9,(%RBX,%RSI,8)

  (582) 0x46299c JNE	462980

  (582) 0x46299e MOV	-0xa0(%RBP),%R11

  (582) 0x4629a5 MOV	-0x98(%RBP),%R10

  (582) 0x4629ac MOV	(%R11,%RSI,8),%RSI

  (582) 0x4629b0 MOV	0x8(%R10,%R12,1),%R12

  (582) 0x4629b5 ADD	%RSI,%R12

  (582) 0x4629b8 CMP	%R12,%RSI

  (582) 0x4629bb JGE	462980

  (582) 0x4629bd MOV	-0xa8(%RBP),%R8

  (582) 0x4629c4 MOV	-0x70(%RBP),%R11

  (582) 0x4629c8 MOV	(%R8,%R11,1),%R10

  (582) 0x4629cc LEA	(%R10,%R12,8),%R12

  (582) 0x4629d0 LEA	(%R10,%RSI,8),%RSI

  (582) 0x4629d4 MOV	%R12,%R8

  (582) 0x4629d7 SUB	%RSI,%R8

  (582) 0x4629da SUB	$0x8,%R8

  (582) 0x4629de SHR	$0x3,%R8

  (582) 0x4629e2 INC	%R8

  (582) 0x4629e5 AND	$0x3,%R8D

  (582) 0x4629e9 JE	462a79

  (582) 0x4629ef CMP	$0x1,%R8

  (582) 0x4629f3 JE	462a49

  (582) 0x4629f5 CMP	$0x2,%R8

  (582) 0x4629f9 JE	462a22

  (582) 0x4629fb MOV	(%RSI),%R11

  (582) 0x4629fe TEST	%R11,%R11

  (582) 0x462a01 JS	462da0

  (582) 0x462a07 LEA	(%R13,%R11,8),%R8

  (582) 0x462a0c CMP	(%R8),%RAX

  (582) 0x462a0f JE	462a1e

  (582) 0x462a11 MOV	-0x38(%RBP),%R10

  (582) 0x462a15 INC	%RCX

  (582) 0x462a18 INCQ	(%R10)

  (582) 0x462a1b MOV	%RAX,(%R8)

  (582) 0x462a1e ADD	$0x8,%RSI

  (582) 0x462a22 MOV	(%RSI),%R10

  (582) 0x462a25 TEST	%R10,%R10

  (582) 0x462a28 JS	462d78

  (582) 0x462a2e LEA	(%R13,%R10,8),%R11

  (582) 0x462a33 CMP	(%R11),%RAX

  (582) 0x462a36 JE	462a45

  (582) 0x462a38 MOV	-0x38(%RBP),%R8

  (582) 0x462a3c INC	%RCX

  (582) 0x462a3f INCQ	(%R8)

  (582) 0x462a42 MOV	%RAX,(%R11)

  (582) 0x462a45 ADD	$0x8,%RSI

  (582) 0x462a49 MOV	(%RSI),%R8

  (582) 0x462a4c TEST	%R8,%R8

  (582) 0x462a4f JS	462d50

  (582) 0x462a55 LEA	(%R13,%R8,8),%R11

  (582) 0x462a5a CMP	(%R11),%RAX

  (582) 0x462a5d JE	462a6c

  (582) 0x462a5f MOV	-0x38(%RBP),%R10

  (582) 0x462a63 INC	%RCX

  (582) 0x462a66 INCQ	(%R10)

  (582) 0x462a69 MOV	%RAX,(%R11)

  (582) 0x462a6c ADD	$0x8,%RSI

  (582) 0x462a70 CMP	%RSI,%R12

  (582) 0x462a73 JE	462bc7

  (582) 0x462a79 MOV	-0x88(%RBP),%R11

  (582) 0x462a80 MOV	-0x38(%RBP),%R10

  (582) 0x462a84 JMP	462b14

0x462a89 NOPL	(%RAX)

    (583) 0x462a90 LEA	(%R13,%R8,8),%R8

    (583) 0x462a95 CMP	(%R8),%RAX

    (583) 0x462a98 JE	462aa3

    (583) 0x462a9a INCQ	(%R10)

    (583) 0x462a9d MOV	%RAX,(%R8)

    (583) 0x462aa0 INC	%RCX

    (583) 0x462aa3 LEA	0x8(%RSI),%R8

    (583) 0x462aa7 MOV	0x8(%RSI),%RSI

    (583) 0x462aab TEST	%RSI,%RSI

    (583) 0x462aae JS	462b4a

    (583) 0x462ab4 LEA	(%R13,%RSI,8),%RSI

    (583) 0x462ab9 CMP	(%RSI),%RAX

    (583) 0x462abc JE	462ac7

    (583) 0x462abe INCQ	(%R10)

    (583) 0x462ac1 MOV	%RAX,(%RSI)

    (583) 0x462ac4 INC	%RCX

    (583) 0x462ac7 MOV	0x8(%R8),%RSI

    (583) 0x462acb TEST	%RSI,%RSI

    (583) 0x462ace JS	462b70

    (583) 0x462ad4 LEA	(%R13,%RSI,8),%RSI

    (583) 0x462ad9 CMP	(%RSI),%RAX

    (583) 0x462adc JE	462ae7

    (583) 0x462ade INCQ	(%R10)

    (583) 0x462ae1 MOV	%RAX,(%RSI)

    (583) 0x462ae4 INC	%RCX

    (583) 0x462ae7 MOV	0x10(%R8),%RSI

    (583) 0x462aeb TEST	%RSI,%RSI

    (583) 0x462aee JS	462b96

    (583) 0x462af4 LEA	(%R13,%RSI,8),%RSI

    (583) 0x462af9 CMP	(%RSI),%RAX

    (583) 0x462afc JE	462b07

    (583) 0x462afe INCQ	(%R10)

    (583) 0x462b01 MOV	%RAX,(%RSI)

    (583) 0x462b04 INC	%RCX

    (583) 0x462b07 LEA	0x18(%R8),%RSI

    (583) 0x462b0b CMP	%RSI,%R12

    (583) 0x462b0e JE	462bbc

    (583) 0x462b14 MOV	(%RSI),%R8

    (583) 0x462b17 TEST	%R8,%R8

    (583) 0x462b1a JNS	462a90

    (583) 0x462b20 NOT	%R8

    (583) 0x462b23 LEA	(%R15,%R8,8),%R8

    (583) 0x462b27 CMP	(%R8),%RAX

    (583) 0x462b2a JE	462aa3

    (583) 0x462b30 INCQ	(%R11)

    (583) 0x462b33 MOV	%RAX,(%R8)

    (583) 0x462b36 LEA	0x8(%RSI),%R8

    (583) 0x462b3a INC	%RDI

    (583) 0x462b3d MOV	0x8(%RSI),%RSI

    (583) 0x462b41 TEST	%RSI,%RSI

    (583) 0x462b44 JNS	462ab4

    (583) 0x462b4a NOT	%RSI

    (583) 0x462b4d LEA	(%R15,%RSI,8),%RSI

    (583) 0x462b51 CMP	(%RSI),%RAX

    (583) 0x462b54 JE	462ac7

    (583) 0x462b5a INCQ	(%R11)

    (583) 0x462b5d MOV	%RAX,(%RSI)

    (583) 0x462b60 INC	%RDI

    (583) 0x462b63 MOV	0x8(%R8),%RSI

    (583) 0x462b67 TEST	%RSI,%RSI

    (583) 0x462b6a JNS	462ad4

    (583) 0x462b70 NOT	%RSI

    (583) 0x462b73 LEA	(%R15,%RSI,8),%RSI

    (583) 0x462b77 CMP	(%RSI),%RAX

    (583) 0x462b7a JE	462ae7

    (583) 0x462b80 INCQ	(%R11)

    (583) 0x462b83 MOV	%RAX,(%RSI)

    (583) 0x462b86 INC	%RDI

    (583) 0x462b89 MOV	0x10(%R8),%RSI

    (583) 0x462b8d TEST	%RSI,%RSI

    (583) 0x462b90 JNS	462af4

    (583) 0x462b96 NOT	%RSI

    (583) 0x462b99 LEA	(%R15,%RSI,8),%RSI

    (583) 0x462b9d CMP	(%RSI),%RAX

    (583) 0x462ba0 JE	462b07

    (583) 0x462ba6 INCQ	(%R11)

    (583) 0x462ba9 MOV	%RAX,(%RSI)

    (583) 0x462bac LEA	0x18(%R8),%RSI

    (583) 0x462bb0 INC	%RDI

    (583) 0x462bb3 CMP	%RSI,%R12

    (583) 0x462bb6 JNE	462b14

  (582) 0x462bbc MOV	%R11,-0x88(%RBP)

  (582) 0x462bc3 MOV	%R10,-0x38(%RBP)

  (582) 0x462bc7 MOV	-0x90(%RBP),%R12

  (582) 0x462bce INC	%RDX

  (582) 0x462bd1 MOV	(%R12),%R8

  (582) 0x462bd5 CMP	%R8,%RDX

  (582) 0x462bd8 JL	46298c

(581) 0x462bde XCHG	%AX,%AX

(581) 0x462be0 INCQ	-0x68(%RBP)

(581) 0x462be4 MOV	-0x68(%RBP),%R11

(581) 0x462be8 CMP	%R11,-0xb8(%RBP)

(581) 0x462bef JG	462420

0x462bf5 MOV	-0x128(%RBP),%R8

0x462bfc MOV	-0x130(%RBP),%R10

0x462c03 MOV	-0x70(%RBP),%R14

0x462c07 MOV	-0x138(%RBP),%R11

0x462c0e MOV	-0x110(%RBP),%R12

0x462c15 MOV	%R11,-0x70(%RBP)

0x462c19 TEST	%R12,%R12

0x462c1c JNE	462dc5

0x462c22 MOV	-0x120(%RBP),%RBX

0x462c29 MOV	-0x150(%RBP),%R11

0x462c30 MOV	%R10,-0x38(%RBP)

0x462c34 MOV	%R11,(%RBX)

0x462c37 MOV	%RCX,(%R8)

0x462c3a MOV	%RDI,(%R10)

0x462c3d MOV	%R8,-0x68(%RBP)

0x462c41 MOV	$0x1,%R12D

0x462c47 CALL	411290 <GOMP_barrier@plt>

0x462c4c CMPQ	$0x1,(%RBX)

0x462c50 MOV	-0x120(%RBP),%RAX

0x462c57 MOV	-0x38(%RBP),%R10

0x462c5b MOV	-0x68(%RBP),%RDI

0x462c5f MOV	-0x70(%RBP),%RCX

0x462c63 JLE	462c9a

0x462c65 NOPW	%CS:(%RAX,%RAX,1)

0x462c70 NOPW	%CS:(%RAX,%RAX,1)

0x462c7b NOPL	(%RAX,%RAX,1)

(580) 0x462c80 MOV	-0x8(%RDI,%R12,8),%RDX

(580) 0x462c85 ADD	%RDX,(%RDI,%R12,8)

(580) 0x462c89 MOV	-0x8(%R10,%R12,8),%RSI

(580) 0x462c8e ADD	%RSI,(%R10,%R12,8)

(580) 0x462c92 INC	%R12

(580) 0x462c95 CMP	%R12,(%RAX)

(580) 0x462c98 JG	462c80

0x462c9a MOV	%RCX,-0x70(%RBP)

0x462c9e MOV	%R10,-0x68(%RBP)

0x462ca2 MOV	%RDI,-0x38(%RBP)

0x462ca6 CALL	411290 <GOMP_barrier@plt>

0x462cab MOV	-0x38(%RBP),%R9

0x462caf MOV	-0x68(%RBP),%R8

0x462cb3 MOV	-0x70(%RBP),%R11

0x462cb7 MOV	-0x120(%RBP),%RBX

0x462cbe MOV	-0x148(%RBP),%RAX

0x462cc5 MOV	(%RBX),%R12

0x462cc8 MOV	-0xe8(%RBP),%R10

0x462ccf SAL	$0x3,%R12

0x462cd3 MOV	-0x8(%R8,%R12,1),%RDI

0x462cd8 MOV	-0x8(%R9,%R12,1),%RBX

0x462cdd ADD	%RDI,0x78(%RAX)

0x462ce1 ADD	%RBX,0xb0(%RAX)

0x462ce8 MOV	$0x8,%ESI

0x462ced LEA	(%R10,%R14,1),%R12

0x462cf1 MOV	%R11,-0x38(%RBP)

0x462cf5 CALL	5523b0 <hypre_CAlloc>

0x462cfa TEST	%RBX,%RBX

0x462cfd MOV	%RAX,(%R12)

0x462d01 MOV	-0x38(%RBP),%RDI

0x462d05 JNE	46380d

0x462d0b MOV	-0x148(%RBP),%RCX

0x462d12 MOV	0xa8(%RCX),%RDX

0x462d19 CMPQ	$0x1,(%RDX)

0x462d1d JLE	463845

0x462d23 MOV	-0xe0(%RBP),%RSI

0x462d2a MOV	-0xf0(%RBP),%R9

0x462d31 MOVQ	$0,(%RSI,%R9,8)

0x462d39 CALL	411290 <GOMP_barrier@plt>

0x462d3e MOV	-0x38(%RBP),%R11

0x462d42 XOR	%EAX,%EAX

0x462d44 XOR	%ESI,%ESI

0x462d46 JMP	462f7b

0x462d4b NOPL	(%RAX,%RAX,1)

  (582) 0x462d50 NOT	%R8

  (582) 0x462d53 LEA	(%R15,%R8,8),%R8

  (582) 0x462d57 CMP	(%R8),%RAX

  (582) 0x462d5a JE	462a6c

  (582) 0x462d60 MOV	-0x88(%RBP),%R11

  (582) 0x462d67 INC	%RDI

  (582) 0x462d6a INCQ	(%R11)

  (582) 0x462d6d MOV	%RAX,(%R8)

  (582) 0x462d70 JMP	462a6c

0x462d75 NOPL	(%RAX)

  (582) 0x462d78 NOT	%R10

  (582) 0x462d7b LEA	(%R15,%R10,8),%R11

  (582) 0x462d7f CMP	(%R11),%RAX

  (582) 0x462d82 JE	462a45

  (582) 0x462d88 MOV	-0x88(%RBP),%R10

  (582) 0x462d8f INC	%RDI

  (582) 0x462d92 INCQ	(%R10)

  (582) 0x462d95 MOV	%RAX,(%R11)

  (582) 0x462d98 JMP	462a45

0x462d9d NOPL	(%RAX)

  (582) 0x462da0 NOT	%R11

  (582) 0x462da3 LEA	(%R15,%R11,8),%R11

  (582) 0x462da7 CMP	(%R11),%RAX

  (582) 0x462daa JE	462a1e

  (582) 0x462db0 MOV	-0x88(%RBP),%R8

  (582) 0x462db7 INC	%RDI

  (582) 0x462dba INCQ	(%R8)

  (582) 0x462dbd MOV	%RAX,(%R11)

  (582) 0x462dc0 JMP	462a1e

0x462dc5 MOV	%RCX,(%R8,%R12,8)

0x462dc9 MOV	%RDI,(%R10,%R12,8)

0x462dcd MOV	%R8,-0x68(%RBP)

0x462dd1 MOV	%R10,-0x38(%RBP)

0x462dd5 CALL	411290 <GOMP_barrier@plt>

0x462dda CALL	411290 <GOMP_barrier@plt>

0x462ddf TEST	%R12,%R12

0x462de2 MOV	-0x38(%RBP),%R8

0x462de6 MOV	-0x68(%RBP),%R9

0x462dea MOV	-0x70(%RBP),%R11

0x462dee LEA	(,%R12,8),%RBX

0x462df6 JLE	462cb7

0x462dfc MOV	-0xf8(%RBP),%R10

0x462e03 LEA	-0x8(%RBX),%RSI

0x462e07 LEA	(%R8,%RSI,1),%R12

0x462e0b LEA	(%R9,%RSI,1),%RBX

0x462e0f CMP	%R10,-0x100(%RBP)

0x462e16 JLE	46383b

0x462e1c MOV	-0xb0(%RBP),%RAX

0x462e23 MOV	(%R12),%RCX

0x462e27 MOV	(%RAX,%R11,8),%R9

0x462e2b MOV	-0x80(%RBP),%R8

0x462e2f MOV	%R9,-0x38(%RBP)

0x462e33 SAL	$0x3,%R9

0x462e37 ADD	%RCX,(%R8,%R9,1)

0x462e3b MOV	-0xb8(%RBP),%RDI

0x462e42 MOV	-0x78(%RBP),%RSI

0x462e46 MOV	%R11,%RDX

0x462e49 MOV	(%RBX),%R10

0x462e4c NOT	%RDX

0x462e4f ADD	%R10,(%RSI,%R9,1)

0x462e53 ADD	%RDI,%RDX

0x462e56 LEA	0x1(%R11),%R10

0x462e5a AND	$0x3,%EDX

0x462e5d CMP	%R10,%RDI

0x462e60 JLE	462f67

0x462e66 TEST	%RDX,%RDX

0x462e69 JE	4637c8

0x462e6f CMP	$0x1,%RDX

0x462e73 JE	462eb0

0x462e75 CMP	$0x2,%RDX

0x462e79 JNE	4637de

0x462e7f MOV	-0xb0(%RBP),%RSI

0x462e86 MOV	(%R12),%R9

0x462e8a MOV	(%RSI,%R10,8),%RDX

0x462e8e MOV	-0x80(%RBP),%RDI

0x462e92 LEA	(,%RDX,8),%RAX

0x462e9a ADD	%R9,(%RDI,%RAX,1)

0x462e9e MOV	-0x78(%RBP),%R8

0x462ea2 MOV	%RDX,-0x38(%RBP)

0x462ea6 INC	%R10

0x462ea9 MOV	(%RBX),%RCX

0x462eac ADD	%RCX,(%R8,%RAX,1)

0x462eb0 MOV	-0xb0(%RBP),%RSI

0x462eb7 MOV	(%R12),%R9

0x462ebb MOV	(%RSI,%R10,8),%RDX

0x462ebf MOV	-0x80(%RBP),%RDI

0x462ec3 LEA	(,%RDX,8),%RAX

0x462ecb ADD	%R9,(%RDI,%RAX,1)

0x462ecf MOV	-0x78(%RBP),%R8

0x462ed3 INC	%R10

0x462ed6 MOV	%RDX,-0x38(%RBP)

0x462eda MOV	(%RBX),%RCX

0x462edd ADD	%RCX,(%R8,%RAX,1)

0x462ee1 CMP	%R10,-0xb8(%RBP)

0x462ee8 JLE	462f67

0x462eea MOV	-0x80(%RBP),%RAX

0x462eee MOV	-0xb0(%RBP),%RDI

0x462ef5 MOV	-0xb8(%RBP),%RCX

0x462efc MOV	%R8,%RDX

(579) 0x462eff MOV	(%RDI,%R10,8),%RSI

(579) 0x462f03 MOV	(%R12),%R9

(579) 0x462f07 SAL	$0x3,%RSI

(579) 0x462f0b ADD	%R9,(%RAX,%RSI,1)

(579) 0x462f0f MOV	(%RBX),%R8

(579) 0x462f12 ADD	%R8,(%RDX,%RSI,1)

(579) 0x462f16 MOV	0x8(%RDI,%R10,8),%RSI

(579) 0x462f1b MOV	(%R12),%R9

(579) 0x462f1f SAL	$0x3,%RSI

(579) 0x462f23 ADD	%R9,(%RAX,%RSI,1)

(579) 0x462f27 MOV	(%RBX),%R8

(579) 0x462f2a ADD	%R8,(%RDX,%RSI,1)

(579) 0x462f2e MOV	0x10(%RDI,%R10,8),%RSI

(579) 0x462f33 MOV	(%R12),%R9

(579) 0x462f37 SAL	$0x3,%RSI

(579) 0x462f3b ADD	%R9,(%RAX,%RSI,1)

(579) 0x462f3f MOV	(%RBX),%R8

(579) 0x462f42 ADD	%R8,(%RDX,%RSI,1)

(579) 0x462f46 MOV	0x18(%RDI,%R10,8),%RSI

(579) 0x462f4b MOV	(%R12),%R9

(579) 0x462f4f SAL	$0x3,%RSI

(579) 0x462f53 ADD	%R9,(%RAX,%RSI,1)

(579) 0x462f57 ADD	$0x4,%R10

(579) 0x462f5b MOV	(%RBX),%R8

(579) 0x462f5e ADD	%R8,(%RDX,%RSI,1)

(579) 0x462f62 CMP	%R10,%RCX

(579) 0x462f65 JG	462eff

0x462f67 MOV	%R11,-0x38(%RBP)

0x462f6b CALL	411290 <GOMP_barrier@plt>

0x462f70 MOV	(%R12),%RSI

0x462f74 MOV	(%RBX),%RAX

0x462f77 MOV	-0x38(%RBP),%R11

0x462f7b MOV	-0xf0(%RBP),%RBX

0x462f82 MOV	-0xf8(%RBP),%R10

0x462f89 DEC	%RBX

0x462f8c CMP	%R10,-0x100(%RBP)

0x462f93 JLE	46362d

0x462f99 MOV	%RAX,-0x88(%RBP)

0x462fa0 MOV	%R11,-0x70(%RBP)

0x462fa4 MOV	-0xe0(%RBP),%R9

0x462fab MOV	-0xe8(%RBP),%R10

0x462fb2 MOV	%R15,%R12

0x462fb5 MOV	%R13,%R15

0x462fb8 NOPL	(%RAX,%RAX,1)

(573) 0x462fc0 MOV	-0xb0(%RBP),%R13

(573) 0x462fc7 MOV	-0x70(%RBP),%RDI

(573) 0x462fcb MOV	-0xd0(%RBP),%R8

(573) 0x462fd2 MOV	(%R13,%RDI,8),%RDI

(573) 0x462fd7 LEA	0x8(,%RDI,8),%R11

(573) 0x462fdf MOV	(%R8,%RDI,8),%RCX

(573) 0x462fe3 ADD	%R11,%R8

(573) 0x462fe6 MOV	%R8,-0x90(%RBP)

(573) 0x462fed MOV	(%R8),%R8

(573) 0x462ff0 MOV	%RDI,%RAX

(573) 0x462ff3 MOV	%RCX,-0x38(%RBP)

(573) 0x462ff7 NOT	%RAX

(573) 0x462ffa CMP	%R8,%RCX

(573) 0x462ffd JGE	463340

(573) 0x463003 MOV	%RDI,-0xc0(%RBP)

(573) 0x46300a MOV	%R11,-0xe0(%RBP)

(573) 0x463011 MOV	-0x88(%RBP),%RDI

(573) 0x463018 MOV	%RBX,%R13

(573) 0x46301b JMP	463051

0x46301d NOPW	%CS:(%RAX,%RAX,1)

0x463028 NOPW	%CS:(%RAX,%RAX,1)

0x463033 NOPW	%CS:(%RAX,%RAX,1)

0x46303e XCHG	%AX,%AX

  (576) 0x463040 INCQ	-0x38(%RBP)

  (576) 0x463044 MOV	-0x38(%RBP),%RDX

  (576) 0x463048 CMP	%R8,%RDX

  (576) 0x46304b JGE	463328

  (576) 0x463051 MOV	-0x38(%RBP),%R11

  (576) 0x463055 MOV	-0x40(%RBP),%RDX

  (576) 0x463059 MOV	-0x48(%RBP),%RBX

  (576) 0x46305d MOV	(%RDX,%R11,8),%RCX

  (576) 0x463061 LEA	(,%RCX,8),%R11

  (576) 0x463069 CMP	%R13,(%RBX,%RCX,8)

  (576) 0x46306d JNE	463040

  (576) 0x46306f MOV	-0x80(%RBP),%R8

  (576) 0x463073 MOV	-0x60(%RBP),%RDX

  (576) 0x463077 MOV	(%R8,%RCX,8),%R8

  (576) 0x46307b MOV	0x8(%RDX,%R11,1),%RBX

  (576) 0x463080 ADD	%R8,%RBX

  (576) 0x463083 CMP	%RBX,%R8

  (576) 0x463086 JGE	4631e4

  (576) 0x46308c MOV	-0x8(%R10,%R14,1),%RDX

  (576) 0x463091 LEA	(%RDX,%RBX,8),%RBX

  (576) 0x463095 LEA	(%RDX,%R8,8),%R8

  (576) 0x463099 MOV	%RBX,-0x68(%RBP)

  (576) 0x46309d SUB	%R8,%RBX

  (576) 0x4630a0 SUB	$0x8,%RBX

  (576) 0x4630a4 SHR	$0x3,%RBX

  (576) 0x4630a8 INC	%RBX

  (576) 0x4630ab AND	$0x3,%EBX

  (576) 0x4630ae JE	463157

  (576) 0x4630b4 CMP	$0x1,%RBX

  (576) 0x4630b8 JE	46311e

  (576) 0x4630ba CMP	$0x2,%RBX

  (576) 0x4630be JE	4630ef

  (576) 0x4630c0 MOV	(%R8),%RDX

  (576) 0x4630c3 MOV	%RDX,%RBX

  (576) 0x4630c6 LEA	(%R12,%RDX,8),%RDX

  (576) 0x4630ca MOV	%RDX,-0x88(%RBP)

  (576) 0x4630d1 CMP	%RAX,(%RDX)

  (576) 0x4630d4 JE	4630eb

  (576) 0x4630d6 MOV	(%R10,%R14,1),%RDX

  (576) 0x4630da MOV	%RBX,(%RDX,%RSI,8)

  (576) 0x4630de MOV	-0x88(%RBP),%RBX

  (576) 0x4630e5 INC	%RSI

  (576) 0x4630e8 MOV	%RAX,(%RBX)

  (576) 0x4630eb ADD	$0x8,%R8

  (576) 0x4630ef MOV	(%R8),%RDX

  (576) 0x4630f2 MOV	%RDX,%RBX

  (576) 0x4630f5 LEA	(%R12,%RDX,8),%RDX

  (576) 0x4630f9 MOV	%RDX,-0x88(%RBP)

  (576) 0x463100 CMP	%RAX,(%RDX)

  (576) 0x463103 JE	46311a

  (576) 0x463105 MOV	(%R10,%R14,1),%RDX

  (576) 0x463109 MOV	%RBX,(%RDX,%RSI,8)

  (576) 0x46310d MOV	-0x88(%RBP),%RBX

  (576) 0x463114 INC	%RSI

  (576) 0x463117 MOV	%RAX,(%RBX)

  (576) 0x46311a ADD	$0x8,%R8

  (576) 0x46311e MOV	(%R8),%RDX

  (576) 0x463121 MOV	%RDX,%RBX

  (576) 0x463124 LEA	(%R12,%RDX,8),%RDX

  (576) 0x463128 MOV	%RDX,-0x88(%RBP)

  (576) 0x46312f CMP	%RAX,(%RDX)

  (576) 0x463132 JE	463149

  (576) 0x463134 MOV	(%R10,%R14,1),%RDX

  (576) 0x463138 MOV	%RBX,(%RDX,%RSI,8)

  (576) 0x46313c MOV	-0x88(%RBP),%RBX

  (576) 0x463143 INC	%RSI

  (576) 0x463146 MOV	%RAX,(%RBX)

  (576) 0x463149 ADD	$0x8,%R8

  (576) 0x46314d CMP	%R8,-0x68(%RBP)

  (576) 0x463151 JE	4631e4

  (576) 0x463157 MOV	%RCX,-0x88(%RBP)

  (576) 0x46315e MOV	%RDI,%RBX

    (578) 0x463161 MOV	(%R8),%RDI

    (578) 0x463164 LEA	(%R12,%RDI,8),%RDX

    (578) 0x463168 CMP	%RAX,(%RDX)

    (578) 0x46316b JE	46317b

    (578) 0x46316d MOV	(%R10,%R14,1),%RCX

    (578) 0x463171 MOV	%RDI,(%RCX,%RSI,8)

    (578) 0x463175 MOV	%RAX,(%RDX)

    (578) 0x463178 INC	%RSI

    (578) 0x46317b LEA	0x8(%R8),%RDX

    (578) 0x46317f MOV	0x8(%R8),%R8

    (578) 0x463183 LEA	(%R12,%R8,8),%RDI

    (578) 0x463187 CMP	%RAX,(%RDI)

    (578) 0x46318a JE	46319a

    (578) 0x46318c MOV	(%R10,%R14,1),%RCX

    (578) 0x463190 MOV	%R8,(%RCX,%RSI,8)

    (578) 0x463194 MOV	%RAX,(%RDI)

    (578) 0x463197 INC	%RSI

    (578) 0x46319a MOV	0x8(%RDX),%R8

    (578) 0x46319e LEA	(%R12,%R8,8),%RDI

    (578) 0x4631a2 CMP	%RAX,(%RDI)

    (578) 0x4631a5 JE	4631b5

    (578) 0x4631a7 MOV	(%R10,%R14,1),%RCX

    (578) 0x4631ab MOV	%R8,(%RCX,%RSI,8)

    (578) 0x4631af MOV	%RAX,(%RDI)

    (578) 0x4631b2 INC	%RSI

    (578) 0x4631b5 MOV	0x10(%RDX),%R8

    (578) 0x4631b9 LEA	(%R12,%R8,8),%RDI

    (578) 0x4631bd CMP	%RAX,(%RDI)

    (578) 0x4631c0 JE	4631d0

    (578) 0x4631c2 MOV	(%R10,%R14,1),%RCX

    (578) 0x4631c6 MOV	%R8,(%RCX,%RSI,8)

    (578) 0x4631ca MOV	%RAX,(%RDI)

    (578) 0x4631cd INC	%RSI

    (578) 0x4631d0 LEA	0x18(%RDX),%R8

    (578) 0x4631d4 CMP	%R8,-0x68(%RBP)

    (578) 0x4631d8 JNE	463161

  (576) 0x4631da MOV	-0x88(%RBP),%RCX

  (576) 0x4631e1 MOV	%RBX,%RDI

  (576) 0x4631e4 MOV	-0x78(%RBP),%RBX

  (576) 0x4631e8 MOV	-0x58(%RBP),%RDX

  (576) 0x4631ec MOV	(%RBX,%RCX,8),%RCX

  (576) 0x4631f0 MOV	0x8(%RDX,%R11,1),%R8

  (576) 0x4631f5 ADD	%RCX,%R8

  (576) 0x4631f8 CMP	%R8,%RCX

  (576) 0x4631fb JGE	463710

  (576) 0x463201 MOV	-0x8(%R9,%R14,1),%RBX

  (576) 0x463206 LEA	(%RBX,%RCX,8),%RCX

  (576) 0x46320a LEA	(%RBX,%R8,8),%RBX

  (576) 0x46320e MOV	%RBX,%RDX

  (576) 0x463211 SUB	%RCX,%RDX

  (576) 0x463214 SUB	$0x8,%RDX

  (576) 0x463218 SHR	$0x3,%RDX

  (576) 0x46321c INC	%RDX

  (576) 0x46321f AND	$0x3,%EDX

  (576) 0x463222 JE	46328f

  (576) 0x463224 CMP	$0x1,%RDX

  (576) 0x463228 JE	46326c

  (576) 0x46322a CMP	$0x2,%RDX

  (576) 0x46322e JE	46324e

  (576) 0x463230 MOV	(%RCX),%R11

  (576) 0x463233 LEA	(%R15,%R11,8),%R8

  (576) 0x463237 CMP	%RAX,(%R8)

  (576) 0x46323a JE	46324a

  (576) 0x46323c MOV	(%R9,%R14,1),%RDX

  (576) 0x463240 MOV	%R11,(%RDX,%RDI,8)

  (576) 0x463244 MOV	%RAX,(%R8)

  (576) 0x463247 INC	%RDI

  (576) 0x46324a ADD	$0x8,%RCX

  (576) 0x46324e MOV	(%RCX),%R11

  (576) 0x463251 LEA	(%R15,%R11,8),%R8

  (576) 0x463255 CMP	%RAX,(%R8)

  (576) 0x463258 JE	463268

  (576) 0x46325a MOV	(%R9,%R14,1),%RDX

  (576) 0x46325e MOV	%R11,(%RDX,%RDI,8)

  (576) 0x463262 MOV	%RAX,(%R8)

  (576) 0x463265 INC	%RDI

  (576) 0x463268 ADD	$0x8,%RCX

  (576) 0x46326c MOV	(%RCX),%R11

  (576) 0x46326f LEA	(%R15,%R11,8),%R8

  (576) 0x463273 CMP	%RAX,(%R8)

  (576) 0x463276 JE	463286

  (576) 0x463278 MOV	(%R9,%R14,1),%RDX

  (576) 0x46327c MOV	%R11,(%RDX,%RDI,8)

  (576) 0x463280 MOV	%RAX,(%R8)

  (576) 0x463283 INC	%RDI

  (576) 0x463286 ADD	$0x8,%RCX

  (576) 0x46328a CMP	%RBX,%RCX

  (576) 0x46328d JE	463307

    (577) 0x46328f MOV	(%RCX),%R8

    (577) 0x463292 LEA	(%R15,%R8,8),%RDX

    (577) 0x463296 CMP	%RAX,(%RDX)

    (577) 0x463299 JE	4632a9

    (577) 0x46329b MOV	(%R9,%R14,1),%R11

    (577) 0x46329f MOV	%R8,(%R11,%RDI,8)

    (577) 0x4632a3 MOV	%RAX,(%RDX)

    (577) 0x4632a6 INC	%RDI

    (577) 0x4632a9 MOV	0x8(%RCX),%R8

    (577) 0x4632ad LEA	0x8(%RCX),%RDX

    (577) 0x4632b1 LEA	(%R15,%R8,8),%RCX

    (577) 0x4632b5 CMP	%RAX,(%RCX)

    (577) 0x4632b8 JE	4632c8

    (577) 0x4632ba MOV	(%R9,%R14,1),%R11

    (577) 0x4632be MOV	%R8,(%R11,%RDI,8)

    (577) 0x4632c2 MOV	%RAX,(%RCX)

    (577) 0x4632c5 INC	%RDI

    (577) 0x4632c8 MOV	0x8(%RDX),%R8

    (577) 0x4632cc LEA	(%R15,%R8,8),%RCX

    (577) 0x4632d0 CMP	%RAX,(%RCX)

    (577) 0x4632d3 JE	4632e3

    (577) 0x4632d5 MOV	(%R9,%R14,1),%R11

    (577) 0x4632d9 MOV	%R8,(%R11,%RDI,8)

    (577) 0x4632dd MOV	%RAX,(%RCX)

    (577) 0x4632e0 INC	%RDI

    (577) 0x4632e3 MOV	0x10(%RDX),%R8

    (577) 0x4632e7 LEA	(%R15,%R8,8),%RCX

    (577) 0x4632eb CMP	%RAX,(%RCX)

    (577) 0x4632ee JE	4632fe

    (577) 0x4632f0 MOV	(%R9,%R14,1),%R11

    (577) 0x4632f4 MOV	%R8,(%R11,%RDI,8)

    (577) 0x4632f8 MOV	%RAX,(%RCX)

    (577) 0x4632fb INC	%RDI

    (577) 0x4632fe LEA	0x18(%RDX),%RCX

    (577) 0x463302 CMP	%RBX,%RCX

    (577) 0x463305 JNE	46328f

  (576) 0x463307 INCQ	-0x38(%RBP)

  (576) 0x46330b MOV	-0x90(%RBP),%RBX

  (576) 0x463312 MOV	(%RBX),%R8

  (576) 0x463315 MOV	-0x38(%RBP),%RDX

  (576) 0x463319 CMP	%R8,%RDX

  (576) 0x46331c JL	463051

(573) 0x463322 NOPW	(%RAX,%RAX,1)

(573) 0x463328 MOV	%RDI,-0x88(%RBP)

(573) 0x46332f MOV	-0xe0(%RBP),%R11

(573) 0x463336 MOV	-0xc0(%RBP),%RDI

(573) 0x46333d MOV	%R13,%RBX

(573) 0x463340 MOV	-0xc8(%RBP),%RCX

(573) 0x463347 MOV	(%RCX,%RDI,8),%RAX

(573) 0x46334b ADD	%R11,%RCX

(573) 0x46334e MOV	%RCX,-0xc0(%RBP)

(573) 0x463355 MOV	(%RCX),%RCX

(573) 0x463358 NOT	%RDI

(573) 0x46335b CMP	%RAX,%RCX

(573) 0x46335e JLE	463612

(573) 0x463364 MOV	%R9,-0x68(%RBP)

(573) 0x463368 MOV	%R10,-0x90(%RBP)

(573) 0x46336f MOV	-0x88(%RBP),%R8

(573) 0x463376 MOV	-0xd8(%RBP),%R13

(573) 0x46337d JMP	46338c

0x46337f NOP

  (574) 0x463380 INC	%RAX

  (574) 0x463383 CMP	%RCX,%RAX

  (574) 0x463386 JGE	463600

  (574) 0x46338c MOV	-0x50(%RBP),%R9

  (574) 0x463390 MOV	(%R9,%RAX,8),%RDX

  (574) 0x463394 LEA	(,%RDX,8),%R11

  (574) 0x46339c CMP	%RBX,(%R13,%RDX,8)

  (574) 0x4633a1 JNE	463380

  (574) 0x4633a3 MOV	-0xa0(%RBP),%R10

  (574) 0x4633aa MOV	-0x98(%RBP),%R9

  (574) 0x4633b1 MOV	(%R10,%RDX,8),%RDX

  (574) 0x4633b5 MOV	0x8(%R9,%R11,1),%R11

  (574) 0x4633ba ADD	%RDX,%R11

  (574) 0x4633bd CMP	%R11,%RDX

  (574) 0x4633c0 JGE	463380

  (574) 0x4633c2 MOV	-0xa8(%RBP),%RCX

  (574) 0x4633c9 MOV	(%RCX,%R14,1),%R10

  (574) 0x4633cd LEA	(%R10,%R11,8),%R9

  (574) 0x4633d1 LEA	(%R10,%RDX,8),%RDX

  (574) 0x4633d5 MOV	%R9,-0x38(%RBP)

  (574) 0x4633d9 SUB	%RDX,%R9

  (574) 0x4633dc SUB	$0x8,%R9

  (574) 0x4633e0 SHR	$0x3,%R9

  (574) 0x4633e4 INC	%R9

  (574) 0x4633e7 AND	$0x3,%R9D

  (574) 0x4633eb JE	463488

  (574) 0x4633f1 CMP	$0x1,%R9

  (574) 0x4633f5 JE	463453

  (574) 0x4633f7 CMP	$0x2,%R9

  (574) 0x4633fb JE	463428

  (574) 0x4633fd MOV	(%RDX),%RCX

  (574) 0x463400 TEST	%RCX,%RCX

  (574) 0x463403 JS	463720

  (574) 0x463409 LEA	(%R15,%RCX,8),%R11

  (574) 0x46340d CMP	%RDI,(%R11)

  (574) 0x463410 JE	463424

  (574) 0x463412 MOV	-0x68(%RBP),%R10

  (574) 0x463416 MOV	(%R10,%R14,1),%R9

  (574) 0x46341a MOV	%RCX,(%R9,%R8,8)

  (574) 0x46341e MOV	%RDI,(%R11)

  (574) 0x463421 INC	%R8

  (574) 0x463424 ADD	$0x8,%RDX

  (574) 0x463428 MOV	(%RDX),%RCX

  (574) 0x46342b TEST	%RCX,%RCX

  (574) 0x46342e JS	4636e0

  (574) 0x463434 LEA	(%R15,%RCX,8),%R10

  (574) 0x463438 CMP	%RDI,(%R10)

  (574) 0x46343b JE	46344f

  (574) 0x46343d MOV	-0x68(%RBP),%R9

  (574) 0x463441 MOV	(%R9,%R14,1),%R11

  (574) 0x463445 MOV	%RCX,(%R11,%R8,8)

  (574) 0x463449 MOV	%RDI,(%R10)

  (574) 0x46344c INC	%R8

  (574) 0x46344f ADD	$0x8,%RDX

  (574) 0x463453 MOV	(%RDX),%RCX

  (574) 0x463456 TEST	%RCX,%RCX

  (574) 0x463459 JS	4636b0

  (574) 0x46345f LEA	(%R15,%RCX,8),%R11

  (574) 0x463463 CMP	%RDI,(%R11)

  (574) 0x463466 JE	46347a

  (574) 0x463468 MOV	-0x68(%RBP),%R9

  (574) 0x46346c MOV	(%R9,%R14,1),%R10

  (574) 0x463470 MOV	%RCX,(%R10,%R8,8)

  (574) 0x463474 MOV	%RDI,(%R11)

  (574) 0x463477 INC	%R8

  (574) 0x46347a ADD	$0x8,%RDX

  (574) 0x46347e CMP	%RDX,-0x38(%RBP)

  (574) 0x463482 JE	4635e7

  (574) 0x463488 MOV	%RAX,-0x88(%RBP)

  (574) 0x46348f MOV	-0x68(%RBP),%R9

  (574) 0x463493 MOV	-0x90(%RBP),%R10

  (574) 0x46349a JMP	46350d

0x46349c NOPL	(%RAX)

    (575) 0x4634a0 LEA	(%R15,%RDX,8),%R11

    (575) 0x4634a4 CMP	%RDI,(%R11)

    (575) 0x4634a7 JE	4634b7

    (575) 0x4634a9 MOV	(%R9,%R14,1),%RAX

    (575) 0x4634ad MOV	%RDX,(%RAX,%R8,8)

    (575) 0x4634b1 MOV	%RDI,(%R11)

    (575) 0x4634b4 INC	%R8

    (575) 0x4634b7 MOV	0x8(%RCX),%RDX

    (575) 0x4634bb TEST	%RDX,%RDX

    (575) 0x4634be JS	463572

    (575) 0x4634c4 LEA	(%R15,%RDX,8),%R11

    (575) 0x4634c8 CMP	%RDI,(%R11)

    (575) 0x4634cb JE	4634db

    (575) 0x4634cd MOV	(%R9,%R14,1),%RAX

    (575) 0x4634d1 MOV	%RDX,(%RAX,%R8,8)

    (575) 0x4634d5 MOV	%RDI,(%R11)

    (575) 0x4634d8 INC	%R8

    (575) 0x4634db MOV	0x10(%RCX),%RDX

    (575) 0x4634df TEST	%RDX,%RDX

    (575) 0x4634e2 JS	4635a3

    (575) 0x4634e8 LEA	(%R15,%RDX,8),%R11

    (575) 0x4634ec CMP	%RDI,(%R11)

    (575) 0x4634ef JE	4634ff

    (575) 0x4634f1 MOV	(%R9,%R14,1),%RAX

    (575) 0x4634f5 MOV	%RDX,(%RAX,%R8,8)

    (575) 0x4634f9 MOV	%RDI,(%R11)

    (575) 0x4634fc INC	%R8

    (575) 0x4634ff LEA	0x18(%RCX),%RDX

    (575) 0x463503 CMP	%RDX,-0x38(%RBP)

    (575) 0x463507 JE	4635d5

    (575) 0x46350d MOV	(%RDX),%RCX

    (575) 0x463510 TEST	%RCX,%RCX

    (575) 0x463513 JS	463680

    (575) 0x463519 LEA	(%R15,%RCX,8),%R11

    (575) 0x46351d CMP	%RDI,(%R11)

    (575) 0x463520 JE	463530

    (575) 0x463522 MOV	(%R9,%R14,1),%RAX

    (575) 0x463526 MOV	%RCX,(%RAX,%R8,8)

    (575) 0x46352a MOV	%RDI,(%R11)

    (575) 0x46352d INC	%R8

    (575) 0x463530 LEA	0x8(%RDX),%RCX

    (575) 0x463534 MOV	0x8(%RDX),%RDX

    (575) 0x463538 TEST	%RDX,%RDX

    (575) 0x46353b JNS	4634a0

    (575) 0x463541 MOV	%RDX,%R11

    (575) 0x463544 NOT	%R11

    (575) 0x463547 LEA	(%R12,%R11,8),%R11

    (575) 0x46354b CMP	%RDI,(%R11)

    (575) 0x46354e JE	4634b7

    (575) 0x463554 MOV	(%R10,%R14,1),%RAX

    (575) 0x463558 NOT	%RDX

    (575) 0x46355b MOV	%RDX,(%RAX,%RSI,8)

    (575) 0x46355f MOV	%RDI,(%R11)

    (575) 0x463562 INC	%RSI

    (575) 0x463565 MOV	0x8(%RCX),%RDX

    (575) 0x463569 TEST	%RDX,%RDX

    (575) 0x46356c JNS	4634c4

    (575) 0x463572 MOV	%RDX,%R11

    (575) 0x463575 NOT	%R11

    (575) 0x463578 LEA	(%R12,%R11,8),%R11

    (575) 0x46357c CMP	%RDI,(%R11)

    (575) 0x46357f JE	4634db

    (575) 0x463585 MOV	(%R10,%R14,1),%RAX

    (575) 0x463589 NOT	%RDX

    (575) 0x46358c MOV	%RDX,(%RAX,%RSI,8)

    (575) 0x463590 MOV	%RDI,(%R11)

    (575) 0x463593 INC	%RSI

    (575) 0x463596 MOV	0x10(%RCX),%RDX

    (575) 0x46359a TEST	%RDX,%RDX

    (575) 0x46359d JNS	4634e8

    (575) 0x4635a3 MOV	%RDX,%R11

    (575) 0x4635a6 NOT	%R11

    (575) 0x4635a9 LEA	(%R12,%R11,8),%R11

    (575) 0x4635ad CMP	%RDI,(%R11)

    (575) 0x4635b0 JE	4634ff

    (575) 0x4635b6 MOV	(%R10,%R14,1),%RAX

    (575) 0x4635ba NOT	%RDX

    (575) 0x4635bd MOV	%RDX,(%RAX,%RSI,8)

    (575) 0x4635c1 LEA	0x18(%RCX),%RDX

    (575) 0x4635c5 MOV	%RDI,(%R11)

    (575) 0x4635c8 INC	%RSI

    (575) 0x4635cb CMP	%RDX,-0x38(%RBP)

    (575) 0x4635cf JNE	46350d

  (574) 0x4635d5 MOV	%R9,-0x68(%RBP)

  (574) 0x4635d9 MOV	%R10,-0x90(%RBP)

  (574) 0x4635e0 MOV	-0x88(%RBP),%RAX

  (574) 0x4635e7 MOV	-0xc0(%RBP),%R9

  (574) 0x4635ee INC	%RAX

  (574) 0x4635f1 MOV	(%R9),%RCX

  (574) 0x4635f4 CMP	%RCX,%RAX

  (574) 0x4635f7 JL	46338c

(573) 0x4635fd NOPL	(%RAX)

(573) 0x463600 MOV	%R8,-0x88(%RBP)

(573) 0x463607 MOV	-0x68(%RBP),%R9

(573) 0x46360b MOV	-0x90(%RBP),%R10

(573) 0x463612 INCQ	-0x70(%RBP)

(573) 0x463616 MOV	-0x70(%RBP),%RDI

(573) 0x46361a CMP	%RDI,-0xb8(%RBP)

(573) 0x463621 JG	462fc0

0x463627 MOV	%R15,%R13

0x46362a MOV	%R12,%R15

0x46362d MOV	%R15,%RDI

0x463630 CALL	552440 <hypre_Free>

0x463635 CMPQ	$0,-0x108(%RBP)

0x46363d JNE	463661

0x46363f MOV	-0x140(%RBP),%R14

0x463646 CMP	%R14,-0x118(%RBP)

0x46364d JE	463661

0x46364f ADD	$0x128,%RSP

0x463656 POP	%RBX

0x463657 POP	%R12

0x463659 POP	%R13

0x46365b POP	%R14

0x46365d POP	%R15

0x46365f POP	%RBP

0x463660 RET

0x463661 ADD	$0x128,%RSP

0x463668 POP	%RBX

0x463669 POP	%R12

0x46366b MOV	%R13,%RDI

0x46366e POP	%R13

0x463670 POP	%R14

0x463672 POP	%R15

0x463674 POP	%RBP

0x463675 JMP	552440

0x46367a NOPW	(%RAX,%RAX,1)

    (575) 0x463680 MOV	%RCX,%R11

    (575) 0x463683 NOT	%R11

    (575) 0x463686 LEA	(%R12,%R11,8),%R11

    (575) 0x46368a CMP	%RDI,(%R11)

    (575) 0x46368d JE	463530

    (575) 0x463693 MOV	(%R10,%R14,1),%RAX

    (575) 0x463697 NOT	%RCX

    (575) 0x46369a MOV	%RCX,(%RAX,%RSI,8)

    (575) 0x46369e MOV	%RDI,(%R11)

    (575) 0x4636a1 INC	%RSI

    (575) 0x4636a4 JMP	463530

0x4636a9 NOPL	(%RAX)

  (574) 0x4636b0 MOV	%RCX,%R11

  (574) 0x4636b3 NOT	%R11

  (574) 0x4636b6 LEA	(%R12,%R11,8),%R10

  (574) 0x4636ba CMP	%RDI,(%R10)

  (574) 0x4636bd JE	46347a

  (574) 0x4636c3 MOV	-0x90(%RBP),%R9

  (574) 0x4636ca NOT	%RCX

  (574) 0x4636cd MOV	(%R9,%R14,1),%R11

  (574) 0x4636d1 MOV	%RCX,(%R11,%RSI,8)

  (574) 0x4636d5 MOV	%RDI,(%R10)

  (574) 0x4636d8 INC	%RSI

  (574) 0x4636db JMP	46347a

  (574) 0x4636e0 MOV	%RCX,%R10

  (574) 0x4636e3 NOT	%R10

  (574) 0x4636e6 LEA	(%R12,%R10,8),%R11

  (574) 0x4636ea CMP	%RDI,(%R11)

  (574) 0x4636ed JE	46344f

  (574) 0x4636f3 MOV	-0x90(%RBP),%R9

  (574) 0x4636fa NOT	%RCX

  (574) 0x4636fd MOV	(%R9,%R14,1),%R10

  (574) 0x463701 MOV	%RCX,(%R10,%RSI,8)

  (574) 0x463705 MOV	%RDI,(%R11)

  (574) 0x463708 INC	%RSI

  (574) 0x46370b JMP	46344f

  (576) 0x463710 MOV	-0x90(%RBP),%R11

  (576) 0x463717 MOV	(%R11),%R8

  (576) 0x46371a JMP	463040

0x46371f NOP

  (574) 0x463720 MOV	%RCX,%R11

  (574) 0x463723 NOT	%R11

  (574) 0x463726 LEA	(%R12,%R11,8),%R10

  (574) 0x46372a CMP	%RDI,(%R10)

  (574) 0x46372d JE	463424

  (574) 0x463733 MOV	-0x90(%RBP),%R9

  (574) 0x46373a NOT	%RCX

  (574) 0x46373d MOV	(%R9,%R14,1),%R11

  (574) 0x463741 MOV	%RCX,(%R11,%RSI,8)

  (574) 0x463745 MOV	%RDI,(%R10)

  (574) 0x463748 INC	%RSI

  (574) 0x46374b JMP	463424

0x463750 MOV	%R11,-0x70(%RBP)

0x463754 MOV	%R10,-0x68(%RBP)

0x463758 MOV	%R8,-0x38(%RBP)

0x46375c MOV	-0x108(%RBP),%R12

0x463763 MOV	$0x8,%ESI

0x463768 MOV	%R12,%RDI

0x46376b CALL	5523b0 <hypre_CAlloc>

0x463770 TEST	%R12,%R12

0x463773 MOV	-0x38(%RBP),%R8

0x463777 MOV	-0x68(%RBP),%R10

0x46377b MOV	-0x70(%RBP),%R11

0x46377f MOV	%RAX,%R13

0x463782 JLE	4623de

0x463788 LEA	(,%R12,8),%RDX

0x463790 MOV	$0xff,%ESI

0x463795 MOV	%RAX,%RDI

0x463798 CALL	4110a0 <memset@plt>

0x46379d MOV	-0x38(%RBP),%R8

0x4637a1 MOV	-0x68(%RBP),%R10

0x4637a5 MOV	-0x70(%RBP),%R11

0x4637a9 JMP	4623de

0x4637ae MOV	%R11,-0x70(%RBP)

0x4637b2 MOV	%R10,-0x68(%RBP)

0x4637b6 MOV	%R8,-0x38(%RBP)

0x4637ba MOV	-0x118(%RBP),%R12

0x4637c1 MOV	$0x8,%ESI

0x4637c6 JMP	463768

0x4637c8 MOV	%RDI,%RCX

0x4637cb MOV	-0x80(%RBP),%RAX

0x4637cf MOV	-0xb0(%RBP),%RDI

0x4637d6 MOV	%RSI,%RDX

0x4637d9 JMP	462eff

0x4637de MOV	-0xb0(%RBP),%RDX

0x4637e5 MOV	(%R12),%R9

0x4637e9 MOV	(%RDX,%R10,8),%RAX

0x4637ed MOV	-0x80(%RBP),%RDI

0x4637f1 SAL	$0x3,%RAX

0x4637f5 ADD	%R9,(%RDI,%RAX,1)

0x4637f9 MOV	-0x78(%RBP),%R8

0x4637fd LEA	0x2(%R11),%R10

0x463801 MOV	(%RBX),%RCX

0x463804 ADD	%RCX,(%R8,%RAX,1)

0x463808 JMP	462e7f

0x46380d MOV	-0xe0(%RBP),%R8

0x463814 MOV	%RDI,-0x38(%RBP)

0x463818 MOV	$0x8,%ESI

0x46381d MOV	%RBX,%RDI

0x463820 LEA	(%R8,%R14,1),%R12

0x463824 CALL	5523b0 <hypre_CAlloc>

0x463829 MOV	%RAX,(%R12)

0x46382d CALL	411290 <GOMP_barrier@plt>

0x463832 MOV	-0x38(%RBP),%R11

0x463836 JMP	462d42

0x46383b CALL	411290 <GOMP_barrier@plt>

0x463840 JMP	46362d

0x463845 MOV	%RDI,-0x38(%RBP)

0x463849 CALL	411290 <GOMP_barrier@plt>

0x46384e MOV	-0x38(%RBP),%R11

0x463852 JMP	462d42

0x463857 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○97.90	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.10	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	par_multi_interp.c:891-1134
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:891,900-927,939-970,976-999,1008-1034,1040-1125,1132-1134.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 67.50 to 5.62 cycles (12.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

GOMP_barrier@plt: 9 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1013
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1024
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1013
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1024
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
hypre_CAlloc: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:916
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1048
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:921
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1050
hypre_Free: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1132
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:900
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:901
memset@plt: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:918
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:923

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 10 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1044
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1045
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1033
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1034
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1033
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1034
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1033
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1034
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1033
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1034
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:902

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:902

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1088 bytes. The binary function is storing 632 bytes.

General properties

nb instructions	373
nb uops	405
loop length	1776
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	34

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	67.50 cycles
front end	67.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	15.10	15.00	49.67	49.67	51.50	15.00	14.90	51.50	51.50	51.50	15.00	49.67
cycles	15.10	15.00	49.67	49.67	51.50	15.00	14.90	51.50	51.50	51.50	15.00	49.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	67.50
Dispatch	51.50
DIV/SQRT	10.00
Overall L1	67.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 67.50 cycles. At this rate:

8% of peak load performance is reached (16.12 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.36 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 67.50 to 51.50 cycles (1.31x speedup).

ASM code

In the binary file, the address of the function is: 4621d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x128,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0xe0(%RDI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xd8(%RDI),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xc0(%RAX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xa0(%RAX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x98(%RAX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x90(%RAX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x148(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd0(%RDI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xc8(%RAX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x88(%RAX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x118(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb8(%RAX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x80(%RAX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RAX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x68(%RAX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x60(%RAX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x58(%RAX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x50(%RAX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x48(%RAX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RAX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RAX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RAX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x40(%RAX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RAX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RAX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RAX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 555090 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 555080 <hypre_NumActiveThreads>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x150(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RSI	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOV -0x110(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf0(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R15,%R10,8),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%RSI),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (,%R10,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RAX,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R9,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R11,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVNE %RAX,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
LEA (%R9,%R15,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R8,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 4623b8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1e8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%R12,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4110a0 <memset@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RBX),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RBX,-0x118(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 4637ae <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x15de>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPQ $0,-0x108(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 463750 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1580>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xf0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x1(%RAX),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDX,-0x100(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JLE 462c0e <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xa3e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,-0x128(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x138(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x128(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x130(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x138(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x110(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 462dc5 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xbf5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x120(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x150(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,(%R8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CMPQ $0x1,(%RBX)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x120(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JLE 462c9a <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xaca>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x120(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x148(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xe8(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%R12	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV -0x8(%R8,%R12,1),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x8(%R9,%R12,1),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDI,0x78(%RAX)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
ADD %RBX,0xb0(%RAX)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R10,%R14,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %RBX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %RAX,(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x38(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 46380d <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x163d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x148(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xa8(%RCX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0x1,(%RDX)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JLE 463845 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1675>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xe0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf0(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,(%RSI,%R9,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 462f7b <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdab>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,(%R8,%R12,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,(%R10,%R12,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV -0x38(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R12,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JLE 462cb7 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xae7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xf8(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA -0x8(%RBX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%RSI,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R9,%RSI,1),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R10,-0x100(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JLE 46383b <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x166b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R12),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R11,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x80(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SAL $0x3,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %RCX,(%R8,%R9,1)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV -0xb8(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x78(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOT %RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R10,(%RSI,%R9,1)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%R11),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x3,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R10,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 462f67 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd97>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 4637c8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x15f8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 462eb0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xce0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4637de <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x160e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RSI,%R10,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x80(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RDX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R9,(%RDI,%RAX,1)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV -0x78(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,(%R8,%RAX,1)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV -0xb0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RSI,%R10,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x80(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RDX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R9,(%RDI,%RAX,1)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV -0x78(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,(%R8,%RAX,1)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
CMP %R10,-0xb8(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JLE 462f67 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd97>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x80(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xb0(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xb8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV (%R12),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf0(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf8(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,-0x100(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JLE 46362d <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x145d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xe0(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xe8(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R13,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R12,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 552440 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CMPQ $0,-0x108(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 463661 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1491>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x140(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R14,-0x118(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 463661 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1491>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x128,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
ADD $0x128,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 552440 <hypre_Free>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x108(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV -0x38(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 4623de <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x20e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%R12,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4110a0 <memset@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 4623de <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x20e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %R11,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x118(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 463768 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1598>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x80(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xb0(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 462eff <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd2f>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0xb0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%R10,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x80(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R9,(%RDI,%RAX,1)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV -0x78(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x2(%R11),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,(%R8,%RAX,1)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	N/A
JMP 462e7f <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcaf>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0xe0(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R8,%R14,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 462d42 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xb72>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 46362d <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x145d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %RDI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 462d42 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xb72>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	par_multi_interp.c:891-1134
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

GOMP_barrier@plt: 9 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1013
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1024
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1013
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1024
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1055
hypre_CAlloc: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:916
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1048
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:921
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1050
hypre_Free: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1132
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:900
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:901
memset@plt: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:918
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:923

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 10 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1044
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1045
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1033
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1034
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1033
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1034
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1033
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1034
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1033
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1034
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:902

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:902

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1088 bytes. The binary function is storing 632 bytes.

General properties

nb instructions	373
nb uops	405
loop length	1776
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	34

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	67.50 cycles
front end	67.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	15.10	15.00	49.67	49.67	51.50	15.00	14.90	51.50	51.50	51.50	15.00	49.67
cycles	15.10	15.00	49.67	49.67	51.50	15.00	14.90	51.50	51.50	51.50	15.00	49.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	67.50
Dispatch	51.50
DIV/SQRT	10.00
Overall L1	67.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 67.50 cycles. At this rate:

8% of peak load performance is reached (16.12 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.36 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4621d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x128,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0xe0(%RDI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xd8(%RDI),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xc0(%RAX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xa0(%RAX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x98(%RAX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x90(%RAX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x148(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd0(%RDI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xc8(%RAX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x88(%RAX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x120(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x118(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0x108(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xb8(%RAX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x80(%RAX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RAX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x68(%RAX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x60(%RAX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x58(%RAX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x50(%RAX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x48(%RAX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RAX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RAX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RAX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x40(%RAX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RAX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RAX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0xe8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RAX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%RAX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 555090 <hypre_GetThreadNum>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,-0x110(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 555080 <hypre_NumActiveThreads>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x150(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RSI	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
MOV -0x110(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf0(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R15,%R10,8),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%RSI),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (,%R10,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RAX,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R9,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R11,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMOVNE %RAX,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
LEA (%R9,%R15,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R8,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,-0x100(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,-0xf8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 4623b8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1e8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%R12,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 4110a0 <memset@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RBX),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,-0x140(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP %RBX,-0x118(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 4637ae <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x15de>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMPQ $0,-0x108(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 463750 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1580>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xf0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x1(%RAX),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDX,-0x100(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JLE 462c0e <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xa3e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8,-0x128(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x130(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x138(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x128(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x130(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x138(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x110(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JNE 462dc5 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xbf5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x120(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x150(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,(%R8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,(%R10)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%R12D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CMPQ $0x1,(%RBX)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV -0x120(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JLE 462c9a <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xaca>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x120(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x148(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xe8(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%R12	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV -0x8(%R8,%R12,1),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x8(%R9,%R12,1),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDI,0x78(%RAX)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
ADD %RBX,0xb0(%RAX)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R10,%R14,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %RBX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %RAX,(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x38(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JNE 46380d <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x163d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x148(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xa8(%RCX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMPQ $0x1,(%RDX)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JLE 463845 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1675>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xe0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf0(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVQ $0,(%RSI,%R9,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 462f7b <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xdab>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,(%R8,%R12,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,(%R10,%R12,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV -0x38(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R12,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JLE 462cb7 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xae7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xf8(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA -0x8(%RBX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%RSI,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R9,%RSI,1),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R10,-0x100(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JLE 46383b <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x166b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb0(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R12),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX,%R11,8),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x80(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SAL $0x3,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %RCX,(%R8,%R9,1)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV -0xb8(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x78(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOT %RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R10,(%RSI,%R9,1)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%R11),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x3,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R10,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JLE 462f67 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd97>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 4637c8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x15f8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 462eb0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xce0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JNE 4637de <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x160e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0xb0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RSI,%R10,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x80(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RDX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R9,(%RDI,%RAX,1)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV -0x78(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
INC %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,(%R8,%RAX,1)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV -0xb0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RSI,%R10,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x80(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RDX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R9,(%RDI,%RAX,1)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV -0x78(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,(%R8,%RAX,1)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
CMP %R10,-0xb8(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JLE 462f67 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd97>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x80(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xb0(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xb8(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV (%R12),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf0(%RBP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xf8(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
DEC %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,-0x100(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JLE 46362d <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x145d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0xe0(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xe8(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R15,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R13,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R12,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 552440 <hypre_Free>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
CMPQ $0,-0x108(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JNE 463661 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1491>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x140(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP %R14,-0x118(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 463661 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1491>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x128,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
ADD $0x128,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 552440 <hypre_Free>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x108(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
TEST %R12,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV -0x38(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 4623de <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x20e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA (,%R12,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0xff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4110a0 <memset@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 4623de <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x20e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %R11,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x118(%RBP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JMP 463768 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1598>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x80(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0xb0(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 462eff <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xd2f>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0xb0(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDX,%R10,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x80(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R9,(%RDI,%RAX,1)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV -0x78(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x2(%R11),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,(%R8,%RAX,1)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	N/A
JMP 462e7f <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcaf>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV -0xe0(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x8,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R8,%R14,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 5523b0 <hypre_CAlloc>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %RAX,(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 462d42 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xb72>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 46362d <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x145d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %RDI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 462d42 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xb72>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass._omp_fn.5–	1.74	0.75
▼Loop 581 - par_multi_interp.c:939-999 - exec–	0.07	0.02
▼Loop 584 - par_multi_interp.c:944-970 - exec–	0.84	0.32
○Loop 585 - par_multi_interp.c:963-970 - exec	0.00	0.00
○Loop 586 - par_multi_interp.c:951-958 - exec	0.00	0.00
▼Loop 582 - par_multi_interp.c:976-999 - exec–	0.00	0.01
○Loop 583 - par_multi_interp.c:983-999 - exec	0.00	0.00
▼Loop 573 - par_multi_interp.c:1072-1125 - exec–	0.05	0.02
▼Loop 576 - par_multi_interp.c:1075-1099 - exec–	0.74	0.28
○Loop 578 - par_multi_interp.c:1082-1088 - exec	0.00	0.01
○Loop 577 - par_multi_interp.c:1093-1099 - exec	0.00	0.00
▼Loop 574 - par_multi_interp.c:1104-1125 - exec–	0.00	0.01
○Loop 575 - par_multi_interp.c:1111-1125 - exec	0.00	0.00
○Loop 579 - par_multi_interp.c:1030-1034 - exec	0.04	0.02
○Loop 580 - par_multi_interp.c:1017-1020 - exec	0.00	0.00

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