OV - exec - Function hypre_BoomerAMGCoarsenPMIS._omp

	Function: hypre_BoomerAMGCoarsenPMIS._omp_fn.4	Module: exec	Source: par_coarsen.c:2327-2334	Coverage (incl. loops): 0.05% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2327 - 2334

--------------------------------------------------------------------------------

2327: #pragma omp parallel for private(ig, i) HYPRE_SMP_SCHEDULE

2328: #endif

2329:         for (ig = 0; ig < graph_size; ig++)

2330:         {

2331:            i = graph_array[ig];

2332:            if (measure_array[i] > 1)

2333:            {

2334:               CF_marker[i] = 1;

0x42df60 PUSH	%RBP

0x42df61 MOV	%RSP,%RBP

0x42df64 PUSH	%R12

0x42df66 MOV	%RDI,%R12

0x42df69 PUSH	%RBX

0x42df6a CALL	4110b0 <omp_get_num_threads@plt>

0x42df6f MOV	%EAX,%EBX

0x42df71 CALL	4111f0 <omp_get_thread_num@plt>

0x42df76 MOVSXD	%EAX,%RCX

0x42df79 MOV	0x18(%R12),%RAX

0x42df7e MOVSXD	%EBX,%RSI

0x42df81 MOV	(%RAX),%RAX

0x42df84 CQTO

0x42df86 IDIV	%RSI

0x42df89 CMP	%RDX,%RCX

0x42df8c JL	42e188

0x42df92 IMUL	%RAX,%RCX

0x42df96 ADD	%RCX,%RDX

0x42df99 ADD	%RDX,%RAX

0x42df9c CMP	%RAX,%RDX

0x42df9f JGE	42e180

0x42dfa5 MOV	0x10(%R12),%RDI

0x42dfaa MOV	0x8(%R12),%R8

0x42dfaf LEA	(%RDI,%RAX,8),%R10

0x42dfb3 LEA	(%RDI,%RDX,8),%RDX

0x42dfb7 MOV	%R10,%R11

0x42dfba SUB	%RDX,%R11

0x42dfbd SUB	$0x8,%R11

0x42dfc1 SHR	$0x3,%R11

0x42dfc5 INC	%R11

0x42dfc8 MOV	(%R12),%R9

0x42dfcc VMOVSD	0x12c744(%RIP),%XMM0

0x42dfd4 AND	$0x7,%R11D

0x42dfd8 JE	42e0d0

0x42dfde CMP	$0x1,%R11

0x42dfe2 JE	42e0ac

0x42dfe8 CMP	$0x2,%R11

0x42dfec JE	42e091

0x42dff2 CMP	$0x3,%R11

0x42dff6 JE	42e076

0x42dff8 CMP	$0x4,%R11

0x42dffc JE	42e05b

0x42dffe CMP	$0x5,%R11

0x42e002 JE	42e040

0x42e004 CMP	$0x6,%R11

0x42e008 JE	42e025

0x42e00a MOV	(%RDX),%R12

0x42e00d SAL	$0x3,%R12

0x42e011 VCOMISD	(%R8,%R12,1),%XMM0

0x42e017 JAE	42e021

0x42e019 MOVQ	$0x1,(%R9,%R12,1)

0x42e021 ADD	$0x8,%RDX

0x42e025 MOV	(%RDX),%RBX

0x42e028 SAL	$0x3,%RBX

0x42e02c VCOMISD	(%R8,%RBX,1),%XMM0

0x42e032 JAE	42e03c

0x42e034 MOVQ	$0x1,(%R9,%RBX,1)

0x42e03c ADD	$0x8,%RDX

0x42e040 MOV	(%RDX),%RCX

0x42e043 SAL	$0x3,%RCX

0x42e047 VCOMISD	(%R8,%RCX,1),%XMM0

0x42e04d JAE	42e057

0x42e04f MOVQ	$0x1,(%R9,%RCX,1)

0x42e057 ADD	$0x8,%RDX

0x42e05b MOV	(%RDX),%RSI

0x42e05e SAL	$0x3,%RSI

0x42e062 VCOMISD	(%R8,%RSI,1),%XMM0

0x42e068 JAE	42e072

0x42e06a MOVQ	$0x1,(%R9,%RSI,1)

0x42e072 ADD	$0x8,%RDX

0x42e076 MOV	(%RDX),%RAX

0x42e079 SAL	$0x3,%RAX

0x42e07d VCOMISD	(%R8,%RAX,1),%XMM0

0x42e083 JAE	42e08d

0x42e085 MOVQ	$0x1,(%R9,%RAX,1)

0x42e08d ADD	$0x8,%RDX

0x42e091 MOV	(%RDX),%RDI

0x42e094 SAL	$0x3,%RDI

0x42e098 VCOMISD	(%R8,%RDI,1),%XMM0

0x42e09e JAE	42e0a8

0x42e0a0 MOVQ	$0x1,(%R9,%RDI,1)

0x42e0a8 ADD	$0x8,%RDX

0x42e0ac MOV	(%RDX),%R11

0x42e0af SAL	$0x3,%R11

0x42e0b3 VCOMISD	(%R8,%R11,1),%XMM0

0x42e0b9 JAE	42e0c3

0x42e0bb MOVQ	$0x1,(%R9,%R11,1)

0x42e0c3 ADD	$0x8,%RDX

0x42e0c7 CMP	%RDX,%R10

0x42e0ca JE	42e180

(95) 0x42e0d0 MOV	(%RDX),%R12

(95) 0x42e0d3 VCOMISD	(%R8,%R12,8),%XMM0

(95) 0x42e0d9 JAE	42e0e3

(95) 0x42e0db MOVQ	$0x1,(%R9,%R12,8)

(95) 0x42e0e3 LEA	0x8(%RDX),%RBX

(95) 0x42e0e7 MOV	0x8(%RDX),%RDX

(95) 0x42e0eb VCOMISD	(%R8,%RDX,8),%XMM0

(95) 0x42e0f1 JAE	42e0fb

(95) 0x42e0f3 MOVQ	$0x1,(%R9,%RDX,8)

(95) 0x42e0fb MOV	0x8(%RBX),%RCX

(95) 0x42e0ff VCOMISD	(%R8,%RCX,8),%XMM0

(95) 0x42e105 JAE	42e10f

(95) 0x42e107 MOVQ	$0x1,(%R9,%RCX,8)

(95) 0x42e10f MOV	0x10(%RBX),%RSI

(95) 0x42e113 VCOMISD	(%R8,%RSI,8),%XMM0

(95) 0x42e119 JAE	42e123

(95) 0x42e11b MOVQ	$0x1,(%R9,%RSI,8)

(95) 0x42e123 MOV	0x18(%RBX),%RAX

(95) 0x42e127 VCOMISD	(%R8,%RAX,8),%XMM0

(95) 0x42e12d JAE	42e137

(95) 0x42e12f MOVQ	$0x1,(%R9,%RAX,8)

(95) 0x42e137 MOV	0x20(%RBX),%RDI

(95) 0x42e13b VCOMISD	(%R8,%RDI,8),%XMM0

(95) 0x42e141 JAE	42e14b

(95) 0x42e143 MOVQ	$0x1,(%R9,%RDI,8)

(95) 0x42e14b MOV	0x28(%RBX),%R11

(95) 0x42e14f VCOMISD	(%R8,%R11,8),%XMM0

(95) 0x42e155 JAE	42e15f

(95) 0x42e157 MOVQ	$0x1,(%R9,%R11,8)

(95) 0x42e15f MOV	0x30(%RBX),%R12

(95) 0x42e163 VCOMISD	(%R8,%R12,8),%XMM0

(95) 0x42e169 JAE	42e173

(95) 0x42e16b MOVQ	$0x1,(%R9,%R12,8)

(95) 0x42e173 LEA	0x38(%RBX),%RDX

(95) 0x42e177 CMP	%RDX,%R10

(95) 0x42e17a JNE	42e0d0

0x42e180 POP	%RBX

0x42e181 POP	%R12

0x42e183 POP	%RBP

0x42e184 RET

0x42e185 NOPL	(%RAX)

0x42e188 INC	%RAX

0x42e18b XOR	%EDX,%EDX

0x42e18d JMP	42df92

0x42e192 NOPW	%CS:(%RAX,%RAX,1)

0x42e19d NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○97.83	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.17	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	par_coarsen.c:2327-2334
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2327-2334.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.83 to 12.50 cycles (1.51x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 18.83 to 5.00 cycles (3.77x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2327
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2327

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2327
VCOMISD: 7 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2327

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 160 bytes (20 double precision FP elements). The binary function is storing 56 bytes (7 double precision FP elements).

General properties

nb instructions	100
nb uops	113
loop length	400
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.83 cycles
front end	18.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	17.00	6.40	8.00	8.00	6.00	6.40	17.00	6.00	6.00	6.00	6.20	8.00
cycles	17.00	7.27	8.00	8.00	6.00	6.40	17.00	6.00	6.00	6.00	6.20	8.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	18.83
Dispatch	17.00
DIV/SQRT	10.00
Overall L1	18.83

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.83 cycles. At this rate:

4% of peak load performance is reached (8.50 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.97 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 18.83 to 17.00 cycles (1.11x speedup).

ASM code

In the binary file, the address of the function is: 42df60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4110b0 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4111f0 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV 0x18(%R12),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %EBX,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV (%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RSI	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 42e188 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x228>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 42e180 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x220>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x10(%R12),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R12),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDI,%RAX,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RDI,%RDX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RDX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB $0x8,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%R11	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x12c744(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
AND $0x7,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 42e0d0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x170>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 42e0ac <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x14c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 42e091 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x131>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 42e076 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x116>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 42e05b <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xfb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 42e040 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xe0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 42e025 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xc5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%RDX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%R12	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VCOMISD (%R8,%R12,1),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42e021 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xc1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R9,%R12,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VCOMISD (%R8,%RBX,1),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42e03c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xdc>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R9,%RBX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VCOMISD (%R8,%RCX,1),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42e057 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xf7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R9,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VCOMISD (%R8,%RSI,1),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42e072 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x112>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R9,%RSI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VCOMISD (%R8,%RAX,1),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42e08d <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x12d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R9,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VCOMISD (%R8,%RDI,1),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42e0a8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x148>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R9,%RDI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%R11	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VCOMISD (%R8,%R11,1),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42e0c3 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x163>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R9,%R11,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 42e180 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x220>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 42df92 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x32>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	par_coarsen.c:2327-2334
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2327-2334.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2327
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2327

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2327
VCOMISD: 7 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2332

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-927-0874/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2327

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

General properties

nb instructions	100
nb uops	113
loop length	400
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.83 cycles
front end	18.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	17.00	6.40	8.00	8.00	6.00	6.40	17.00	6.00	6.00	6.00	6.20	8.00
cycles	17.00	7.27	8.00	8.00	6.00	6.40	17.00	6.00	6.00	6.00	6.20	8.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

10.00

Cycles summary

Front-end	18.83
Dispatch	17.00
DIV/SQRT	10.00
Overall L1	18.83

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.83 cycles. At this rate:

4% of peak load performance is reached (8.50 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.97 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 42df60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
CALL 4110b0 <omp_get_num_threads@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4111f0 <omp_get_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOVSXD %EAX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV 0x18(%R12),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %EBX,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV (%RAX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CQTO	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (12.5%)
IDIV %RSI	5	0	3	0	0	0	0	0	0	0	0	0	0	11-16	10	scal (12.5%)
CMP %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JL 42e188 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x228>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JGE 42e180 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x220>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x10(%R12),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R12),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDI,%RAX,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RDI,%RDX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %RDX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB $0x8,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%R11	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
INC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x12c744(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
AND $0x7,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
JE 42e0d0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x170>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 42e0ac <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x14c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 42e091 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x131>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 42e076 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x116>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 42e05b <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xfb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 42e040 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xe0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 42e025 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xc5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV (%RDX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%R12	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VCOMISD (%R8,%R12,1),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42e021 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xc1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R9,%R12,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VCOMISD (%R8,%RBX,1),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42e03c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xdc>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R9,%RBX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VCOMISD (%R8,%RCX,1),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42e057 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xf7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R9,%RCX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VCOMISD (%R8,%RSI,1),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42e072 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x112>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R9,%RSI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VCOMISD (%R8,%RAX,1),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42e08d <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x12d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R9,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VCOMISD (%R8,%RDI,1),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42e0a8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x148>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R9,%RDI,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%R11	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VCOMISD (%R8,%R11,1),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (12.5%)
JAE 42e0c3 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x163>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVQ $0x1,(%R9,%R11,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x8,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 42e180 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x220>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 42df92 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x32>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCoarsenPMIS._omp_fn.4–	0.05	0.02
○Loop 95 - par_coarsen.c:2332-2334 - exec	0.05	0.02

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