OV - attention-avx512 - Loop 32

0x8320 MOV	0x40(%RSP),%R10D

0x8325 MOV	0x30(%RSP),%RCX

0x832a INC	%R10D

0x832d ADD	%RCX,%R9

0x8330 CMP	%ECX,%R10D

0x8333 JE	82f0

0x8335 MOV	0x28(%RSP),%RAX

0x833a CMP	$0x1,%R12

0x833e MOV	%R10D,%R14D

0x8341 MOV	%R10D,0x40(%RSP)

0x8346 SETNE	%DL

0x8349 MOV	%RAX,%R8

0x834c SHR	$0x20,%R8

0x8350 MOV	%R10D,%R8D

0x8353 SETNE	%R11B

0x8357 IMUL	%ECX,%R8D

0x835b IMUL	%R12D,%R14D

0x835f ADD	%EAX,%R8D

0x8362 SETB	%R8B

0x8366 OR	%DL,%R11B

0x8369 OR	%R8B,%R11B

0x836c XOR	%R8D,%R8D

0x836f MOV	%R11B,0x240(%RSP)

0x8377 JMP	83a9

  (33) 0x8380 MOV	0x2b8(%RSP),%RCX

  (33) 0x8388 MOV	0x238(%RSP),%R13

  (33) 0x8390 VCVTSD2SS	%XMM0,%XMM0,%XMM0

  (33) 0x8394 LEA	(%R14,%R8,1),%EDX

  (33) 0x8398 INC	%R8

  (33) 0x839b VMOVSS	%XMM0,(%RCX,%RDX,4)

  (33) 0x83a0 CMP	%R15,%R8

  (33) 0x83a3 JE	8320

  (33) 0x83a9 CMPL	$0x4,0x38(%RSP)

  (33) 0x83ae VXORPS	%XMM0,%XMM0,%XMM0

  (33) 0x83b2 JB	83c7

  (33) 0x83b4 MOV	%R8D,%EDX

  (33) 0x83b7 ADD	0x28(%RSP),%EDX

  (33) 0x83bb SETB	%DL

  (33) 0x83be OR	0x240(%RSP),%DL

  (33) 0x83c5 JE	8420

  (33) 0x83c7 MOV	0xb0(%RSP),%R10

  (33) 0x83cf MOV	0x38(%RSP),%RAX

  (33) 0x83d4 MOV	0x80(%RSP),%R11

  (33) 0x83dc XOR	%R13D,%R13D

  (33) 0x83df MOV	%R12,%RDX

  (33) 0x83e2 IMUL	%R13,%RDX

  (33) 0x83e6 ADD	%R8,%RDX

  (33) 0x83e9 NOPL	(%RAX)

    (30) 0x83f0 LEA	(%R9,%R13,1),%ECX

    (30) 0x83f4 INC	%R13

    (30) 0x83f7 VMOVSS	(%R11,%RCX,4),%XMM1

    (30) 0x83fd MOV	%EDX,%ECX

    (30) 0x83ff VMOVSS	(%R10,%RCX,4),%XMM2

    (30) 0x8405 ADD	%R12,%RDX

    (30) 0x8408 VCVTSS2SD	%XMM1,%XMM1,%XMM1

    (30) 0x840c VCVTSS2SD	%XMM2,%XMM2,%XMM2

    (30) 0x8410 VFMADD231SD	%XMM2,%XMM1,%XMM0

    (30) 0x8415 CMP	%R13,%RAX

    (30) 0x8418 JNE	83f0

  (33) 0x841a JMP	8380

  (33) 0x8420 CMPL	$0x20,0x38(%RSP)

  (33) 0x8425 JAE	843e

  (33) 0x8427 MOV	0xb0(%RSP),%R10

  (33) 0x842f MOV	0x80(%RSP),%R11

  (33) 0x8437 XOR	%EDX,%EDX

  (33) 0x8439 JMP	853e

  (33) 0x843e MOV	0xb0(%RSP),%RCX

  (33) 0x8446 MOV	0x80(%RSP),%RAX

  (33) 0x844e VXORPS	%XMM0,%XMM0,%XMM0

  (33) 0x8452 VXORPS	%XMM1,%XMM1,%XMM1

  (33) 0x8456 VXORPS	%XMM2,%XMM2,%XMM2

  (33) 0x845a VPXOR	%XMM3,%XMM3,%XMM3

  (33) 0x845e XOR	%R13D,%R13D

  (33) 0x8461 NOPW	%CS:(%RAX,%RAX,1)

    (34) 0x8470 LEA	(%R9,%R13,1),%EDX

    (34) 0x8474 VCVTPS2PD	(%RAX,%RDX,4),%ZMM4

    (34) 0x847b VCVTPS2PD	0x20(%RAX,%RDX,4),%ZMM5

    (34) 0x8483 VCVTPS2PD	0x40(%RAX,%RDX,4),%ZMM6

    (34) 0x848b VCVTPS2PD	0x60(%RAX,%RDX,4),%ZMM7

    (34) 0x8493 LEA	(%R8,%R13,1),%EDX

    (34) 0x8497 ADD	$0x20,%R13

    (34) 0x849b VCVTPS2PD	(%RCX,%RDX,4),%ZMM8

    (34) 0x84a2 VCVTPS2PD	0x20(%RCX,%RDX,4),%ZMM9

    (34) 0x84aa VFMADD231PD	%ZMM8,%ZMM4,%ZMM0

    (34) 0x84b0 VCVTPS2PD	0x40(%RCX,%RDX,4),%ZMM8

    (34) 0x84b8 VFMADD231PD	%ZMM9,%ZMM5,%ZMM1

    (34) 0x84be VCVTPS2PD	0x60(%RCX,%RDX,4),%ZMM5

    (34) 0x84c6 VFMADD231PD	%ZMM8,%ZMM6,%ZMM2

    (34) 0x84cc VFMADD231PD	%ZMM5,%ZMM7,%ZMM3

    (34) 0x84d2 CMP	%R13,%RSI

    (34) 0x84d5 JNE	8470

  (33) 0x84d7 VADDPD	%ZMM0,%ZMM1,%ZMM0

  (33) 0x84dd VADDPD	%ZMM2,%ZMM3,%ZMM2

  (33) 0x84e3 MOV	0x100(%RSP),%RAX

  (33) 0x84eb VADDPD	%ZMM0,%ZMM2,%ZMM0

  (33) 0x84f1 VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

  (33) 0x84f8 VADDPD	%ZMM1,%ZMM0,%ZMM0

  (33) 0x84fe VEXTRACTF128	$0x1,%YMM0,%XMM1

  (33) 0x8504 VADDPD	%XMM1,%XMM0,%XMM0

  (33) 0x8508 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (33) 0x850d VADDSD	%XMM1,%XMM0,%XMM0

  (33) 0x8511 TEST	%RAX,%RAX

  (33) 0x8514 JE	8380

  (33) 0x851a MOV	%RSI,%RDX

  (33) 0x851d MOV	%RSI,%R13

  (33) 0x8520 MOV	0xb0(%RSP),%R10

  (33) 0x8528 MOV	0x80(%RSP),%R11

  (33) 0x8530 CMP	$0x4,%EAX

  (33) 0x8533 MOV	0x38(%RSP),%RAX

  (33) 0x8538 JB	83df

  (33) 0x853e VMOVQ	%XMM0,%XMM0

  (33) 0x8542 NOPW	%CS:(%RAX,%RAX,1)

    (35) 0x8550 LEA	(%R9,%RDX,1),%R13D

    (35) 0x8554 VCVTPS2PD	(%R11,%R13,4),%YMM1

    (35) 0x855a LEA	(%R8,%RDX,1),%R13D

    (35) 0x855e ADD	$0x4,%RDX

    (35) 0x8562 VCVTPS2PD	(%R10,%R13,4),%YMM2

    (35) 0x8568 VFMADD231PD	%YMM2,%YMM1,%YMM0

    (35) 0x856d CMP	%RDX,%RDI

    (35) 0x8570 JNE	8550

  (33) 0x8572 VEXTRACTF128	$0x1,%YMM0,%XMM1

  (33) 0x8578 CMPQ	$0,0x1c0(%RSP)

  (33) 0x8581 MOV	0x38(%RSP),%RAX

  (33) 0x8586 MOV	%RDI,%R13

  (33) 0x8589 VADDPD	%XMM1,%XMM0,%XMM0

  (33) 0x858d VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (33) 0x8592 VADDSD	%XMM1,%XMM0,%XMM0

  (33) 0x8596 JNE	83df

  (33) 0x859c JMP	8380

/home/eoseret/llm-attention/attention.cpp: 26 - 306

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

306:    for (size_t r = 0; r < rept; r++)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	14.22
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:26-26,attention.cpp:306-306
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.21
Front-end cycles	3.00
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	2.50
P6 cycles	1.25
P7 cycles	1.25
P8 cycles	1.25
P9 cycles	1.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	3.00
Nb stores	2.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.33
Bytes prefetched	0.00
Bytes loaded	20.00
Bytes stored	5.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.33
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	9.38
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.33

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	14.22
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:26-26,attention.cpp:306-306
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.21
Front-end cycles	3.00
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	2.50
P6 cycles	1.25
P7 cycles	1.25
P8 cycles	1.25
P9 cycles	1.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	3.00
Nb stores	2.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.33
Bytes prefetched	0.00
Bytes loaded	20.00
Bytes stored	5.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.33
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	9.38
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.33

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:26-306
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:26-33,306.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:26,306.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.21 cycles (14.22x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 20 bytes. The binary loop is storing 5 bytes.

General properties

nb instructions	24
nb uops	24
loop length	89
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.50	2.50	2.50	2.50	2.50	2.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.50	2.50	2.50	2.50	2.50	2.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.00
Dispatch	2.50
Overall L1	3.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	9%
store	6%
mul	6%
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

2% of peak load performance is reached (6.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.00 to 2.50 cycles (1.20x speedup).

ASM code

In the binary file, the address of the loop is: 8335

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV 0x40(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x30(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
INC %R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD %RCX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMP %ECX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JE 82f0 <main+0x38a0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
MOV 0x28(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP $0x1,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %R10D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R10D,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SETNE %DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x20,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
MOV %R10D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SETNE %R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL %ECX,%R8D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %R12D,%R14D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %EAX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SETB %R8B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
OR %DL,%R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
OR %R8B,%R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11B,0x240(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	N/A
JMP 83a9 <main+0x3959>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention.cpp:26-306
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:26-33,306.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:26,306.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.21 cycles (14.22x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 20 bytes. The binary loop is storing 5 bytes.

General properties

nb instructions	24
nb uops	24
loop length	89
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.50	2.50	2.50	2.50	2.50	2.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.50	2.50	2.50	2.50	2.50	2.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.00
Dispatch	2.50
Overall L1	3.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	9%
store	6%
mul	6%
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

2% of peak load performance is reached (6.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.00 to 2.50 cycles (1.20x speedup).

ASM code

In the binary file, the address of the loop is: 8335

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV 0x40(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x30(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
INC %R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD %RCX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMP %ECX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JE 82f0 <main+0x38a0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
MOV 0x28(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP $0x1,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %R10D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R10D,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SETNE %DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x20,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
MOV %R10D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SETNE %R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL %ECX,%R8D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %R12D,%R14D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %EAX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SETB %R8B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
OR %DL,%R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
OR %R8B,%R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11B,0x240(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	N/A
JMP 83a9 <main+0x3959>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code