OV - attention-avx512 - Loop 59

0x6480 MOV	0x1c0(%RSP),%EDX

0x6487 ADD	%R12,%R10

0x648a INC	%EDX

0x648c CMP	%EDX,0x30(%RSP)

0x6490 JE	6450

0x6492 CMP	$0x1,%R12

0x6496 MOV	%RCX,%RAX

0x6499 MOV	%EDX,0x1c0(%RSP)

0x64a0 SETNE	%SIL

0x64a4 SHR	$0x20,%RAX

0x64a8 MOV	%EDX,%EAX

0x64aa SETNE	%R14B

0x64ae IMUL	%R12D,%EAX

0x64b2 MOV	%EAX,%R9D

0x64b5 ADD	%ECX,%R9D

0x64b8 SETB	%R9B

0x64bc OR	%SIL,%R14B

0x64bf OR	%R9B,%R14B

0x64c2 XOR	%R9D,%R9D

0x64c5 JMP	64ed

  (60) 0x64d0 MOV	0xb0(%RSP),%RDX

  (60) 0x64d8 VCVTSD2SS	%XMM0,%XMM0,%XMM0

  (60) 0x64dc LEA	(%RAX,%R9,1),%ESI

  (60) 0x64e0 INC	%R9

  (60) 0x64e3 VMOVSS	%XMM0,(%RDX,%RSI,4)

  (60) 0x64e8 CMP	%R15,%R9

  (60) 0x64eb JE	6480

  (60) 0x64ed VXORPS	%XMM0,%XMM0,%XMM0

  (60) 0x64f1 CMP	$0x4,%R15D

  (60) 0x64f5 JB	6505

  (60) 0x64f7 MOV	%R9D,%ESI

  (60) 0x64fa ADD	%ECX,%ESI

  (60) 0x64fc SETB	%SIL

  (60) 0x6500 OR	%R14B,%SIL

  (60) 0x6503 JE	6550

  (60) 0x6505 MOV	0x98(%RSP),%R11

  (60) 0x650d XOR	%R13D,%R13D

  (60) 0x6510 MOV	%R12,%RSI

  (60) 0x6513 IMUL	%R13,%RSI

  (60) 0x6517 ADD	%R9,%RSI

  (60) 0x651a NOPW	(%RAX,%RAX,1)

    (57) 0x6520 LEA	(%R10,%R13,1),%EDX

    (57) 0x6524 INC	%R13

    (57) 0x6527 VMOVSS	(%RBX,%RDX,4),%XMM1

    (57) 0x652c MOV	%ESI,%EDX

    (57) 0x652e VMOVSS	(%R11,%RDX,4),%XMM2

    (57) 0x6534 ADD	%R12,%RSI

    (57) 0x6537 VCVTSS2SD	%XMM1,%XMM1,%XMM1

    (57) 0x653b VCVTSS2SD	%XMM2,%XMM2,%XMM2

    (57) 0x653f VFMADD231SD	%XMM2,%XMM1,%XMM0

    (57) 0x6544 CMP	%R13,%R15

    (57) 0x6547 JNE	6520

  (60) 0x6549 JMP	64d0

  (60) 0x6550 CMP	$0x20,%R15D

  (60) 0x6554 JAE	6565

  (60) 0x6556 MOV	0x98(%RSP),%R11

  (60) 0x655e XOR	%ESI,%ESI

  (60) 0x6560 JMP	6641

  (60) 0x6565 MOV	0x98(%RSP),%RDX

  (60) 0x656d VXORPS	%XMM0,%XMM0,%XMM0

  (60) 0x6571 VXORPS	%XMM1,%XMM1,%XMM1

  (60) 0x6575 VXORPS	%XMM2,%XMM2,%XMM2

  (60) 0x6579 VPXOR	%XMM3,%XMM3,%XMM3

  (60) 0x657d XOR	%R13D,%R13D

    (61) 0x6580 LEA	(%R10,%R13,1),%ESI

    (61) 0x6584 VCVTPS2PD	(%RBX,%RSI,4),%ZMM4

    (61) 0x658b VCVTPS2PD	0x20(%RBX,%RSI,4),%ZMM5

    (61) 0x6593 VCVTPS2PD	0x40(%RBX,%RSI,4),%ZMM6

    (61) 0x659b VCVTPS2PD	0x60(%RBX,%RSI,4),%ZMM7

    (61) 0x65a3 LEA	(%R9,%R13,1),%ESI

    (61) 0x65a7 ADD	$0x20,%R13

    (61) 0x65ab VCVTPS2PD	(%RDX,%RSI,4),%ZMM8

    (61) 0x65b2 VCVTPS2PD	0x20(%RDX,%RSI,4),%ZMM9

    (61) 0x65ba VFMADD231PD	%ZMM8,%ZMM4,%ZMM0

    (61) 0x65c0 VCVTPS2PD	0x40(%RDX,%RSI,4),%ZMM8

    (61) 0x65c8 VFMADD231PD	%ZMM9,%ZMM5,%ZMM1

    (61) 0x65ce VCVTPS2PD	0x60(%RDX,%RSI,4),%ZMM5

    (61) 0x65d6 VFMADD231PD	%ZMM8,%ZMM6,%ZMM2

    (61) 0x65dc VFMADD231PD	%ZMM5,%ZMM7,%ZMM3

    (61) 0x65e2 CMP	%R13,%RDI

    (61) 0x65e5 JNE	6580

  (60) 0x65e7 VADDPD	%ZMM0,%ZMM1,%ZMM0

  (60) 0x65ed VADDPD	%ZMM2,%ZMM3,%ZMM2

  (60) 0x65f3 MOV	0x240(%RSP),%RDX

  (60) 0x65fb VADDPD	%ZMM0,%ZMM2,%ZMM0

  (60) 0x6601 VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

  (60) 0x6608 VADDPD	%ZMM1,%ZMM0,%ZMM0

  (60) 0x660e VEXTRACTF128	$0x1,%YMM0,%XMM1

  (60) 0x6614 VADDPD	%XMM1,%XMM0,%XMM0

  (60) 0x6618 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (60) 0x661d VADDSD	%XMM1,%XMM0,%XMM0

  (60) 0x6621 TEST	%RDX,%RDX

  (60) 0x6624 JE	64d0

  (60) 0x662a MOV	0x98(%RSP),%R11

  (60) 0x6632 MOV	%RDI,%RSI

  (60) 0x6635 MOV	%RDI,%R13

  (60) 0x6638 CMP	$0x4,%EDX

  (60) 0x663b JB	6510

  (60) 0x6641 VMOVQ	%XMM0,%XMM0

  (60) 0x6645 NOPW	%CS:(%RAX,%RAX,1)

    (62) 0x6650 LEA	(%R10,%RSI,1),%R13D

    (62) 0x6654 VCVTPS2PD	(%RBX,%R13,4),%YMM1

    (62) 0x665a LEA	(%R9,%RSI,1),%R13D

    (62) 0x665e ADD	$0x4,%RSI

    (62) 0x6662 VCVTPS2PD	(%R11,%R13,4),%YMM2

    (62) 0x6668 VFMADD231PD	%YMM2,%YMM1,%YMM0

    (62) 0x666d CMP	%RSI,%R8

    (62) 0x6670 JNE	6650

  (60) 0x6672 VEXTRACTF128	$0x1,%YMM0,%XMM1

  (60) 0x6678 CMPQ	$0,0x28(%RSP)

  (60) 0x667e MOV	%R8,%R13

  (60) 0x6681 VADDPD	%XMM1,%XMM0,%XMM0

  (60) 0x6685 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (60) 0x668a VADDSD	%XMM1,%XMM0,%XMM0

  (60) 0x668e JNE	6510

  (60) 0x6694 JMP	64d0

/home/eoseret/llm-attention/attention.cpp: 26 - 215

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

215:    for (size_t r = 0; r < rept; r++)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.91
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:26-26,attention.cpp:215-215
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	0.18
Front-end cycles	2.50
P0 cycles	2.33
P1 cycles	2.33
P2 cycles	2.33
P3 cycles	2.33
P4 cycles	2.33
P5 cycles	2.33
P6 cycles	0.75
P7 cycles	0.75
P8 cycles	0.75
P9 cycles	0.75
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	20.00
Nb loads	2.00
Nb stores	1.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.80
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.75
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	9.38
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.91
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:26-26,attention.cpp:215-215
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	0.18
Front-end cycles	2.50
P0 cycles	2.33
P1 cycles	2.33
P2 cycles	2.33
P3 cycles	2.33
P4 cycles	2.33
P5 cycles	2.33
P6 cycles	0.75
P7 cycles	0.75
P8 cycles	0.75
P9 cycles	0.75
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	20.00
Nb loads	2.00
Nb stores	1.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.80
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.75
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	9.38
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:26-215
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:26-33,215.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:26,215.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.50 to 0.18 cycles (13.91x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	20
nb uops	20
loop length	71
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.50 cycles
front end	2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.33	2.33	2.33	2.33	2.33	2.33	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.33	2.33	2.33	2.33	2.33	2.33	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.50
Dispatch	2.33
Overall L1	2.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	6%
store	6%
mul	6%
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

1% of peak load performance is reached (3.20 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.60 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.50 to 2.33 cycles (1.07x speedup).

ASM code

In the binary file, the address of the loop is: 6492

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV 0x1c0(%RSP),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
ADD %R12,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
INC %EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %EDX,0x30(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JE 6450 <main+0x1a00>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
CMP $0x1,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %EDX,0x1c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SETNE %SIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SHR $0x20,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SETNE %R14B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL %R12D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %ECX,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SETB %R9B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
OR %SIL,%R14B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
OR %R9B,%R14B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 64ed <main+0x1a9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention.cpp:26-215
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:26-33,215.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:26,215.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.50 to 0.18 cycles (13.91x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	20
nb uops	20
loop length	71
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.50 cycles
front end	2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.33	2.33	2.33	2.33	2.33	2.33	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.33	2.33	2.33	2.33	2.33	2.33	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.50
Dispatch	2.33
Overall L1	2.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	6%
store	6%
mul	6%
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

1% of peak load performance is reached (3.20 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.60 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.50 to 2.33 cycles (1.07x speedup).

ASM code

In the binary file, the address of the loop is: 6492

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV 0x1c0(%RSP),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
ADD %R12,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
INC %EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %EDX,0x30(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JE 6450 <main+0x1a00>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
CMP $0x1,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %EDX,0x1c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SETNE %SIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SHR $0x20,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SETNE %R14B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL %R12D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %ECX,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SETB %R9B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
OR %SIL,%R14B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
OR %R9B,%R14B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 64ed <main+0x1a9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code