OV - attention-avx512 - Loop 65

0x4fe0 MOV	0x30(%RSP),%EDX

0x4fe4 ADD	%R12,%R10

0x4fe7 INC	%EDX

0x4fe9 CMP	%EDX,0x38(%RSP)

0x4fed JE	4fb0

0x4fef CMP	$0x1,%R12

0x4ff3 MOV	%RCX,%RAX

0x4ff6 MOV	%EDX,%R9D

0x4ff9 MOV	%EDX,0x30(%RSP)

0x4ffd SETNE	%DIL

0x5001 SHR	$0x20,%RAX

0x5005 SETNE	%AL

0x5008 IMUL	%R12D,%R9D

0x500c MOV	%R9D,%R14D

0x500f ADD	%ECX,%R14D

0x5012 SETB	%R14B

0x5016 OR	%DIL,%AL

0x5019 XOR	%EDI,%EDI

0x501b OR	%R14B,%AL

0x501e JMP	503e

  (66) 0x5020 MOV	0xa8(%RSP),%RDX

  (66) 0x5028 VCVTSD2SS	%XMM0,%XMM0,%XMM0

  (66) 0x502c LEA	(%R9,%RDI,1),%R14D

  (66) 0x5030 INC	%RDI

  (66) 0x5033 VMOVSS	%XMM0,(%RDX,%R14,4)

  (66) 0x5039 CMP	%R15,%RDI

  (66) 0x503c JE	4fe0

  (66) 0x503e VXORPS	%XMM0,%XMM0,%XMM0

  (66) 0x5042 CMP	$0x4,%R15D

  (66) 0x5046 JB	5057

  (66) 0x5048 MOV	%EDI,%R14D

  (66) 0x504b ADD	%ECX,%R14D

  (66) 0x504e SETB	%R14B

  (66) 0x5052 OR	%AL,%R14B

  (66) 0x5055 JE	50a0

  (66) 0x5057 MOV	0x78(%RSP),%R11

  (66) 0x505c XOR	%R14D,%R14D

  (66) 0x505f MOV	%R12,%R13

  (66) 0x5062 IMUL	%R14,%R13

  (66) 0x5066 ADD	%RDI,%R13

  (66) 0x5069 NOPL	(%RAX)

    (63) 0x5070 LEA	(%R10,%R14,1),%EDX

    (63) 0x5074 INC	%R14

    (63) 0x5077 VMOVSS	(%RBX,%RDX,4),%XMM1

    (63) 0x507c MOV	%R13D,%EDX

    (63) 0x507f VMOVSS	(%R11,%RDX,4),%XMM2

    (63) 0x5085 ADD	%R12,%R13

    (63) 0x5088 VCVTSS2SD	%XMM1,%XMM1,%XMM1

    (63) 0x508c VCVTSS2SD	%XMM2,%XMM2,%XMM2

    (63) 0x5090 VFMADD231SD	%XMM2,%XMM1,%XMM0

    (63) 0x5095 CMP	%R14,%R15

    (63) 0x5098 JNE	5070

  (66) 0x509a JMP	5020

  (66) 0x50a0 CMP	$0x20,%R15D

  (66) 0x50a4 JAE	50b3

  (66) 0x50a6 MOV	0x78(%RSP),%R11

  (66) 0x50ab XOR	%R13D,%R13D

  (66) 0x50ae JMP	518e

  (66) 0x50b3 MOV	0x78(%RSP),%RDX

  (66) 0x50b8 VXORPS	%XMM0,%XMM0,%XMM0

  (66) 0x50bc VXORPS	%XMM1,%XMM1,%XMM1

  (66) 0x50c0 VXORPS	%XMM2,%XMM2,%XMM2

  (66) 0x50c4 VPXOR	%XMM3,%XMM3,%XMM3

  (66) 0x50c8 XOR	%R14D,%R14D

  (66) 0x50cb NOPL	(%RAX,%RAX,1)

    (67) 0x50d0 LEA	(%R10,%R14,1),%R13D

    (67) 0x50d4 VCVTPS2PD	(%RBX,%R13,4),%ZMM4

    (67) 0x50db VCVTPS2PD	0x20(%RBX,%R13,4),%ZMM5

    (67) 0x50e3 VCVTPS2PD	0x40(%RBX,%R13,4),%ZMM6

    (67) 0x50eb VCVTPS2PD	0x60(%RBX,%R13,4),%ZMM7

    (67) 0x50f3 LEA	(%RDI,%R14,1),%R13D

    (67) 0x50f7 ADD	$0x20,%R14

    (67) 0x50fb VCVTPS2PD	(%RDX,%R13,4),%ZMM8

    (67) 0x5102 VCVTPS2PD	0x20(%RDX,%R13,4),%ZMM9

    (67) 0x510a VFMADD231PD	%ZMM8,%ZMM4,%ZMM0

    (67) 0x5110 VCVTPS2PD	0x40(%RDX,%R13,4),%ZMM8

    (67) 0x5118 VFMADD231PD	%ZMM9,%ZMM5,%ZMM1

    (67) 0x511e VCVTPS2PD	0x60(%RDX,%R13,4),%ZMM5

    (67) 0x5126 VFMADD231PD	%ZMM8,%ZMM6,%ZMM2

    (67) 0x512c VFMADD231PD	%ZMM5,%ZMM7,%ZMM3

    (67) 0x5132 CMP	%R14,%RSI

    (67) 0x5135 JNE	50d0

  (66) 0x5137 VADDPD	%ZMM0,%ZMM1,%ZMM0

  (66) 0x513d VADDPD	%ZMM2,%ZMM3,%ZMM2

  (66) 0x5143 MOV	0xc0(%RSP),%RDX

  (66) 0x514b VADDPD	%ZMM0,%ZMM2,%ZMM0

  (66) 0x5151 VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

  (66) 0x5158 VADDPD	%ZMM1,%ZMM0,%ZMM0

  (66) 0x515e VEXTRACTF128	$0x1,%YMM0,%XMM1

  (66) 0x5164 VADDPD	%XMM1,%XMM0,%XMM0

  (66) 0x5168 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (66) 0x516d VADDSD	%XMM1,%XMM0,%XMM0

  (66) 0x5171 TEST	%RDX,%RDX

  (66) 0x5174 JE	5020

  (66) 0x517a MOV	0x78(%RSP),%R11

  (66) 0x517f MOV	%RSI,%R13

  (66) 0x5182 MOV	%RSI,%R14

  (66) 0x5185 CMP	$0x4,%EDX

  (66) 0x5188 JB	505f

  (66) 0x518e VMOVQ	%XMM0,%XMM0

  (66) 0x5192 NOPW	%CS:(%RAX,%RAX,1)

    (68) 0x51a0 LEA	(%R10,%R13,1),%R14D

    (68) 0x51a4 VCVTPS2PD	(%RBX,%R14,4),%YMM1

    (68) 0x51aa LEA	(%RDI,%R13,1),%R14D

    (68) 0x51ae ADD	$0x4,%R13

    (68) 0x51b2 VCVTPS2PD	(%R11,%R14,4),%YMM2

    (68) 0x51b8 VFMADD231PD	%YMM2,%YMM1,%YMM0

    (68) 0x51bd CMP	%R13,%R8

    (68) 0x51c0 JNE	51a0

  (66) 0x51c2 VEXTRACTF128	$0x1,%YMM0,%XMM1

  (66) 0x51c8 CMPQ	$0,0x20(%RSP)

  (66) 0x51ce MOV	%R8,%R14

  (66) 0x51d1 VADDPD	%XMM1,%XMM0,%XMM0

  (66) 0x51d5 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (66) 0x51da VADDSD	%XMM1,%XMM0,%XMM0

  (66) 0x51de JNE	505f

  (66) 0x51e4 JMP	5020

/home/eoseret/llm-attention/attention.cpp: 26 - 193

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

193:    for (size_t r = 0; r < rept; r++)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.91
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:26-26,attention.cpp:193-193
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	0.18
Front-end cycles	2.50
P0 cycles	2.33
P1 cycles	2.33
P2 cycles	2.33
P3 cycles	2.33
P4 cycles	2.33
P5 cycles	2.33
P6 cycles	0.75
P7 cycles	0.75
P8 cycles	0.75
P9 cycles	0.75
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	20.00
Nb loads	2.00
Nb stores	1.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.80
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.52
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	9.38
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.38

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.91
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:26-26,attention.cpp:193-193
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	0.18
Front-end cycles	2.50
P0 cycles	2.33
P1 cycles	2.33
P2 cycles	2.33
P3 cycles	2.33
P4 cycles	2.33
P5 cycles	2.33
P6 cycles	0.75
P7 cycles	0.75
P8 cycles	0.75
P9 cycles	0.75
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	20.00
Nb loads	2.00
Nb stores	1.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.80
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.52
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	9.38
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.38

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:26-193
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:26-33,193.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:26,193.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.50 to 0.18 cycles (13.91x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	20
nb uops	20
loop length	64
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.50 cycles
front end	2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.33	2.33	2.33	2.33	2.33	2.33	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.33	2.33	2.33	2.33	2.33	2.33	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.50
Dispatch	2.33
Overall L1	2.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	6%
store	6%
mul	6%
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

1% of peak load performance is reached (3.20 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.60 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.50 to 2.33 cycles (1.07x speedup).

ASM code

In the binary file, the address of the loop is: 4fef

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV 0x30(%RSP),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
ADD %R12,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
INC %EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %EDX,0x38(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JE 4fb0 <main+0x16d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
CMP $0x1,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %EDX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SETNE %DIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SHR $0x20,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
SETNE %AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL %R12D,%R9D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R9D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %ECX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SETB %R14B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
OR %DIL,%AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
OR %R14B,%AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JMP 503e <main+0x175e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention.cpp:26-193
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:26-33,193.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:26,193.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.50 to 0.18 cycles (13.91x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	20
nb uops	20
loop length	64
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.50 cycles
front end	2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.33	2.33	2.33	2.33	2.33	2.33	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.33	2.33	2.33	2.33	2.33	2.33	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.50
Dispatch	2.33
Overall L1	2.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	6%
store	6%
mul	6%
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

1% of peak load performance is reached (3.20 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.60 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.50 to 2.33 cycles (1.07x speedup).

ASM code

In the binary file, the address of the loop is: 4fef

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV 0x30(%RSP),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
ADD %R12,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
INC %EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %EDX,0x38(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JE 4fb0 <main+0x16d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-1	N/A
CMP $0x1,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %EDX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %EDX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SETNE %DIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SHR $0x20,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
SETNE %AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
IMUL %R12D,%R9D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R9D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %ECX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SETB %R14B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
OR %DIL,%AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
OR %R14B,%AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JMP 503e <main+0x175e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code