OV - attention-avx512 - Loop 41

	Loop Id: 41	Module: attention-avx512	Source: attention.cpp:43-284 [...]	Coverage: 0.16%

0x5b70 VMOVAPS	0xc0(%RSP),%XMM0

0x5b79 MOV	0x120(%RSP),%RDX

0x5b81 MOV	0x140(%RSP),%RCX

0x5b89 MOV	0x138(%RSP),%R8

0x5b91 MOV	0xb0(%RSP),%R13

0x5b99 INC	%RSI

0x5b9c MOV	%R14,%R9

0x5b9f ADD	%RDX,%RCX

0x5ba2 ADD	%RDX,%R8

0x5ba5 ADD	%RDX,%RDI

0x5ba8 VMOVSS	%XMM0,(%R13,%RAX,4)

0x5baf MOV	%RCX,%RAX

0x5bb2 CMP	0x50(%RSP),%R14

0x5bb7 MOV	0xa0(%RSP),%R14

0x5bbf JE	5b30

0x5bc5 MOV	%RSI,%R10

0x5bc8 MOV	%RSI,%R11

0x5bcb AND	$-0x8,%R10

0x5bcf AND	$-0x40,%R11

0x5bd3 MOV	%RAX,0x140(%RSP)

0x5bdb CMP	$0x8,%RSI

0x5bdf JAE	5bf0

0x5be1 VMOVSS	-0x4c19(%RIP),%XMM1

0x5be9 XOR	%EAX,%EAX

0x5beb JMP	5d00

0x5bf0 CMP	$0x40,%RSI

0x5bf4 JAE	5c10

0x5bf6 VMOVSS	-0x4c2e(%RIP),%XMM1

0x5bfe XOR	%EAX,%EAX

0x5c00 JMP	5cad

0x5c10 VMOVAPS	0x3c0(%RSP),%ZMM3

0x5c18 MOV	$0x7ffffffffffffff8,%RAX

0x5c22 XOR	%ECX,%ECX

0x5c24 ADD	$-0x38,%RAX

0x5c28 AND	%RSI,%RAX

0x5c2b VMOVAPS	%ZMM3,%ZMM0

0x5c31 VMOVAPS	%ZMM3,%ZMM1

0x5c37 VMOVAPS	%ZMM3,%ZMM2

0x5c3d NOPL	(%RAX)

  (36) 0x5c40 VMAXPS	-0xc0(%R8,%RCX,4),%ZMM0,%ZMM0

  (36) 0x5c48 VMAXPS	-0x80(%R8,%RCX,4),%ZMM1,%ZMM1

  (36) 0x5c50 VMAXPS	-0x40(%R8,%RCX,4),%ZMM2,%ZMM2

  (36) 0x5c58 VMAXPS	(%R8,%RCX,4),%ZMM3,%ZMM3

  (36) 0x5c5f ADD	$0x40,%RCX

  (36) 0x5c63 CMP	%RCX,%R11

  (36) 0x5c66 JNE	5c40

0x5c68 VMAXPS	%ZMM1,%ZMM0,%ZMM0

0x5c6e VMAXPS	%ZMM3,%ZMM2,%ZMM2

0x5c74 VMAXPS	%ZMM2,%ZMM0,%ZMM0

0x5c7a VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

0x5c81 VMAXPS	%ZMM1,%ZMM0,%ZMM0

0x5c87 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x5c8d VMAXPS	%XMM1,%XMM0,%XMM0

0x5c91 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x5c96 VMAXPS	%XMM1,%XMM0,%XMM0

0x5c9a VMOVSHDUP	%XMM0,%XMM1

0x5c9e VMAXSS	%XMM1,%XMM0,%XMM1

0x5ca2 CMP	%RAX,%RSI

0x5ca5 JE	5d0d

0x5ca7 TEST	$0x38,%SIL

0x5cab JE	5d00

0x5cad MOV	$0x7ffffffffffffff8,%RDX

0x5cb7 VBROADCASTSS	%XMM1,%YMM0

0x5cbc MOV	%RAX,%RCX

0x5cbf MOV	%RSI,%RAX

0x5cc2 AND	%RDX,%RAX

0x5cc5 NOPW	%CS:(%RAX,%RAX,1)

  (46) 0x5cd0 VMAXPS	(%RDI,%RCX,4),%YMM0,%YMM0

  (46) 0x5cd5 ADD	$0x8,%RCX

  (46) 0x5cd9 CMP	%RCX,%R10

  (46) 0x5cdc JNE	5cd0

0x5cde VEXTRACTF128	$0x1,%YMM0,%XMM1

0x5ce4 VMAXPS	%XMM1,%XMM0,%XMM0

0x5ce8 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x5ced VMAXPS	%XMM1,%XMM0,%XMM0

0x5cf1 VMOVSHDUP	%XMM0,%XMM1

0x5cf5 VMAXSS	%XMM1,%XMM0,%XMM1

0x5cf9 JMP	5d08

  (45) 0x5d00 VMAXSS	(%RDI,%RAX,4),%XMM1,%XMM1

  (45) 0x5d05 INC	%RAX

  (45) 0x5d08 CMP	%RAX,%RSI

  (45) 0x5d0b JNE	5d00

0x5d0d MOV	%RSI,0x30(%RSP)

0x5d12 MOV	%RDI,0x20(%RSP)

0x5d17 MOV	%R9,0x130(%RSP)

0x5d1f VMOVAPS	%XMM1,0x40(%RSP)

0x5d25 MOV	%R8,0x138(%RSP)

0x5d2d MOV	%R10,0x180(%RSP)

0x5d35 CMP	$0x8,%RSI

0x5d39 JAE	5d50

0x5d3b VXORPS	%XMM2,%XMM2,%XMM2

0x5d3f XOR	%R14D,%R14D

0x5d42 JMP	5fd0

0x5d50 CMP	$0x40,%RSI

0x5d54 JAE	5d70

0x5d56 VXORPS	%XMM2,%XMM2,%XMM2

0x5d5a XOR	%R14D,%R14D

0x5d5d JMP	5f2f

0x5d70 MOV	$0x7ffffffffffffff8,%RAX

0x5d7a VBROADCASTSS	%XMM1,%ZMM0

0x5d80 VXORPS	%XMM1,%XMM1,%XMM1

0x5d84 VXORPS	%XMM2,%XMM2,%XMM2

0x5d88 VXORPS	%XMM3,%XMM3,%XMM3

0x5d8c VPXOR	%XMM4,%XMM4,%XMM4

0x5d90 XOR	%R13D,%R13D

0x5d93 MOV	%R11,0x268(%RSP)

0x5d9b LEA	-0x38(%RAX),%R14

0x5d9f AND	%RSI,%R14

0x5da2 VMOVAPS	%ZMM0,0x400(%RSP)

0x5daa NOPW	(%RAX,%RAX,1)

  (37) 0x5db0 VMOVAPS	%ZMM3,0x200(%RSP)

  (37) 0x5db8 VMOVAPS	%ZMM2,0x1c0(%RSP)

  (37) 0x5dc0 VMOVAPS	%ZMM1,0xc0(%RSP)

  (37) 0x5dc8 VMOVUPS	-0xc0(%R8,%R13,4),%ZMM0

  (37) 0x5dd0 VMOVAPS	0x400(%RSP),%ZMM6

  (37) 0x5dd8 VMOVUPS	-0x80(%R8,%R13,4),%ZMM1

  (37) 0x5de0 VMOVUPS	-0x40(%R8,%R13,4),%ZMM2

  (37) 0x5de8 VMOVUPS	(%R8,%R13,4),%ZMM3

  (37) 0x5def VMOVDQA64	%ZMM4,0x280(%RSP)

  (37) 0x5df7 VSUBPS	%ZMM6,%ZMM2,%ZMM5

  (37) 0x5dfd VSUBPS	%ZMM6,%ZMM0,%ZMM0

  (37) 0x5e03 VSUBPS	%ZMM6,%ZMM1,%ZMM1

  (37) 0x5e09 VSUBPS	%ZMM6,%ZMM3,%ZMM2

  (37) 0x5e0f VMOVAPS	%ZMM1,0x340(%RSP)

  (37) 0x5e17 VMOVAPS	%ZMM5,0x300(%RSP)

  (37) 0x5e1f VMOVAPS	%ZMM2,0x2c0(%RSP)

  (37) 0x5e27 CALL	69b0 <@plt_start@+0x20>

  (37) 0x5e2c VMOVAPS	%ZMM0,0x380(%RSP)

  (37) 0x5e34 VMOVAPS	0x340(%RSP),%ZMM0

  (37) 0x5e3c CALL	69b0 <@plt_start@+0x20>

  (37) 0x5e41 VMOVAPS	%ZMM0,0x340(%RSP)

  (37) 0x5e49 VMOVAPS	0x300(%RSP),%ZMM0

  (37) 0x5e51 CALL	69b0 <@plt_start@+0x20>

  (37) 0x5e56 VMOVAPS	%ZMM0,0x300(%RSP)

  (37) 0x5e5e VMOVAPS	0x2c0(%RSP),%ZMM0

  (37) 0x5e66 CALL	69b0 <@plt_start@+0x20>

  (37) 0x5e6b VMOVAPS	0x280(%RSP),%ZMM4

  (37) 0x5e73 VMOVAPS	0x200(%RSP),%ZMM3

  (37) 0x5e7b VMOVAPS	0x1c0(%RSP),%ZMM2

  (37) 0x5e83 VMOVAPS	0xc0(%RSP),%ZMM1

  (37) 0x5e8b MOV	0x268(%RSP),%R11

  (37) 0x5e93 MOV	0x138(%RSP),%R8

  (37) 0x5e9b ADD	$0x40,%R13

  (37) 0x5e9f VADDPS	0x380(%RSP),%ZMM1,%ZMM1

  (37) 0x5ea7 VADDPS	0x340(%RSP),%ZMM2,%ZMM2

  (37) 0x5eaf VADDPS	0x300(%RSP),%ZMM3,%ZMM3

  (37) 0x5eb7 VADDPS	%ZMM4,%ZMM0,%ZMM4

  (37) 0x5ebd CMP	%R13,%R11

  (37) 0x5ec0 JNE	5db0

0x5ec6 VADDPS	%ZMM1,%ZMM2,%ZMM0

0x5ecc MOV	0x30(%RSP),%RSI

0x5ed1 VADDPS	%ZMM0,%ZMM3,%ZMM0

0x5ed7 VADDPS	%ZMM0,%ZMM4,%ZMM0

0x5edd VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

0x5ee4 VADDPS	%ZMM1,%ZMM0,%ZMM0

0x5eea VEXTRACTF128	$0x1,%YMM0,%XMM1

0x5ef0 VADDPS	%XMM1,%XMM0,%XMM0

0x5ef4 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x5ef9 VADDPS	%XMM1,%XMM0,%XMM0

0x5efd VMOVSHDUP	%XMM0,%XMM1

0x5f01 VADDSS	%XMM1,%XMM0,%XMM2

0x5f05 CMP	%R14,%RSI

0x5f08 JNE	5f1a

0x5f0a VMOVAPS	0x40(%RSP),%XMM1

0x5f10 MOV	0x20(%RSP),%RDI

0x5f15 JMP	6010

0x5f1a VMOVAPS	0x40(%RSP),%XMM1

0x5f20 MOV	0x20(%RSP),%RDI

0x5f25 TEST	$0x38,%SIL

0x5f29 JE	5fd0

0x5f2f VXORPS	%XMM0,%XMM0,%XMM0

0x5f33 VBLENDPS	$0x1,%XMM2,%XMM0,%XMM2

0x5f39 VBROADCASTSS	%XMM1,%YMM0

0x5f3e MOV	$0x7ffffffffffffff8,%RAX

0x5f48 MOV	%R14,%R13

0x5f4b MOV	%RSI,%R14

0x5f4e AND	%RAX,%R14

0x5f51 VMOVAPS	%YMM0,0x1c0(%RSP)

0x5f5a NOPW	(%RAX,%RAX,1)

  (44) 0x5f60 VMOVUPS	(%RDI,%R13,4),%YMM0

  (44) 0x5f66 VMOVAPS	%YMM2,0xc0(%RSP)

  (44) 0x5f6f VSUBPS	0x1c0(%RSP),%YMM0,%YMM0

  (44) 0x5f78 CALL	69c0 <@plt_start@+0x30>

  (44) 0x5f7d VMOVAPS	0xc0(%RSP),%YMM2

  (44) 0x5f86 MOV	0x20(%RSP),%RDI

  (44) 0x5f8b ADD	$0x8,%R13

  (44) 0x5f8f VADDPS	%YMM2,%YMM0,%YMM2

  (44) 0x5f93 CMP	%R13,0x180(%RSP)

  (44) 0x5f9b JNE	5f60

0x5f9d VEXTRACTF128	$0x1,%YMM2,%XMM0

0x5fa3 MOV	0x30(%RSP),%RSI

0x5fa8 VADDPS	%XMM0,%XMM2,%XMM0

0x5fac VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x5fb1 VADDPS	%XMM1,%XMM0,%XMM0

0x5fb5 VMOVSHDUP	%XMM0,%XMM1

0x5fb9 VADDSS	%XMM1,%XMM0,%XMM2

0x5fbd VMOVAPS	0x40(%RSP),%XMM1

0x5fc3 CMP	%R14,%RSI

0x5fc6 JE	6010

0x5fc8 NOPL	(%RAX,%RAX,1)

  (38) 0x5fd0 VMOVSS	(%RDI,%R14,4),%XMM0

  (38) 0x5fd6 VMOVAPS	%XMM2,0xc0(%RSP)

  (38) 0x5fdf VSUBSS	%XMM1,%XMM0,%XMM0

  (38) 0x5fe3 VZEROUPPER

  (38) 0x5fe6 CALL	69d0 <@plt_start@+0x40>

  (38) 0x5feb VMOVAPS	0xc0(%RSP),%XMM2

  (38) 0x5ff4 VMOVAPS	0x40(%RSP),%XMM1

  (38) 0x5ffa MOV	0x20(%RSP),%RDI

  (38) 0x5fff MOV	0x30(%RSP),%RSI

  (38) 0x6004 INC	%R14

  (38) 0x6007 VADDSS	%XMM2,%XMM0,%XMM2

  (38) 0x600b CMP	%R14,%RSI

  (38) 0x600e JNE	5fd0

0x6010 VMOVAPS	%XMM2,0xc0(%RSP)

0x6019 CMP	$0x8,%RSI

0x601d JAE	6030

0x601f MOV	0x140(%RSP),%RCX

0x6027 XOR	%R14D,%R14D

0x602a JMP	6190

0x6030 CMP	$0x10,%RSI

0x6034 JAE	60e0

0x603a XOR	%R14D,%R14D

0x603d VBROADCASTSS	%XMM1,%YMM0

0x6042 MOV	$0x7ffffffffffffff8,%RAX

0x604c MOV	%R14,%R13

0x604f MOV	%RSI,%R14

0x6052 AND	%RAX,%R14

0x6055 VMOVAPS	%YMM0,0x1c0(%RSP)

0x605e VMOVSS	-0x50a6(%RIP),%XMM0

0x6066 VDIVSS	0xc0(%RSP),%XMM0,%XMM0

0x606f VBROADCASTSS	%XMM0,%YMM0

0x6074 VMOVAPS	%YMM0,0x200(%RSP)

0x607d NOPL	(%RAX)

  (42) 0x6080 VMOVUPS	(%RDI,%R13,4),%YMM0

  (42) 0x6086 VSUBPS	0x1c0(%RSP),%YMM0,%YMM0

  (42) 0x608f CALL	69c0 <@plt_start@+0x30>

  (42) 0x6094 VMULPS	0x200(%RSP),%YMM0,%YMM0

  (42) 0x609d MOV	0x140(%RSP),%RCX

  (42) 0x60a5 MOV	0x20(%RSP),%RDI

  (42) 0x60aa VMOVUPS	%YMM0,(%RCX,%R13,4)

  (42) 0x60b0 ADD	$0x8,%R13

  (42) 0x60b4 CMP	%R13,0x180(%RSP)

  (42) 0x60bc JNE	6080

0x60be VMOVAPS	0x40(%RSP),%XMM1

0x60c4 MOV	0x30(%RSP),%RSI

0x60c9 CMP	%R14,%RSI

0x60cc JNE	6190

0x60d2 JMP	61f0

0x60e0 VBROADCASTSS	%XMM1,%ZMM0

0x60e6 MOV	%RSI,%RAX

0x60e9 AND	$-0x10,%RAX

0x60ed XOR	%R13D,%R13D

0x60f0 MOV	%RAX,0x1c0(%RSP)

0x60f8 MOV	$0x7ffffffffffffff8,%RAX

0x6102 VMOVAPS	%ZMM0,0x200(%RSP)

0x610a VMOVSS	-0x5152(%RIP),%XMM0

0x6112 LEA	-0x8(%RAX),%R14

0x6116 AND	%RSI,%R14

0x6119 VDIVSS	%XMM2,%XMM0,%XMM0

0x611d VBROADCASTSS	%XMM0,%ZMM0

0x6123 VMOVAPS	%ZMM0,0x280(%RSP)

0x612b NOPL	(%RAX,%RAX,1)

  (39) 0x6130 VMOVUPS	(%RDI,%R13,4),%ZMM0

  (39) 0x6137 VSUBPS	0x200(%RSP),%ZMM0,%ZMM0

  (39) 0x613f CALL	69b0 <@plt_start@+0x20>

  (39) 0x6144 VMULPS	0x280(%RSP),%ZMM0,%ZMM0

  (39) 0x614c MOV	0x140(%RSP),%RCX

  (39) 0x6154 MOV	0x20(%RSP),%RDI

  (39) 0x6159 VMOVUPS	%ZMM0,(%RCX,%R13,4)

  (39) 0x6160 ADD	$0x10,%R13

  (39) 0x6164 CMP	%R13,0x1c0(%RSP)

  (39) 0x616c JNE	6130

0x616e VMOVAPS	0x40(%RSP),%XMM1

0x6174 MOV	0x30(%RSP),%RSI

0x6179 CMP	%R14,%RSI

0x617c JE	61f0

0x617e TEST	$0x8,%SIL

0x6182 JNE	603d

0x6188 NOPL	(%RAX,%RAX,1)

0x6190 VMOVSS	-0x51d8(%RIP),%XMM0

0x6198 VDIVSS	0xc0(%RSP),%XMM0,%XMM0

0x61a1 VMOVSS	%XMM0,0x180(%RSP)

0x61aa NOPW	(%RAX,%RAX,1)

  (43) 0x61b0 VMOVSS	(%RDI,%R14,4),%XMM0

  (43) 0x61b6 MOV	%RCX,%R13

  (43) 0x61b9 VSUBSS	%XMM1,%XMM0,%XMM0

  (43) 0x61bd VZEROUPPER

  (43) 0x61c0 CALL	69d0 <@plt_start@+0x40>

  (43) 0x61c5 VMULSS	0x180(%RSP),%XMM0,%XMM0

  (43) 0x61ce VMOVAPS	0x40(%RSP),%XMM1

  (43) 0x61d4 MOV	0x20(%RSP),%RDI

  (43) 0x61d9 MOV	0x30(%RSP),%RSI

  (43) 0x61de MOV	%R13,%RCX

  (43) 0x61e1 VMOVSS	%XMM0,(%R13,%R14,4)

  (43) 0x61e8 INC	%R14

  (43) 0x61eb CMP	%R14,%RSI

  (43) 0x61ee JNE	61b0

0x61f0 MOV	0x130(%RSP),%RAX

0x61f8 LEA	0x1(%RAX),%R14

0x61fc CMP	0x50(%RSP),%R14

0x6201 JAE	5b70

0x6207 MOV	%RAX,%RDI

0x620a IMUL	0x260(%RSP),%RDI

0x6213 MOV	0x258(%RSP),%RDX

0x621b LEA	(,%RAX,4),%RAX

0x6223 XOR	%ESI,%ESI

0x6225 SUB	%RAX,%RDX

0x6228 ADD	$0x4,%RDI

0x622c ADD	0x58(%RSP),%RDI

0x6231 VZEROUPPER

0x6234 CALL	69e0 <@plt_start@+0x50>

0x6239 MOV	0x130(%RSP),%RAX

0x6241 MOV	0x20(%RSP),%RDI

0x6246 MOV	0x30(%RSP),%RSI

0x624b JMP	5b70

/home/eoseret/llm-attention/attention.cpp: 43 - 284

--------------------------------------------------------------------------------

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

[...]

284:    for (size_t r = 0; r < rept; r++)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.90
CQA speedup if FP arith vectorized	1.03
CQA speedup if fully vectorized	1.62
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.84
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:43-44,attention.cpp:47-47,attention.cpp:52-52,attention.cpp:55-55,attention.cpp:58-61,attention.cpp:284-284
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.88
CQA cycles if no scalar integer	13.13
CQA cycles if FP arith vectorized	24.05
CQA cycles if fully vectorized	15.31
Front-end cycles	24.88
P0 cycles	11.67
P1 cycles	11.67
P2 cycles	11.67
P3 cycles	11.67
P4 cycles	11.67
P5 cycles	11.67
P6 cycles	13.50
P7 cycles	13.50
P8 cycles	13.50
P9 cycles	13.50
P10 cycles	11.00
P11 cycles	11.50
P12 cycles	11.50
P13 cycles	11.00
P14 cycles	6.50
P15 cycles	6.50
DIV/SQRT cycles	7.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	204.00
Nb uops	199.00
Nb loads	35.00
Nb stores	18.00
Nb stack references	21.00
FLOP/cycle	3.42
Nb FLOP add-sub	82.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.07
Bytes prefetched	0.00
Bytes loaded	356.00
Bytes stored	392.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	42.86
Vectorization ratio load	25.93
Vectorization ratio store	44.44
Vectorization ratio mul	NA
Vectorization ratio add_sub	57.14
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	45.33
Vector-efficiency ratio all	25.61
Vector-efficiency ratio load	16.90
Vector-efficiency ratio store	34.03
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	40.18
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	23.92

Metric	Value
CQA speedup if no scalar integer	1.90
CQA speedup if FP arith vectorized	1.03
CQA speedup if fully vectorized	1.62
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.84
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:43-44,attention.cpp:47-47,attention.cpp:52-52,attention.cpp:55-55,attention.cpp:58-61,attention.cpp:284-284
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.88
CQA cycles if no scalar integer	13.13
CQA cycles if FP arith vectorized	24.05
CQA cycles if fully vectorized	15.31
Front-end cycles	24.88
P0 cycles	11.67
P1 cycles	11.67
P2 cycles	11.67
P3 cycles	11.67
P4 cycles	11.67
P5 cycles	11.67
P6 cycles	13.50
P7 cycles	13.50
P8 cycles	13.50
P9 cycles	13.50
P10 cycles	11.00
P11 cycles	11.50
P12 cycles	11.50
P13 cycles	11.00
P14 cycles	6.50
P15 cycles	6.50
DIV/SQRT cycles	7.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	204.00
Nb uops	199.00
Nb loads	35.00
Nb stores	18.00
Nb stack references	21.00
FLOP/cycle	3.42
Nb FLOP add-sub	82.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.07
Bytes prefetched	0.00
Bytes loaded	356.00
Bytes stored	392.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	42.86
Vectorization ratio load	25.93
Vectorization ratio store	44.44
Vectorization ratio mul	NA
Vectorization ratio add_sub	57.14
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	45.33
Vector-efficiency ratio all	25.61
Vector-efficiency ratio load	16.90
Vector-efficiency ratio store	34.03
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	40.18
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	23.92

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:43-284
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:43-61,284.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:43-44,47,52,55,58-61,284.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 490 paths individually, rerun with max-paths=490
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 490 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.88 to 13.13 cycles (1.90x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 25% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 24.88 to 15.31 cycles (1.62x speedup).

Details

42% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

25% of SSE/AVX loads are used in vector version.
44% of SSE/AVX stores are used in vector version.
57% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
45% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVAPS: 3 occurrences►
- /home/eoseret/llm-attention/attention.cpp:52
- /home/eoseret/llm-attention/attention.cpp:55
- /home/eoseret/llm-attention/attention.cpp:55

Vector unaligned load/store instructions

Detected 6 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 4 occurrences►
- /home/eoseret/llm-attention/attention.cpp:47
- /home/eoseret/llm-attention/attention.cpp:47
- /home/eoseret/llm-attention/attention.cpp:52
- /home/eoseret/llm-attention/attention.cpp:52
VEXTRACTF64X4: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:47
- /home/eoseret/llm-attention/attention.cpp:52

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 8 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time). 8 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 85 FP arithmetical operations:

82: addition or subtraction
3: divide

The binary loop is loading 356 bytes (89 single precision FP elements). The binary loop is storing 392 bytes (98 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	204
nb uops	199
loop length	1053
used x86 registers	12
used mmx registers	0
used xmm registers	5
used ymm registers	3
used zmm registers	5
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	24.88 cycles
front end	24.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	11.67	11.67	11.67	11.67	11.67	11.67	13.50	13.50	13.50	13.50	11.00	11.50	11.50	11.00	6.50	6.50
cycles	11.67	11.67	11.67	11.67	11.67	11.67	13.50	13.50	13.50	13.50	11.00	11.50	11.50	11.00	6.50	6.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

7.50

Cycles summary

Front-end	24.88
Dispatch	13.50
DIV/SQRT	7.50
Overall L1	24.88

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	5%

all	72%
load	50%
store	80%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	80%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	78%

INT+FP

all	42%
load	25%
store	44%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	57%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	45%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	35%
load	20%
store	51%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	51%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	33%

INT+FP

all	25%
load	16%
store	34%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	40%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.88 cycles. At this rate:

5% of peak load performance is reached (14.31 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (15.76 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 24.88 to 13.50 cycles (1.84x speedup).

ASM code

In the binary file, the address of the loop is: 5bc5

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVAPS 0xc0(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV 0x120(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x140(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x138(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xb0(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R14,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RDX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS %XMM0,(%R13,%RAX,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP 0x50(%RSP),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV 0xa0(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JE 5b30 <main+0x2250>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RSI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $-0x8,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x40,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 5bf0 <main+0x2310>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VMOVSS -0x4c19(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 5d00 <main+0x2420>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
CMP $0x40,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 5c10 <main+0x2330>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VMOVSS -0x4c2e(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 5cad <main+0x23cd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VMOVAPS 0x3c0(%RSP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
MOV $0x7ffffffffffffff8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD $-0x38,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %ZMM3,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPS %ZMM3,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPS %ZMM3,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMAXPS %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMAXPS %ZMM3,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMAXPS %ZMM2,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMAXPS %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
VMAXSS %XMM1,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (6.3%)
CMP %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5d0d <main+0x242d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
TEST $0x38,%SIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 5d00 <main+0x2420>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV $0x7ffffffffffffff8,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VBROADCASTSS %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
VMAXSS %XMM1,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (6.3%)
JMP 5d08 <main+0x2428>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV %RSI,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPS %XMM1,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %R8,0x138(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 5d50 <main+0x2470>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 5fd0 <main+0x26f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
CMP $0x40,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 5d70 <main+0x2490>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 5f2f <main+0x264f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV $0x7ffffffffffffff8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VBROADCASTSS %XMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPXOR %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,0x268(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA -0x38(%RAX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RSI,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVAPS %ZMM0,0x400(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VADDPS %ZMM1,%ZMM2,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOV 0x30(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VADDPS %ZMM0,%ZMM3,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPS %ZMM0,%ZMM4,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VADDPS %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (6.3%)
CMP %R14,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 5f1a <main+0x263a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV 0x20(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 6010 <main+0x2730>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV 0x20(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
TEST $0x38,%SIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 5fd0 <main+0x26f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VBLENDPS $0x1,%XMM2,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VBROADCASTSS %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
MOV $0x7ffffffffffffff8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND %RAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVAPS %YMM0,0x1c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VEXTRACTF128 $0x1,%YMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
MOV 0x30(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VADDPS %XMM0,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (6.3%)
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
CMP %R14,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 6010 <main+0x2730>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVAPS %XMM2,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
CMP $0x8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 6030 <main+0x2750>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x140(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 6190 <main+0x28b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
CMP $0x10,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 60e0 <main+0x2800>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VBROADCASTSS %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
MOV $0x7ffffffffffffff8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND %RAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVAPS %YMM0,0x1c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVSS -0x50a6(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VDIVSS 0xc0(%RSP),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
VBROADCASTSS %XMM0,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
VMOVAPS %YMM0,0x200(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV 0x30(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %R14,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 6190 <main+0x28b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
JMP 61f0 <main+0x2910>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VBROADCASTSS %XMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x10,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x1c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV $0x7ffffffffffffff8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %ZMM0,0x200(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMOVSS -0x5152(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
LEA -0x8(%RAX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RSI,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VDIVSS %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
VBROADCASTSS %XMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
VMOVAPS %ZMM0,0x280(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV 0x30(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %R14,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 61f0 <main+0x2910>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
TEST $0x8,%SIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 603d <main+0x275d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVSS -0x51d8(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VDIVSS 0xc0(%RSP),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
VMOVSS %XMM0,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0x130(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1(%RAX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x50(%RSP),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JAE 5b70 <main+0x2290>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL 0x260(%RSP),%RDI	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.33	N/A
MOV 0x258(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
LEA (,%RAX,4),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0x4,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD 0x58(%RSP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 69e0 <@plt_start@+0x50>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x130(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x30(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JMP 5b70 <main+0x2290>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention.cpp:43-284
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:43-61,284.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:43-44,47,52,55,58-61,284.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 490 paths individually, rerun with max-paths=490
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

42% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

25% of SSE/AVX loads are used in vector version.
44% of SSE/AVX stores are used in vector version.
57% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
45% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVAPS: 3 occurrences►
- /home/eoseret/llm-attention/attention.cpp:52
- /home/eoseret/llm-attention/attention.cpp:55
- /home/eoseret/llm-attention/attention.cpp:55

Vector unaligned load/store instructions

Detected 6 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 4 occurrences►
- /home/eoseret/llm-attention/attention.cpp:47
- /home/eoseret/llm-attention/attention.cpp:47
- /home/eoseret/llm-attention/attention.cpp:52
- /home/eoseret/llm-attention/attention.cpp:52
VEXTRACTF64X4: 2 occurrences►
- /home/eoseret/llm-attention/attention.cpp:47
- /home/eoseret/llm-attention/attention.cpp:52

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 85 FP arithmetical operations:

82: addition or subtraction
3: divide

The binary loop is loading 356 bytes (89 single precision FP elements). The binary loop is storing 392 bytes (98 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	204
nb uops	199
loop length	1053
used x86 registers	12
used mmx registers	0
used xmm registers	5
used ymm registers	3
used zmm registers	5
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	24.88 cycles
front end	24.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	11.67	11.67	11.67	11.67	11.67	11.67	13.50	13.50	13.50	13.50	11.00	11.50	11.50	11.00	6.50	6.50
cycles	11.67	11.67	11.67	11.67	11.67	11.67	13.50	13.50	13.50	13.50	11.00	11.50	11.50	11.00	6.50	6.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

7.50

Cycles summary

Front-end	24.88
Dispatch	13.50
DIV/SQRT	7.50
Overall L1	24.88

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	5%

all	72%
load	50%
store	80%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	80%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	78%

INT+FP

all	42%
load	25%
store	44%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	57%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	45%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	35%
load	20%
store	51%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	51%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	33%

INT+FP

all	25%
load	16%
store	34%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	40%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.88 cycles. At this rate:

5% of peak load performance is reached (14.31 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (15.76 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 5bc5

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVAPS 0xc0(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV 0x120(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x140(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x138(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xb0(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R14,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RDX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS %XMM0,(%R13,%RAX,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP 0x50(%RSP),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOV 0xa0(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JE 5b30 <main+0x2250>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RSI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $-0x8,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x40,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 5bf0 <main+0x2310>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VMOVSS -0x4c19(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 5d00 <main+0x2420>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
CMP $0x40,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 5c10 <main+0x2330>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VMOVSS -0x4c2e(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 5cad <main+0x23cd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VMOVAPS 0x3c0(%RSP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
MOV $0x7ffffffffffffff8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD $-0x38,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %ZMM3,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPS %ZMM3,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPS %ZMM3,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMAXPS %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMAXPS %ZMM3,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMAXPS %ZMM2,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMAXPS %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
VMAXSS %XMM1,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (6.3%)
CMP %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5d0d <main+0x242d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
TEST $0x38,%SIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 5d00 <main+0x2420>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV $0x7ffffffffffffff8,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VBROADCASTSS %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
VMAXSS %XMM1,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (6.3%)
JMP 5d08 <main+0x2428>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV %RSI,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPS %XMM1,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %R8,0x138(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 5d50 <main+0x2470>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 5fd0 <main+0x26f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
CMP $0x40,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 5d70 <main+0x2490>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 5f2f <main+0x264f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV $0x7ffffffffffffff8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VBROADCASTSS %XMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPXOR %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,0x268(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA -0x38(%RAX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RSI,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVAPS %ZMM0,0x400(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VADDPS %ZMM1,%ZMM2,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOV 0x30(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VADDPS %ZMM0,%ZMM3,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPS %ZMM0,%ZMM4,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VADDPS %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (6.3%)
CMP %R14,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 5f1a <main+0x263a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV 0x20(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 6010 <main+0x2730>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV 0x20(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
TEST $0x38,%SIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 5fd0 <main+0x26f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VBLENDPS $0x1,%XMM2,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VBROADCASTSS %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
MOV $0x7ffffffffffffff8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND %RAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVAPS %YMM0,0x1c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VEXTRACTF128 $0x1,%YMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
MOV 0x30(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VADDPS %XMM0,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (6.3%)
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
CMP %R14,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 6010 <main+0x2730>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVAPS %XMM2,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
CMP $0x8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 6030 <main+0x2750>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV 0x140(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 6190 <main+0x28b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
CMP $0x10,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 60e0 <main+0x2800>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VBROADCASTSS %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
MOV $0x7ffffffffffffff8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND %RAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVAPS %YMM0,0x1c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVSS -0x50a6(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VDIVSS 0xc0(%RSP),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
VBROADCASTSS %XMM0,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
VMOVAPS %YMM0,0x200(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV 0x30(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %R14,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 6190 <main+0x28b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
JMP 61f0 <main+0x2910>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VBROADCASTSS %XMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x10,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x1c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV $0x7ffffffffffffff8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %ZMM0,0x200(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMOVSS -0x5152(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
LEA -0x8(%RAX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RSI,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VDIVSS %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
VBROADCASTSS %XMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (6.3%)
VMOVAPS %ZMM0,0x280(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV 0x30(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %R14,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 61f0 <main+0x2910>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
TEST $0x8,%SIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 603d <main+0x275d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVSS -0x51d8(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VDIVSS 0xc0(%RSP),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
VMOVSS %XMM0,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0x130(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1(%RAX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x50(%RSP),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JAE 5b70 <main+0x2290>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL 0x260(%RSP),%RDI	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.33	N/A
MOV 0x258(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
LEA (,%RAX,4),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0x4,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD 0x58(%RSP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 69e0 <@plt_start@+0x50>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x130(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x30(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JMP 5b70 <main+0x2290>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

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Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code