OV - attention-avx512 - Loop 48

	Loop Id: 48	Module: attention-avx512	Source: attention.cpp:240-241 [...]	Coverage: 0.11%

0x5880 VPMULLQ	%YMM0,%YMM5,%YMM7

0x5886 VPMULLQ	%YMM0,%YMM6,%YMM8

0x588c VPADDQ	%YMM3,%YMM5,%YMM5

0x5890 VPADDQ	%YMM3,%YMM6,%YMM6

0x5894 VPADDQ	%YMM4,%YMM7,%YMM7

0x5898 VPADDQ	%YMM4,%YMM8,%YMM8

0x589c VPEXTRQ	$0x1,%XMM7,%R12

0x58a2 VMOVQ	%XMM7,%RDX

0x58a7 VEXTRACTI128	$0x1,%YMM7,%XMM7

0x58ad VMOVQ	%XMM8,%RAX

0x58b2 VPEXTRQ	$0x1,%XMM8,%RCX

0x58b8 VMOVQ	%XMM7,%R9

0x58bd VPEXTRQ	$0x1,%XMM7,%RSI

0x58c3 VEXTRACTI128	$0x1,%YMM8,%XMM7

0x58c9 VMOVDQU	0x10(%R10,%R13,4),%XMM8    [2]

0x58d0 VMOVQ	%XMM7,%R8

0x58d5 VPEXTRQ	$0x1,%XMM7,%R11

0x58db VMOVDQU	(%R10,%R13,4),%XMM7    [2]

0x58e1 ADD	$0x8,%R13

0x58e5 VMOVD	%XMM7,(%RDI,%RDX,4)    [1]

0x58ea VEXTRACTPS	$0x1,%XMM7,(%RDI,%R12,4)    [1]

0x58f1 VEXTRACTPS	$0x2,%XMM7,(%RDI,%R9,4)    [1]

0x58f8 VEXTRACTPS	$0x3,%XMM7,(%RDI,%RSI,4)    [1]

0x58ff MOV	0x80(%RSP),%RSI    [3]

0x5907 VMOVD	%XMM8,(%RDI,%RAX,4)    [1]

0x590c VEXTRACTPS	$0x1,%XMM8,(%RDI,%RCX,4)    [1]

0x5913 VEXTRACTPS	$0x2,%XMM8,(%RDI,%R8,4)    [1]

0x591a VEXTRACTPS	$0x3,%XMM8,(%RDI,%R11,4)    [1]

0x5921 CMP	%R13,%RSI

0x5924 JNE	5880

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1046 - 1046

--------------------------------------------------------------------------------

1046: 	return *(this->_M_impl._M_start + __n);

/home/eoseret/llm-attention/attention.cpp: 240 - 241

--------------------------------------------------------------------------------

240:          for (int j = 0; j < dim; ++j)// vectorized

241:             h_KT[j * context_size + i] = h_K[i * dim + j];

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.31
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.64
Bottlenecks	P14, P15,
Function	main
Source	stl_vector.h:1046-1046,attention.cpp:240-241
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	1.09
Front-end cycles	4.88
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	2.75
P7 cycles	2.75
P8 cycles	2.75
P9 cycles	2.75
P10 cycles	4.50
P11 cycles	4.50
P12 cycles	4.50
P13 cycles	4.50
P14 cycles	8.00
P15 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	39.00
Nb loads	3.00
Nb stores	8.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.00
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	38.46
Vectorization ratio load	100.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	20.00
Vector-efficiency ratio all	21.15
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.31
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.64
Bottlenecks	P14, P15,
Function	main
Source	stl_vector.h:1046-1046,attention.cpp:240-241
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	1.09
Front-end cycles	4.88
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	2.75
P7 cycles	2.75
P8 cycles	2.75
P9 cycles	2.75
P10 cycles	4.50
P11 cycles	4.50
P12 cycles	4.50
P13 cycles	4.50
P14 cycles	8.00
P15 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	39.00
Nb loads	3.00
Nb stores	8.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.00
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	38.46
Vectorization ratio load	100.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	20.00
Vector-efficiency ratio all	21.15
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:240-241
Module	attention-avx512

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/home/eoseret/llm-attention/attention.cpp:240-241

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 21% of vector register length is used (average across all SSE/AVX instructions).

Details

38% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX stores are used in vector version.
20% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VEXTRACTPS: 6 occurrences►
- /home/eoseret/llm-attention/attention.cpp:241
- /home/eoseret/llm-attention/attention.cpp:241
- /home/eoseret/llm-attention/attention.cpp:241
- /home/eoseret/llm-attention/attention.cpp:241
- /home/eoseret/llm-attention/attention.cpp:241
- /home/eoseret/llm-attention/attention.cpp:241
VPEXTRQ: 4 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	30
nb uops	39
loop length	170
used x86 registers	12
used mmx registers	0
used xmm registers	2
used ymm registers	7
used zmm registers	0
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.88 cycles
front end	4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	2.75	2.75	2.75	2.75	4.50	4.50	4.50	4.50	8.00	8.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	2.75	2.75	2.75	2.75	4.50	4.50	4.50	4.50	8.00	8.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.88
Dispatch	8.00
Data deps.	1.00
Overall L1	8.00

Vectorization ratios

INT

all	50%
load	100%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	38%
load	100%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	25%
load	25%
store	6%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	21%
load	25%
store	6%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

1% of peak load performance is reached (5.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 5880

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VPMULLQ %YMM0,%YMM5,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM0,%YMM6,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM3,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM3,%YMM6,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM4,%YMM7,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM4,%YMM8,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPEXTRQ $0x1,%XMM7,%R12	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM7,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM8,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM7,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM7,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM8,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVDQU 0x10(%R10,%R13,4),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM7,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM7,%R11	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVDQU (%R10,%R13,4),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADD $0x8,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVD %XMM7,(%RDI,%RDX,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	8	0.50	scal (6.3%)
VEXTRACTPS $0x1,%XMM7,(%RDI,%R12,4)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (6.3%)
VEXTRACTPS $0x2,%XMM7,(%RDI,%R9,4)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (6.3%)
VEXTRACTPS $0x3,%XMM7,(%RDI,%RSI,4)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (6.3%)
MOV 0x80(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVD %XMM8,(%RDI,%RAX,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	8	0.50	scal (6.3%)
VEXTRACTPS $0x1,%XMM8,(%RDI,%RCX,4)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (6.3%)
VEXTRACTPS $0x2,%XMM8,(%RDI,%R8,4)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (6.3%)
VEXTRACTPS $0x3,%XMM8,(%RDI,%R11,4)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (6.3%)
CMP %R13,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 5880 <main+0x1be0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A

Function	main
Source file and lines	attention.cpp:240-241
Module	attention-avx512

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/home/eoseret/llm-attention/attention.cpp:240-241

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 21% of vector register length is used (average across all SSE/AVX instructions).

Details

38% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX stores are used in vector version.
20% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VEXTRACTPS: 6 occurrences►
- /home/eoseret/llm-attention/attention.cpp:241
- /home/eoseret/llm-attention/attention.cpp:241
- /home/eoseret/llm-attention/attention.cpp:241
- /home/eoseret/llm-attention/attention.cpp:241
- /home/eoseret/llm-attention/attention.cpp:241
- /home/eoseret/llm-attention/attention.cpp:241
VPEXTRQ: 4 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	30
nb uops	39
loop length	170
used x86 registers	12
used mmx registers	0
used xmm registers	2
used ymm registers	7
used zmm registers	0
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.88 cycles
front end	4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	2.75	2.75	2.75	2.75	4.50	4.50	4.50	4.50	8.00	8.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	2.75	2.75	2.75	2.75	4.50	4.50	4.50	4.50	8.00	8.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.88
Dispatch	8.00
Data deps.	1.00
Overall L1	8.00

Vectorization ratios

INT

all	50%
load	100%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	38%
load	100%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	25%
load	25%
store	6%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	21%
load	25%
store	6%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

1% of peak load performance is reached (5.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 5880

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VPMULLQ %YMM0,%YMM5,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM0,%YMM6,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM3,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM3,%YMM6,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM4,%YMM7,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM4,%YMM8,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPEXTRQ $0x1,%XMM7,%R12	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM7,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM8,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM7,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM7,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM8,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVDQU 0x10(%R10,%R13,4),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM7,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM7,%R11	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVDQU (%R10,%R13,4),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
ADD $0x8,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVD %XMM7,(%RDI,%RDX,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	8	0.50	scal (6.3%)
VEXTRACTPS $0x1,%XMM7,(%RDI,%R12,4)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (6.3%)
VEXTRACTPS $0x2,%XMM7,(%RDI,%R9,4)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (6.3%)
VEXTRACTPS $0x3,%XMM7,(%RDI,%RSI,4)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (6.3%)
MOV 0x80(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVD %XMM8,(%RDI,%RAX,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	8	0.50	scal (6.3%)
VEXTRACTPS $0x1,%XMM8,(%RDI,%RCX,4)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (6.3%)
VEXTRACTPS $0x2,%XMM8,(%RDI,%R8,4)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (6.3%)
VEXTRACTPS $0x3,%XMM8,(%RDI,%R11,4)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (6.3%)
CMP %R13,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 5880 <main+0x1be0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code