| Loop Id: 38 | Module: attention-avx512 | Source: attention.cpp:55-56 | Coverage: 0.05% |
|---|
| Loop Id: 38 | Module: attention-avx512 | Source: attention.cpp:55-56 | Coverage: 0.05% |
|---|
0x6730 VMOVUPS (%RCX,%RSI,4),%XMM0 [3] |
0x6735 MOV %RSI,0x20(%RSP) [1] |
0x673a VSUBPS 0xa0(%RSP),%XMM0,%XMM0 [1] |
0x6743 VMOVAPS %XMM0,0xc0(%RSP) [1] |
0x674c VZEROUPPER |
0x674f CALL 7170 <@plt_start@+0x20> |
0x6754 VMOVAPS %XMM0,0x60(%RSP) [1] |
0x675a VMOVSHDUP 0xc0(%RSP),%XMM0 [1] |
0x6763 CALL 7170 <@plt_start@+0x20> |
0x6768 VMOVAPS 0x60(%RSP),%XMM1 [1] |
0x676e VINSERTPS $0x10,%XMM0,%XMM1,%XMM0 |
0x6774 VMOVAPS %XMM0,0x60(%RSP) [1] |
0x677a VPERMILPD $0x1,0xc0(%RSP),%XMM0 [1] |
0x6785 CALL 7170 <@plt_start@+0x20> |
0x678a VMOVAPS 0x60(%RSP),%XMM1 [1] |
0x6790 VINSERTPS $0x20,%XMM0,%XMM1,%XMM0 |
0x6796 VMOVAPS %XMM0,0x60(%RSP) [1] |
0x679c VPERMILPS $-0x1,0xc0(%RSP),%XMM0 [1] |
0x67a7 CALL 7170 <@plt_start@+0x20> |
0x67ac VMOVAPS 0x60(%RSP),%XMM1 [1] |
0x67b2 MOV 0x20(%RSP),%RSI [1] |
0x67b7 MOV 0x1a0(%RSP),%RDX [1] |
0x67bf MOV 0x18(%RSP),%RCX [1] |
0x67c4 VINSERTPS $0x30,%XMM0,%XMM1,%XMM0 |
0x67ca VDIVPS 0x220(%RSP),%XMM0,%XMM0 [1] |
0x67d3 VMOVUPS %XMM0,(%RDX,%RSI,4) [2] |
0x67d8 ADD $0x4,%RSI |
0x67dc CMP %RSI,0x180(%RSP) [1] |
0x67e4 JNE 6730 |
/home/eoseret/llm-attention/attention.cpp: 55 - 56 |
-------------------------------------------------------------------------------- |
55: for (int idx = 0; idx <= row; ++idx) //vectorised |
56: P[row * N + idx] = expf(S_row[idx] - max_val) / sum; |
| Coverage (%) | Name | Source Location | Module |
|---|
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.44 |
| CQA speedup if FP arith vectorized | 1.35 |
| CQA speedup if fully vectorized | 5.75 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.44 |
| Bottlenecks | P6, P7, P8, P9, |
| Function | main |
| Source | attention.cpp:55-56 |
| Source loop unroll info | unrolled by 8 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | intermediate |
| Unroll factor | 4 |
| CQA cycles | 5.75 |
| CQA cycles if no scalar integer | 4.00 |
| CQA cycles if FP arith vectorized | 4.25 |
| CQA cycles if fully vectorized | 1.00 |
| Front-end cycles | 4.00 |
| P0 cycles | 0.33 |
| P1 cycles | 0.33 |
| P2 cycles | 0.33 |
| P3 cycles | 1.67 |
| P4 cycles | 1.67 |
| P5 cycles | 1.67 |
| P6 cycles | 5.75 |
| P7 cycles | 5.75 |
| P8 cycles | 5.75 |
| P9 cycles | 5.75 |
| P10 cycles | 1.75 |
| P11 cycles | 1.75 |
| P12 cycles | 1.75 |
| P13 cycles | 1.75 |
| P14 cycles | 2.50 |
| P15 cycles | 2.50 |
| DIV/SQRT cycles | 2.50 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 29.00 |
| Nb uops | 32.00 |
| Nb loads | 13.00 |
| Nb stores | 6.00 |
| Nb stack references | 8.00 |
| FLOP/cycle | 1.39 |
| Nb FLOP add-sub | 4.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 4.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 45.91 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 176.00 |
| Bytes stored | 88.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 2.00 |
| Vectorization ratio all | 78.95 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 83.33 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | 50.00 |
| Vector-efficiency ratio all | 20.72 |
| Vector-efficiency ratio load | 23.61 |
| Vector-efficiency ratio store | 22.92 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 25.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | 25.00 |
| Vector-efficiency ratio other | 15.63 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.44 |
| CQA speedup if FP arith vectorized | 1.35 |
| CQA speedup if fully vectorized | 5.75 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.44 |
| Bottlenecks | P6, P7, P8, P9, |
| Function | main |
| Source | attention.cpp:55-56 |
| Source loop unroll info | unrolled by 8 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | intermediate |
| Unroll factor | 4 |
| CQA cycles | 5.75 |
| CQA cycles if no scalar integer | 4.00 |
| CQA cycles if FP arith vectorized | 4.25 |
| CQA cycles if fully vectorized | 1.00 |
| Front-end cycles | 4.00 |
| P0 cycles | 0.33 |
| P1 cycles | 0.33 |
| P2 cycles | 0.33 |
| P3 cycles | 1.67 |
| P4 cycles | 1.67 |
| P5 cycles | 1.67 |
| P6 cycles | 5.75 |
| P7 cycles | 5.75 |
| P8 cycles | 5.75 |
| P9 cycles | 5.75 |
| P10 cycles | 1.75 |
| P11 cycles | 1.75 |
| P12 cycles | 1.75 |
| P13 cycles | 1.75 |
| P14 cycles | 2.50 |
| P15 cycles | 2.50 |
| DIV/SQRT cycles | 2.50 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 29.00 |
| Nb uops | 32.00 |
| Nb loads | 13.00 |
| Nb stores | 6.00 |
| Nb stack references | 8.00 |
| FLOP/cycle | 1.39 |
| Nb FLOP add-sub | 4.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 4.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 45.91 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 176.00 |
| Bytes stored | 88.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 2.00 |
| Vectorization ratio all | 78.95 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 83.33 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | 50.00 |
| Vector-efficiency ratio all | 20.72 |
| Vector-efficiency ratio load | 23.61 |
| Vector-efficiency ratio store | 22.92 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 25.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | 25.00 |
| Vector-efficiency ratio other | 15.63 |
| Path / |
| Function | main |
| Source file and lines | attention.cpp:55-56 |
| Module | attention-avx512 |
| nb instructions | 29 |
| nb uops | 32 |
| loop length | 186 |
| used x86 registers | 4 |
| used mmx registers | 0 |
| used xmm registers | 2 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 8 |
| micro-operation queue | 4.00 cycles |
| front end | 4.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.33 | 0.33 | 0.33 | 1.67 | 1.67 | 1.67 | 5.75 | 5.75 | 5.75 | 5.75 | 1.75 | 1.75 | 1.75 | 1.75 | 2.50 | 2.50 |
| cycles | 0.33 | 0.33 | 0.33 | 1.67 | 1.67 | 1.67 | 5.75 | 5.75 | 5.75 | 5.75 | 1.75 | 1.75 | 1.75 | 1.75 | 2.50 | 2.50 |
| Cycles executing div or sqrt instructions | 2.50 |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 4.00 |
| Dispatch | 5.75 |
| DIV/SQRT | 2.50 |
| Data deps. | 0.00 |
| Overall L1 | 5.75 |
| all | 50% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 100% |
| all | 82% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 100% |
| other | 40% |
| all | 78% |
| load | 100% |
| store | 83% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 100% |
| other | 50% |
| all | 18% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 25% |
| all | 20% |
| load | 23% |
| store | 25% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 25% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 25% |
| other | 13% |
| all | 20% |
| load | 23% |
| store | 22% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 25% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 25% |
| other | 15% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPS (%RCX,%RSI,4),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| MOV %RSI,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VSUBPS 0xa0(%RSP),%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | vect (25.0%) |
| VMOVAPS %XMM0,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 4 | 0.50 | vect (25.0%) |
| VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | vect (25.0%) |
| CALL 7170 <@plt_start@+0x20> | 2 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| VMOVAPS %XMM0,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 4 | 0.50 | vect (25.0%) |
| VMOVSHDUP 0xc0(%RSP),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (12.5%) |
| CALL 7170 <@plt_start@+0x20> | 2 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| VMOVAPS 0x60(%RSP),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| VINSERTPS $0x10,%XMM0,%XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
| VMOVAPS %XMM0,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 4 | 0.50 | vect (25.0%) |
| VPERMILPD $0x1,0xc0(%RSP),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| CALL 7170 <@plt_start@+0x20> | 2 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| VMOVAPS 0x60(%RSP),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| VINSERTPS $0x20,%XMM0,%XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
| VMOVAPS %XMM0,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 4 | 0.50 | vect (25.0%) |
| VPERMILPS $-0x1,0xc0(%RSP),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| CALL 7170 <@plt_start@+0x20> | 2 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| VMOVAPS 0x60(%RSP),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| MOV 0x20(%RSP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| MOV 0x1a0(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| MOV 0x18(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| VINSERTPS $0x30,%XMM0,%XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
| VDIVPS 0x220(%RSP),%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 10 | 2.50 | vect (25.0%) |
| VMOVUPS %XMM0,(%RDX,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 4 | 0.50 | vect (25.0%) |
| ADD $0x4,%RSI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP %RSI,0x180(%RSP) | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| JNE 6730 <main+0x2a90> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33-1 | N/A |
| Function | main |
| Source file and lines | attention.cpp:55-56 |
| Module | attention-avx512 |
| nb instructions | 29 |
| nb uops | 32 |
| loop length | 186 |
| used x86 registers | 4 |
| used mmx registers | 0 |
| used xmm registers | 2 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 8 |
| micro-operation queue | 4.00 cycles |
| front end | 4.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.33 | 0.33 | 0.33 | 1.67 | 1.67 | 1.67 | 5.75 | 5.75 | 5.75 | 5.75 | 1.75 | 1.75 | 1.75 | 1.75 | 2.50 | 2.50 |
| cycles | 0.33 | 0.33 | 0.33 | 1.67 | 1.67 | 1.67 | 5.75 | 5.75 | 5.75 | 5.75 | 1.75 | 1.75 | 1.75 | 1.75 | 2.50 | 2.50 |
| Cycles executing div or sqrt instructions | 2.50 |
| Longest recurrence chain latency (RecMII) | 0.00 |
| Front-end | 4.00 |
| Dispatch | 5.75 |
| DIV/SQRT | 2.50 |
| Data deps. | 0.00 |
| Overall L1 | 5.75 |
| all | 50% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 100% |
| all | 82% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 100% |
| other | 40% |
| all | 78% |
| load | 100% |
| store | 83% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 100% |
| other | 50% |
| all | 18% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 25% |
| all | 20% |
| load | 23% |
| store | 25% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 25% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 25% |
| other | 13% |
| all | 20% |
| load | 23% |
| store | 22% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 25% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 25% |
| other | 15% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPS (%RCX,%RSI,4),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| MOV %RSI,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VSUBPS 0xa0(%RSP),%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 2 | 0.50 | vect (25.0%) |
| VMOVAPS %XMM0,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 4 | 0.50 | vect (25.0%) |
| VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | vect (25.0%) |
| CALL 7170 <@plt_start@+0x20> | 2 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| VMOVAPS %XMM0,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 4 | 0.50 | vect (25.0%) |
| VMOVSHDUP 0xc0(%RSP),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | vect (12.5%) |
| CALL 7170 <@plt_start@+0x20> | 2 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| VMOVAPS 0x60(%RSP),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| VINSERTPS $0x10,%XMM0,%XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
| VMOVAPS %XMM0,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 4 | 0.50 | vect (25.0%) |
| VPERMILPD $0x1,0xc0(%RSP),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| CALL 7170 <@plt_start@+0x20> | 2 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| VMOVAPS 0x60(%RSP),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| VINSERTPS $0x20,%XMM0,%XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
| VMOVAPS %XMM0,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 4 | 0.50 | vect (25.0%) |
| VPERMILPS $-0x1,0xc0(%RSP),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.50 | vect (25.0%) |
| CALL 7170 <@plt_start@+0x20> | 2 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| VMOVAPS 0x60(%RSP),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (25.0%) |
| MOV 0x20(%RSP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| MOV 0x1a0(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| MOV 0x18(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| VINSERTPS $0x30,%XMM0,%XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1 | 0.25 | scal (6.3%) |
| VDIVPS 0x220(%RSP),%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 10 | 2.50 | vect (25.0%) |
| VMOVUPS %XMM0,(%RDX,%RSI,4) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 4 | 0.50 | vect (25.0%) |
| ADD $0x4,%RSI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP %RSI,0x180(%RSP) | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| JNE 6730 <main+0x2a90> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33-1 | N/A |
