OV - attention-avx512 - Loop 34

	Loop Id: 34	Module: attention-avx512	Source: attention.cpp:52-53	Coverage: 0.05%

0x6670 VMOVSS	(%R13,%RAX,4),%XMM0    [2]

0x6677 MOV	%R13,%R12

0x667a VMOVAPS	%XMM2,0x80(%RSP)    [1]

0x6683 MOV	%RAX,%R13

0x6686 VSUBSS	%XMM1,%XMM0,%XMM0

0x668a VZEROUPPER

0x668d CALL	7170 <@plt_start@+0x20>

0x6692 VMOVAPS	0x80(%RSP),%XMM2    [1]

0x669b VMOVAPS	0x160(%RSP),%XMM1    [1]

0x66a4 MOV	%R13,%RAX

0x66a7 MOV	%R12,%R13

0x66aa MOV	0x1e0(%RSP),%R12    [1]

0x66b2 INC	%RAX

0x66b5 VADDSS	%XMM2,%XMM0,%XMM2

0x66b9 CMP	%RAX,%R12

0x66bc JNE	6670

/home/eoseret/llm-attention/attention.cpp: 52 - 53

--------------------------------------------------------------------------------

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.33
CQA speedup if FP arith vectorized	1.94
CQA speedup if fully vectorized	8.53
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:52-53
Source loop unroll info	unrolled by 32
Source loop unroll confidence level	max
Unroll/vectorization loop type	peel/tail
Unroll factor	1
CQA cycles	2.00
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.03
CQA cycles if fully vectorized	0.23
Front-end cycles	2.00
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.67
P4 cycles	0.67
P5 cycles	0.67
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	16.00
Nb loads	4.00
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	1.00
Nb FLOP add-sub	2.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.00
Bytes prefetched	0.00
Bytes loaded	44.00
Bytes stored	16.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	57.14
Vectorization ratio load	66.67
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	16.96
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.33
CQA speedup if FP arith vectorized	1.94
CQA speedup if fully vectorized	8.53
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:52-53
Source loop unroll info	unrolled by 32
Source loop unroll confidence level	max
Unroll/vectorization loop type	peel/tail
Unroll factor	1
CQA cycles	2.00
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.03
CQA cycles if fully vectorized	0.23
Front-end cycles	2.00
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.67
P4 cycles	0.67
P5 cycles	0.67
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	16.00
Nb loads	4.00
Nb stores	1.00
Nb stack references	3.00
FLOP/cycle	1.00
Nb FLOP add-sub	2.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.00
Bytes prefetched	0.00
Bytes loaded	44.00
Bytes stored	16.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	57.14
Vectorization ratio load	66.67
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	16.96
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:52-53
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:52-53.

It is peel/tail loop of related source loop which is unrolled by 32 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.00 to 1.50 cycles (1.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is partially vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions).

Details

57% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

66% of SSE/AVX loads are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary loop is loading 44 bytes (11 single precision FP elements). The binary loop is storing 16 bytes (4 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	16
nb uops	16
loop length	78
used x86 registers	4
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.00 cycles
front end	2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.67	0.67	0.67	1.50	1.50	1.50	1.50	0.00	0.00	1.00	1.00	0.50	0.50
cycles	0.33	0.33	0.33	0.67	0.67	0.67	1.50	1.50	1.50	1.50	0.00	0.00	1.00	1.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.00
Dispatch	1.50
Data deps.	1.00
Overall L1	2.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	50%
load	66%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	57%
load	66%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	15%
load	18%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	16%
load	18%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

8% of peak load performance is reached (22.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.00 to 1.50 cycles (1.33x speedup).

ASM code

In the binary file, the address of the loop is: 6670

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVSS (%R13,%RAX,4),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
MOV %R13,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPS %XMM2,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VSUBSS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (6.3%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 7170 <@plt_start@+0x20>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
VMOVAPS 0x80(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPS 0x160(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1e0(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDSS %XMM2,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (6.3%)
CMP %RAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 6670 <main+0x29d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A

Function	main
Source file and lines	attention.cpp:52-53
Module	attention-avx512

The loop is defined in /home/eoseret/llm-attention/attention.cpp:52-53.

It is peel/tail loop of related source loop which is unrolled by 32 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.00 to 1.50 cycles (1.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Unrolling/vectorization cost

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is partially vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions).

Details

57% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

66% of SSE/AVX loads are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:53

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary loop is loading 44 bytes (11 single precision FP elements). The binary loop is storing 16 bytes (4 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	16
nb uops	16
loop length	78
used x86 registers	4
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.00 cycles
front end	2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.67	0.67	0.67	1.50	1.50	1.50	1.50	0.00	0.00	1.00	1.00	0.50	0.50
cycles	0.33	0.33	0.33	0.67	0.67	0.67	1.50	1.50	1.50	1.50	0.00	0.00	1.00	1.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.00
Dispatch	1.50
Data deps.	1.00
Overall L1	2.00

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	50%
load	66%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	57%
load	66%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	15%
load	18%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	16%
load	18%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

8% of peak load performance is reached (22.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 6670

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVSS (%R13,%RAX,4),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
MOV %R13,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPS %XMM2,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VSUBSS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (6.3%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 7170 <@plt_start@+0x20>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
VMOVAPS 0x80(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPS 0x160(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (25.0%)
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1e0(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDSS %XMM2,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (6.3%)
CMP %RAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 6670 <main+0x29d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-1	N/A

Report Configuration

Code clean check

Workaround

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code