| Loop Id: 80 | Module: attention-aocc-znver5-512 | Source: random.tcc:401-3367 [...] | Coverage: 0.10% |
|---|
| Loop Id: 80 | Module: attention-aocc-znver5-512 | Source: random.tcc:401-3367 [...] | Coverage: 0.10% |
|---|
0x51a0 MOV %R12,%RCX |
0x51a3 INC %R12 |
0x51a6 MOV $0x200b,%EDX |
0x51ab MOV %R12,0x18f8(%RSP) |
0x51b3 MOV 0x578(%RSP,%RCX,8),%RCX |
0x51bb BEXTR %RDX,%RCX,%RDX |
0x51c0 XOR %RCX,%RDX |
0x51c3 MOV %EDX,%ECX |
0x51c5 SAL $0x7,%ECX |
0x51c8 AND $-0x62d3a980,%ECX |
0x51ce XOR %RDX,%RCX |
0x51d1 MOV %ECX,%EDX |
0x51d3 SAL $0xf,%EDX |
0x51d6 AND $-0x103a0000,%EDX |
0x51dc XOR %RCX,%RDX |
0x51df MOV %RDX,%RCX |
0x51e2 SHR $0x12,%RCX |
0x51e6 XOR %RDX,%RCX |
0x51e9 DEC %R9 |
0x51ec VCVTUSI2SS %RCX,%XMM5,%XMM2 |
0x51f2 VFMADD231SS %XMM2,%XMM1,%XMM0 |
0x51f7 VMULSS -0x435f(%RIP),%XMM1,%XMM1 |
0x51ff JE 5410 |
0x5205 CMP $0x270,%R12 |
0x520c JB 51a0 |
0x520e VPBROADCASTQ %RSI,%ZMM2 |
0x5214 XOR %ECX,%ECX |
0x5216 NOPW %CS:(%RAX,%RAX,1) |
(81) 0x5220 VMOVDQA64 %ZMM2,%ZMM3 |
(81) 0x5226 VMOVDQU64 0x580(%RSP,%RCX,8),%ZMM2 |
(81) 0x522e VPANDQ -0x4378(%RIP){1to8},%ZMM2,%ZMM4 |
(81) 0x5238 VPTESTMQ -0x4362(%RIP){1to0},%ZMM2,%K1 |
(81) 0x5242 VALIGNQ $0x7,%ZMM3,%ZMM2,%ZMM3 |
(81) 0x5249 VPTERNLOGQ $-0x8,-0x436c(%RIP){1to8},%ZMM3,%ZMM4 |
(81) 0x5254 VPSRLQ $0x1,%ZMM4,%ZMM3 |
(81) 0x525b VPXORQ 0x11e0(%RSP,%RCX,8),%ZMM3,%ZMM3 |
(81) 0x5266 VPXORQ -0x4380(%RIP){1to8},%ZMM3,%ZMM3{%K1} |
(81) 0x5270 VMOVDQU64 %ZMM3,0x578(%RSP,%RCX,8) |
(81) 0x527b ADD $0x8,%RCX |
(81) 0x527f CMP $0xe0,%RCX |
(81) 0x5286 JNE 5220 |
0x5288 MOV 0xc80(%RSP),%RDX |
0x5290 VEXTRACTI32X4 $0x3,%ZMM2,%XMM2 |
0x5297 MOV 0xc88(%RSP),%RCX |
0x529f MOV $-0x66f74f21,%R8D |
0x52a5 VPEXTRQ $0x1,%XMM2,%RSI |
0x52ab AND $-0x80000000,%RSI |
0x52b2 MOV %EDX,%EDI |
0x52b4 AND $0x7ffffffe,%EDI |
0x52ba OR %RSI,%RDI |
0x52bd MOV %EDX,%ESI |
0x52bf AND $0x1,%ESI |
0x52c2 AND $-0x80000000,%RDX |
0x52c9 SHR $0x1,%RDI |
0x52cc XOR 0x18e0(%RSP),%RDI |
0x52d4 NEG %ESI |
0x52d6 AND %R8D,%ESI |
0x52d9 XOR %RDI,%RSI |
0x52dc MOV $-0x66f74f21,%EDI |
0x52e1 MOV %RSI,0xc78(%RSP) |
0x52e9 MOV %ECX,%ESI |
0x52eb AND $0x7ffffffe,%ESI |
0x52f1 OR %RDX,%RSI |
0x52f4 MOV %ECX,%EDX |
0x52f6 AND $0x1,%EDX |
0x52f9 AND $-0x80000000,%RCX |
0x5300 SHR $0x1,%RSI |
0x5303 XOR 0x18e8(%RSP),%RSI |
0x530b NEG %EDX |
0x530d AND %R8D,%EDX |
0x5310 XOR %RSI,%RDX |
0x5313 MOV %RDX,0xc80(%RSP) |
0x531b MOV 0xc90(%RSP),%RDX |
0x5323 MOV %EDX,%ESI |
0x5325 VPBROADCASTQ %RDX,%XMM2 |
0x532b AND $0x7ffffffe,%EDX |
0x5331 AND $0x1,%ESI |
0x5334 OR %RCX,%RDX |
0x5337 NEG %ESI |
0x5339 MOV $0xe4,%ECX |
0x533e SHR $0x1,%RDX |
0x5341 XOR 0x18f0(%RSP),%RDX |
0x5349 AND %R8D,%ESI |
0x534c XOR %RDX,%RSI |
0x534f MOV %RSI,0xc88(%RSP) |
0x5357 NOPW (%RAX,%RAX,1) |
(82) 0x5360 VMOVDQU 0x578(%RSP,%RCX,8),%XMM3 |
(82) 0x5369 VPANDQ -0x44b3(%RIP){1to2},%XMM3,%XMM4 |
(82) 0x5373 VPTESTMQ -0x449d(%RIP){1to0},%XMM3,%K1 |
(82) 0x537d VPALIGNR $0x8,%XMM2,%XMM3,%XMM2 |
(82) 0x5383 VPTERNLOGQ $-0x8,-0x44a6(%RIP){1to2},%XMM2,%XMM4 |
(82) 0x538e VPSRLQ $0x1,%XMM4,%XMM2 |
(82) 0x5393 VPXOR -0x1a8(%RSP,%RCX,8),%XMM2,%XMM2 |
(82) 0x539c VPXORQ -0x44b6(%RIP){1to2},%XMM2,%XMM2{%K1} |
(82) 0x53a6 VMOVDQU %XMM2,0x570(%RSP,%RCX,8) |
(82) 0x53af ADD $0x2,%RCX |
(82) 0x53b3 VMOVDQA %XMM3,%XMM2 |
(82) 0x53b7 CMP $0x270,%RCX |
(82) 0x53be JNE 5360 |
0x53c0 MOV 0x18f0(%RSP),%RCX |
0x53c8 MOV 0x578(%RSP),%RSI |
0x53d0 MOV $-0x80000000,%RDX |
0x53d7 XOR %R12D,%R12D |
0x53da AND %RDX,%RCX |
0x53dd MOV %ESI,%EDX |
0x53df AND $0x7ffffffe,%EDX |
0x53e5 OR %RCX,%RDX |
0x53e8 MOV %ESI,%ECX |
0x53ea AND $0x1,%ECX |
0x53ed SHR $0x1,%RDX |
0x53f0 XOR 0x11d8(%RSP),%RDX |
0x53f8 NEG %ECX |
0x53fa AND %EDI,%ECX |
0x53fc XOR %RDX,%RCX |
0x53ff MOV %RCX,0x18f0(%RSP) |
0x5407 JMP 51a0 |
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 401 - 3367 |
-------------------------------------------------------------------------------- |
401: for (size_t __k = 0; __k < (__n - __m); ++__k) |
402: { |
403: _UIntType __y = ((_M_x[__k] & __upper_mask) |
404: | (_M_x[__k + 1] & __lower_mask)); |
405: _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1) |
406: ^ ((__y & 0x01) ? __a : 0)); |
[...] |
412: | (_M_x[__k + 1] & __lower_mask)); |
413: _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1) |
414: ^ ((__y & 0x01) ? __a : 0)); |
415: } |
416: |
417: _UIntType __y = ((_M_x[__n - 1] & __upper_mask) |
418: | (_M_x[0] & __lower_mask)); |
419: _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1) |
420: ^ ((__y & 0x01) ? __a : 0)); |
[...] |
455: if (_M_p >= state_size) |
456: _M_gen_rand(); |
457: |
458: // Calculate o(x(i)). |
459: result_type __z = _M_x[_M_p++]; |
460: __z ^= (__z >> __u) & __d; |
461: __z ^= (__z << __s) & __b; |
462: __z ^= (__z << __t) & __c; |
463: __z ^= (__z >> __l); |
[...] |
3364: for (size_t __k = __m; __k != 0; --__k) |
3365: { |
3366: __sum += _RealType(__urng() - __urng.min()) * __tmp; |
3367: __tmp *= __r; |
| Coverage (%) | Name | Source Location | Module |
|---|
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.97 |
| CQA speedup if FP arith vectorized | 2.21 |
| CQA speedup if fully vectorized | 12.51 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.25 |
| Bottlenecks | |
| Function | main |
| Source | random.tcc:401-406,random.tcc:413-413,random.tcc:417-420,random.tcc:455-455,random.tcc:459-463,random.tcc:3364-3367 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 7.88 |
| CQA cycles if no scalar integer | 4.00 |
| CQA cycles if FP arith vectorized | 3.57 |
| CQA cycles if fully vectorized | 0.63 |
| Front-end cycles | 7.44 |
| P0 cycles | 6.00 |
| P1 cycles | 6.00 |
| P2 cycles | 6.00 |
| P3 cycles | 6.00 |
| P4 cycles | 6.00 |
| P5 cycles | 6.00 |
| P6 cycles | 2.38 |
| P7 cycles | 2.38 |
| P8 cycles | 2.38 |
| P9 cycles | 2.38 |
| P10 cycles | 1.13 |
| P11 cycles | 1.75 |
| P12 cycles | 1.25 |
| P13 cycles | 0.88 |
| P14 cycles | 0.25 |
| P15 cycles | 0.25 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 4 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 57.50 |
| Nb uops | 59.50 |
| Nb loads | 6.50 |
| Nb stores | 3.00 |
| Nb stack references | 5.50 |
| FLOP/cycle | 0.38 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 7.78 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 48.00 |
| Bytes stored | 24.00 |
| Stride 0 | 2.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 2.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 0.82 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 1.00 |
| Vector-efficiency ratio all | 9.46 |
| Vector-efficiency ratio load | 8.98 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 6.25 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | 6.25 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 9.21 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.94 |
| CQA speedup if FP arith vectorized | 1.94 |
| CQA speedup if fully vectorized | 12.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.24 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | random.tcc:401-406,random.tcc:413-413,random.tcc:417-420,random.tcc:455-455,random.tcc:459-463,random.tcc:3364-3367 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 11.75 |
| CQA cycles if no scalar integer | 4.00 |
| CQA cycles if FP arith vectorized | 6.06 |
| CQA cycles if fully vectorized | 0.98 |
| Front-end cycles | 11.75 |
| P0 cycles | 9.50 |
| P1 cycles | 9.50 |
| P2 cycles | 9.50 |
| P3 cycles | 9.50 |
| P4 cycles | 9.50 |
| P5 cycles | 9.50 |
| P6 cycles | 4.00 |
| P7 cycles | 4.00 |
| P8 cycles | 4.00 |
| P9 cycles | 4.00 |
| P10 cycles | 1.25 |
| P11 cycles | 2.50 |
| P12 cycles | 2.00 |
| P13 cycles | 1.25 |
| P14 cycles | 0.50 |
| P15 cycles | 0.50 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 4 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 90.00 |
| Nb uops | 94.00 |
| Nb loads | 11.00 |
| Nb stores | 5.00 |
| Nb stack references | 10.00 |
| FLOP/cycle | 0.26 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 10.55 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 84.00 |
| Bytes stored | 40.00 |
| Stride 0 | 2.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 2.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 1.64 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 2.00 |
| Vector-efficiency ratio all | 9.84 |
| Vector-efficiency ratio load | 11.72 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 6.25 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | 6.25 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 9.50 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 3.72 |
| CQA speedup if fully vectorized | 14.29 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.28 |
| Bottlenecks | |
| Function | main |
| Source | random.tcc:401-406,random.tcc:413-413,random.tcc:417-420,random.tcc:455-455,random.tcc:459-463,random.tcc:3364-3367 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 4.00 |
| CQA cycles if no scalar integer | 4.00 |
| CQA cycles if FP arith vectorized | 1.07 |
| CQA cycles if fully vectorized | 0.28 |
| Front-end cycles | 3.13 |
| P0 cycles | 2.50 |
| P1 cycles | 2.50 |
| P2 cycles | 2.50 |
| P3 cycles | 2.50 |
| P4 cycles | 2.50 |
| P5 cycles | 2.50 |
| P6 cycles | 0.75 |
| P7 cycles | 0.75 |
| P8 cycles | 0.75 |
| P9 cycles | 0.75 |
| P10 cycles | 1.00 |
| P11 cycles | 1.00 |
| P12 cycles | 0.50 |
| P13 cycles | 0.50 |
| P14 cycles | 0.00 |
| P15 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 4 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 25.00 |
| Nb uops | 25.00 |
| Nb loads | 2.00 |
| Nb stores | 1.00 |
| Nb stack references | 1.00 |
| FLOP/cycle | 0.75 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 5.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 12.00 |
| Bytes stored | 8.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 9.09 |
| Vector-efficiency ratio load | 6.25 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 6.25 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | 6.25 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 8.93 |
| Path / |
| Function | main |
| Source file and lines | random.tcc:401-3367 |
| Module | attention-aocc-znver5-512 |
| nb instructions | 57.50 |
| nb uops | 59.50 |
| loop length | 265 |
| used x86 registers | 7 |
| used mmx registers | 0 |
| used xmm registers | 4 |
| used ymm registers | 0 |
| used zmm registers | 0.50 |
| nb stack references | 5.50 |
| micro-operation queue | 7.44 cycles |
| front end | 7.44 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 6.00 | 6.00 | 6.00 | 6.00 | 6.00 | 6.00 | 2.38 | 2.38 | 2.38 | 2.38 | 1.13 | 1.75 | 1.25 | 0.88 | 0.25 | 0.25 |
| cycles | 6.00 | 6.00 | 6.00 | 6.00 | 6.00 | 6.00 | 2.38 | 2.38 | 2.38 | 2.38 | 1.13 | 1.75 | 1.25 | 0.88 | 0.25 | 0.25 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 4.00 |
| Front-end | 7.44 |
| Dispatch | 6.00 |
| Data deps. | 4.00 |
| Overall L1 | 7.88 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 1% |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 1% |
| all | 9% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 9% |
| all | 6% |
| load | 6% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 6% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 6% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 9% |
| load | 8% |
| store | 12% |
| mul | 6% |
| add-sub | 12% |
| fma | 6% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 9% |
| Function | main |
| Source file and lines | random.tcc:401-3367 |
| Module | attention-aocc-znver5-512 |
| nb instructions | 90 |
| nb uops | 94 |
| loop length | 420 |
| used x86 registers | 9 |
| used mmx registers | 0 |
| used xmm registers | 4 |
| used ymm registers | 0 |
| used zmm registers | 1 |
| nb stack references | 10 |
| micro-operation queue | 11.75 cycles |
| front end | 11.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 9.50 | 9.50 | 9.50 | 9.50 | 9.50 | 9.50 | 4.00 | 4.00 | 4.00 | 4.00 | 1.25 | 2.50 | 2.00 | 1.25 | 0.50 | 0.50 |
| cycles | 9.50 | 9.50 | 9.50 | 9.50 | 9.50 | 9.50 | 4.00 | 4.00 | 4.00 | 4.00 | 1.25 | 2.50 | 2.00 | 1.25 | 0.50 | 0.50 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 4.00 |
| Front-end | 11.75 |
| Dispatch | 9.50 |
| Data deps. | 4.00 |
| Overall L1 | 11.75 |
| all | 1% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 2% |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 1% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 2% |
| all | 9% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 9% |
| all | 6% |
| load | 6% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 6% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 6% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 9% |
| load | 11% |
| store | 12% |
| mul | 6% |
| add-sub | 12% |
| fma | 6% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 9% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV %R12,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.13 | N/A |
| INC %R12 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV $0x200b,%EDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| MOV %R12,0x18f8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| MOV 0x578(%RSP,%RCX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| BEXTR %RDX,%RCX,%RDX | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| XOR %RCX,%RDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.13 | N/A |
| SAL $0x7,%ECX | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| AND $-0x62d3a980,%ECX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| XOR %RDX,%RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV %ECX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.13 | scal (6.3%) |
| SAL $0xf,%EDX | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (6.3%) |
| AND $-0x103a0000,%EDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| XOR %RCX,%RDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| MOV %RDX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.13 | N/A |
| SHR $0x12,%RCX | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| XOR %RDX,%RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| DEC %R9 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| VCVTUSI2SS %RCX,%XMM5,%XMM2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3-9 | 1 | scal (12.5%) |
| VFMADD231SS %XMM2,%XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (6.3%) |
| VMULSS -0x435f(%RIP),%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| JE 5410 <main+0xab0> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33-0.50 | N/A |
| CMP $0x270,%R12 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| JB 51a0 <main+0x840> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33-0.50 | N/A |
| VPBROADCASTQ %RSI,%ZMM2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 1 | scal (12.5%) |
| XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.13 | N/A |
| MOV 0xc80(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (12.5%) |
| VEXTRACTI32X4 $0x3,%ZMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 5 | 0.50 | vect (25.0%) |
| MOV 0xc88(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| MOV $-0x66f74f21,%R8D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| VPEXTRQ $0x1,%XMM2,%RSI | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 7 | 0.50 | scal (12.5%) |
| AND $-0x80000000,%RSI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| MOV %EDX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.13 | scal (6.3%) |
| AND $0x7ffffffe,%EDI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| OR %RSI,%RDI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| MOV %EDX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.13 | scal (6.3%) |
| AND $0x1,%ESI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| AND $-0x80000000,%RDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| SHR $0x1,%RDI | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| XOR 0x18e0(%RSP),%RDI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| NEG %ESI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| AND %R8D,%ESI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| XOR %RDI,%RSI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| MOV $-0x66f74f21,%EDI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| MOV %RSI,0xc78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| MOV %ECX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.13 | scal (6.3%) |
| AND $0x7ffffffe,%ESI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| OR %RDX,%RSI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| MOV %ECX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.13 | scal (6.3%) |
| AND $0x1,%EDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| AND $-0x80000000,%RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| SHR $0x1,%RSI | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| XOR 0x18e8(%RSP),%RSI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| NEG %EDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| AND %R8D,%EDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| XOR %RSI,%RDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| MOV %RDX,0xc80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| MOV 0xc90(%RSP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (12.5%) |
| MOV %EDX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.13 | scal (6.3%) |
| VPBROADCASTQ %RDX,%XMM2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 1 | scal (12.5%) |
| AND $0x7ffffffe,%EDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| AND $0x1,%ESI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| OR %RCX,%RDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| NEG %ESI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| MOV $0xe4,%ECX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| SHR $0x1,%RDX | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| XOR 0x18f0(%RSP),%RDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| AND %R8D,%ESI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| XOR %RDX,%RSI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| MOV %RSI,0xc88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.13 | N/A |
| MOV 0x18f0(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| MOV 0x578(%RSP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (12.5%) |
| MOV $-0x80000000,%RDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| AND %RDX,%RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV %ESI,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.13 | scal (6.3%) |
| AND $0x7ffffffe,%EDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| OR %RCX,%RDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| MOV %ESI,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.13 | N/A |
| AND $0x1,%ECX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| SHR $0x1,%RDX | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (12.5%) |
| XOR 0x11d8(%RSP),%RDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | scal (12.5%) |
| NEG %ECX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| AND %EDI,%ECX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| XOR %RDX,%RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV %RCX,0x18f0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| JMP 51a0 <main+0x840> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| Function | main |
| Source file and lines | random.tcc:401-3367 |
| Module | attention-aocc-znver5-512 |
| nb instructions | 25 |
| nb uops | 25 |
| loop length | 110 |
| used x86 registers | 5 |
| used mmx registers | 0 |
| used xmm registers | 4 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 1 |
| micro-operation queue | 3.13 cycles |
| front end | 3.13 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.50 | 2.50 | 2.50 | 2.50 | 2.50 | 2.50 | 0.75 | 0.75 | 0.75 | 0.75 | 1.00 | 1.00 | 0.50 | 0.50 | 0.00 | 0.00 |
| cycles | 2.50 | 2.50 | 2.50 | 2.50 | 2.50 | 2.50 | 0.75 | 0.75 | 0.75 | 0.75 | 1.00 | 1.00 | 0.50 | 0.50 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 4.00 |
| Front-end | 3.13 |
| Dispatch | 2.50 |
| Data deps. | 4.00 |
| Overall L1 | 4.00 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 9% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 8% |
| all | 6% |
| load | 6% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 6% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 6% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 9% |
| load | 6% |
| store | 12% |
| mul | 6% |
| add-sub | 12% |
| fma | 6% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 8% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV %R12,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.13 | N/A |
| INC %R12 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV $0x200b,%EDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| MOV %R12,0x18f8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| MOV 0x578(%RSP,%RCX,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| BEXTR %RDX,%RCX,%RDX | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| XOR %RCX,%RDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.13 | N/A |
| SAL $0x7,%ECX | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| AND $-0x62d3a980,%ECX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| XOR %RDX,%RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV %ECX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.13 | scal (6.3%) |
| SAL $0xf,%EDX | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | scal (6.3%) |
| AND $-0x103a0000,%EDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| XOR %RCX,%RDX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| MOV %RDX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.13 | N/A |
| SHR $0x12,%RCX | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | N/A |
| XOR %RDX,%RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| DEC %R9 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| VCVTUSI2SS %RCX,%XMM5,%XMM2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3-9 | 1 | scal (12.5%) |
| VFMADD231SS %XMM2,%XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (6.3%) |
| VMULSS -0x435f(%RIP),%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| JE 5410 <main+0xab0> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33-0.50 | N/A |
| CMP $0x270,%R12 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| JB 51a0 <main+0x840> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33-0.50 | N/A |
