OV - attention-aocc-znver5-256 - Loop 62 - attention-aocc-znver5-256

	Loop Id: 62	Module: attention-aocc-znver5-256	Source: random.tcc:401-3367 [...]	Coverage: 0.15%

0x4c60 MOV	0x1710(%RSP),%RCX

0x4c68 MOV	0x398(%RSP),%RSI

0x4c70 MOV	$-0x80000000,%RDX

0x4c77 XOR	%R12D,%R12D

0x4c7a AND	%RDX,%RCX

0x4c7d MOV	%ESI,%EDX

0x4c7f AND	$0x7ffffffe,%EDX

0x4c85 OR	%RCX,%RDX

0x4c88 MOV	%ESI,%ECX

0x4c8a AND	$0x1,%ECX

0x4c8d SHR	$0x1,%RDX

0x4c90 XOR	0xff8(%RSP),%RDX

0x4c98 NEG	%ECX

0x4c9a AND	%EDI,%ECX

0x4c9c XOR	%RDX,%RCX

0x4c9f MOV	%RCX,0x1710(%RSP)

0x4ca7 MOV	%R12,%RCX

0x4caa INC	%R12

0x4cad MOV	$0x200b,%EDX

0x4cb2 MOV	%R12,0x1718(%RSP)

0x4cba MOV	0x398(%RSP,%RCX,8),%RCX

0x4cc2 BEXTR	%RDX,%RCX,%RDX

0x4cc7 XOR	%RCX,%RDX

0x4cca MOV	%EDX,%ECX

0x4ccc SAL	$0x7,%ECX

0x4ccf AND	$-0x62d3a980,%ECX

0x4cd5 XOR	%RDX,%RCX

0x4cd8 MOV	%ECX,%EDX

0x4cda SAL	$0xf,%EDX

0x4cdd AND	$-0x103a0000,%EDX

0x4ce3 XOR	%RCX,%RDX

0x4ce6 MOV	%RDX,%RCX

0x4ce9 SHR	$0x12,%RCX

0x4ced XOR	%RDX,%RCX

0x4cf0 DEC	%RAX

0x4cf3 VCVTUSI2SS	%RCX,%XMM5,%XMM2

0x4cf9 VFMADD231SS	%XMM2,%XMM1,%XMM0

0x4cfe VMULSS	-0x3e66(%RIP),%XMM1,%XMM1

0x4d06 JE	4ec0

0x4d0c CMP	$0x270,%R12

0x4d13 JB	4ca7

0x4d15 VPBROADCASTQ	%RSI,%YMM2

0x4d1b XOR	%ECX,%ECX

0x4d1d NOPL	(%RAX)

  (63) 0x4d20 VMOVDQA	%YMM2,%YMM3

  (63) 0x4d24 VMOVDQU	0x3a0(%RSP,%RCX,8),%YMM2

  (63) 0x4d2d VPANDQ	-0x3e77(%RIP){1to4},%YMM2,%YMM4

  (63) 0x4d37 VPTESTMQ	-0x3e61(%RIP){1to0},%YMM2,%K1

  (63) 0x4d41 VALIGNQ	$0x3,%YMM3,%YMM2,%YMM3

  (63) 0x4d48 VPTERNLOGQ	$-0x8,-0x3e6b(%RIP){1to4},%YMM3,%YMM4

  (63) 0x4d53 VPSRLQ	$0x1,%YMM4,%YMM3

  (63) 0x4d58 VPXOR	0x1000(%RSP,%RCX,8),%YMM3,%YMM3

  (63) 0x4d61 VPXORQ	-0x3e7b(%RIP){1to4},%YMM3,%YMM3{%K1}

  (63) 0x4d6b VMOVDQU	%YMM3,0x398(%RSP,%RCX,8)

  (63) 0x4d74 ADD	$0x4,%RCX

  (63) 0x4d78 CMP	$0xe0,%RCX

  (63) 0x4d7f JNE	4d20

0x4d81 MOV	0xaa0(%RSP),%RDX

0x4d89 VEXTRACTI128	$0x1,%YMM2,%XMM2

0x4d8f MOV	0xaa8(%RSP),%RCX

0x4d97 MOV	$-0x66f74f21,%R8D

0x4d9d VPEXTRQ	$0x1,%XMM2,%RSI

0x4da3 AND	$-0x80000000,%RSI

0x4daa MOV	%EDX,%EDI

0x4dac AND	$0x7ffffffe,%EDI

0x4db2 OR	%RSI,%RDI

0x4db5 MOV	%EDX,%ESI

0x4db7 AND	$0x1,%ESI

0x4dba AND	$-0x80000000,%RDX

0x4dc1 SHR	$0x1,%RDI

0x4dc4 XOR	0x1700(%RSP),%RDI

0x4dcc NEG	%ESI

0x4dce AND	%R8D,%ESI

0x4dd1 XOR	%RDI,%RSI

0x4dd4 MOV	$-0x66f74f21,%EDI

0x4dd9 MOV	%RSI,0xa98(%RSP)

0x4de1 MOV	%ECX,%ESI

0x4de3 AND	$0x7ffffffe,%ESI

0x4de9 OR	%RDX,%RSI

0x4dec MOV	%ECX,%EDX

0x4dee AND	$0x1,%EDX

0x4df1 AND	$-0x80000000,%RCX

0x4df8 SHR	$0x1,%RSI

0x4dfb XOR	0x1708(%RSP),%RSI

0x4e03 NEG	%EDX

0x4e05 AND	%R8D,%EDX

0x4e08 XOR	%RSI,%RDX

0x4e0b MOV	%RDX,0xaa0(%RSP)

0x4e13 MOV	0xab0(%RSP),%RDX

0x4e1b MOV	%EDX,%ESI

0x4e1d VPBROADCASTQ	%RDX,%XMM2

0x4e23 AND	$0x7ffffffe,%EDX

0x4e29 AND	$0x1,%ESI

0x4e2c OR	%RCX,%RDX

0x4e2f NEG	%ESI

0x4e31 MOV	$0xe4,%ECX

0x4e36 SHR	$0x1,%RDX

0x4e39 XOR	0x1710(%RSP),%RDX

0x4e41 AND	%R8D,%ESI

0x4e44 XOR	%RDX,%RSI

0x4e47 MOV	%RSI,0xaa8(%RSP)

0x4e4f NOP

  (64) 0x4e50 VMOVDQU	0x398(%RSP,%RCX,8),%XMM3

  (64) 0x4e59 VPANDQ	-0x3fa3(%RIP){1to2},%XMM3,%XMM4

  (64) 0x4e63 VPTESTMQ	-0x3f8d(%RIP){1to0},%XMM3,%K1

  (64) 0x4e6d VPALIGNR	$0x8,%XMM2,%XMM3,%XMM2

  (64) 0x4e73 VPTERNLOGQ	$-0x8,-0x3f96(%RIP){1to2},%XMM2,%XMM4

  (64) 0x4e7e VPSRLQ	$0x1,%XMM4,%XMM2

  (64) 0x4e83 VPXOR	-0x388(%RSP,%RCX,8),%XMM2,%XMM2

  (64) 0x4e8c VPXORQ	-0x3fa6(%RIP){1to2},%XMM2,%XMM2{%K1}

  (64) 0x4e96 VMOVDQU	%XMM2,0x390(%RSP,%RCX,8)

  (64) 0x4e9f ADD	$0x2,%RCX

  (64) 0x4ea3 VMOVDQA	%XMM3,%XMM2

  (64) 0x4ea7 CMP	$0x270,%RCX

  (64) 0x4eae JNE	4e50

0x4eb0 JMP	4c60

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 401 - 3367

--------------------------------------------------------------------------------

401:       for (size_t __k = 0; __k < (__n - __m); ++__k)

402:         {

403: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

404: 			   | (_M_x[__k + 1] & __lower_mask));

405: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

406: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

412: 			   | (_M_x[__k + 1] & __lower_mask));

413: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

414: 		       ^ ((__y & 0x01) ? __a : 0));

415: 	}

416:

417:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

418: 		       | (_M_x[0] & __lower_mask));

419:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

420: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

455:       if (_M_p >= state_size)

456: 	_M_gen_rand();

457:

458:       // Calculate o(x(i)).

459:       result_type __z = _M_x[_M_p++];

460:       __z ^= (__z >> __u) & __d;

461:       __z ^= (__z << __s) & __b;

462:       __z ^= (__z << __t) & __c;

463:       __z ^= (__z >> __l);

[...]

3364:       for (size_t __k = __m; __k != 0; --__k)

3365: 	{

3366: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3367: 	  __tmp *= __r;

/home/eoseret/llm-attention/attention_v2.cpp: 166 - 166

--------------------------------------------------------------------------------

166:          h_WK[i] = dist(rng);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.97
CQA speedup if FP arith vectorized	2.25
CQA speedup if fully vectorized	12.59
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks
Function	main
Source	random.tcc:401-406,random.tcc:413-413,random.tcc:417-420,random.tcc:455-455,random.tcc:459-463,random.tcc:3364-3367,attention_v2.cpp:166-166
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.88
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	3.51
CQA cycles if fully vectorized	0.63
Front-end cycles	7.44
P0 cycles	6.00
P1 cycles	6.00
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	6.00
P5 cycles	6.00
P6 cycles	2.38
P7 cycles	2.38
P8 cycles	2.38
P9 cycles	2.38
P10 cycles	1.38
P11 cycles	1.50
P12 cycles	1.13
P13 cycles	1.00
P14 cycles	0.25
P15 cycles	0.25
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	57.50
Nb uops	59.50
Nb loads	6.50
Nb stores	3.00
Nb stack references	5.50
FLOP/cycle	0.38
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.78
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	24.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.83
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	1.00
Vector-efficiency ratio all	9.44
Vector-efficiency ratio load	8.98
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	6.25
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.21

Metric	Value
CQA speedup if no scalar integer	2.94
CQA speedup if FP arith vectorized	1.98
CQA speedup if fully vectorized	12.10
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.24
Bottlenecks	micro-operation queue,
Function	main
Source	random.tcc:401-406,random.tcc:413-413,random.tcc:417-420,random.tcc:455-455,random.tcc:459-463,random.tcc:3364-3367,attention_v2.cpp:166-166
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.75
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	5.94
CQA cycles if fully vectorized	0.97
Front-end cycles	11.75
P0 cycles	9.50
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	9.50
P5 cycles	9.50
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	1.75
P11 cycles	2.00
P12 cycles	1.75
P13 cycles	1.50
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	90.00
Nb uops	94.00
Nb loads	11.00
Nb stores	5.00
Nb stack references	10.00
FLOP/cycle	0.26
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.55
Bytes prefetched	0.00
Bytes loaded	84.00
Bytes stored	40.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	1.67
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	2.00
Vector-efficiency ratio all	9.79
Vector-efficiency ratio load	11.72
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	6.25
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	3.72
CQA speedup if fully vectorized	14.29
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.28
Bottlenecks
Function	main
Source	random.tcc:401-406,random.tcc:413-413,random.tcc:417-420,random.tcc:455-455,random.tcc:459-463,random.tcc:3364-3367,attention_v2.cpp:166-166
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	1.07
CQA cycles if fully vectorized	0.28
Front-end cycles	3.13
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	2.50
P6 cycles	0.75
P7 cycles	0.75
P8 cycles	0.75
P9 cycles	0.75
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	25.00
Nb loads	2.00
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	0.75
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.00
Bytes prefetched	0.00
Bytes loaded	12.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.09
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	6.25
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.93

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:401-3367
Module	attention-aocc-znver5-256

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-406,412-420,455-463,3364-3367
/home/eoseret/llm-attention/attention_v2.cpp:166

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 1 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 0 occurrences
VPBROADCASTQ: 0 occurrences
VPEXTRQ: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
2: multiply (1 inside FMA instructions)

The binary loop is loading 48 bytes (12 single precision FP elements). The binary loop is storing 24 bytes (6 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	57.50
nb uops	59.50
loop length	257
used x86 registers	6.50
used mmx registers	0
used xmm registers	4
used ymm registers	0.50
used zmm registers	0
nb stack references	5.50

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	7.44 cycles
front end	7.44 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.00	6.00	6.00	6.00	6.00	6.00	2.38	2.38	2.38	2.38	1.38	1.50	1.13	1.00	0.25	0.25
cycles	6.00	6.00	6.00	6.00	6.00	6.00	2.38	2.38	2.38	2.38	1.38	1.50	1.13	1.00	0.25	0.25

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	7.44
Dispatch	6.00
Data deps.	4.00
Overall L1	7.88

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	1%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	1%

Vector efficiency ratios

INT

all	9%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	8%
store	12%
mul	6%
add-sub	12%
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.88 cycles. At this rate:

1% of peak load performance is reached (5.07 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.70 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	random.tcc:401-3367
Module	attention-aocc-znver5-256

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-406,412-420,455-463,3364-3367
/home/eoseret/llm-attention/attention_v2.cpp:166

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.75 to 4.00 cycles (2.94x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 1 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
VPBROADCASTQ: 2 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401
VPEXTRQ: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
2: multiply (1 inside FMA instructions)

The binary loop is loading 84 bytes (21 single precision FP elements). The binary loop is storing 40 bytes (10 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	90
nb uops	94
loop length	404
used x86 registers	8
used mmx registers	0
used xmm registers	4
used ymm registers	1
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.75 cycles
front end	11.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	9.50	9.50	9.50	9.50	9.50	9.50	4.00	4.00	4.00	4.00	1.75	2.00	1.75	1.50	0.50	0.50
cycles	9.50	9.50	9.50	9.50	9.50	9.50	4.00	4.00	4.00	4.00	1.75	2.00	1.75	1.50	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	11.75
Dispatch	9.50
Data deps.	4.00
Overall L1	11.75

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	2%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	2%

Vector efficiency ratios

INT

all	9%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	11%
store	12%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.75 cycles. At this rate:

2% of peak load performance is reached (7.15 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.75 to 9.50 cycles (1.24x speedup).

ASM code

In the binary file, the address of the loop is: 4d0c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0x1710(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x398(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV $-0x80000000,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
AND $0x7ffffffe,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
OR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %ESI,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
AND $0x1,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
XOR 0xff8(%RSP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
NEG %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %EDI,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,0x1710(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
INC %R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x200b,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R12,0x1718(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x398(%RSP,%RCX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
BEXTR %RDX,%RCX,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
XOR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %EDX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
SAL $0x7,%ECX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
AND $-0x62d3a980,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
SAL $0xf,%EDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
AND $-0x103a0000,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
SHR $0x12,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
XOR %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VCVTUSI2SS %RCX,%XMM5,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3-9	1	scal (12.5%)
VFMADD231SS %XMM2,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (6.3%)
VMULSS -0x3e66(%RIP),%XMM1,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (6.3%)
JE 4ec0 <main+0x12b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
CMP $0x270,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JB 4ca7 <main+0x1097>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VPBROADCASTQ %RSI,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	1	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0xaa0(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VEXTRACTI128 $0x1,%YMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	vect (25.0%)
MOV 0xaa8(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV $-0x66f74f21,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
VPEXTRQ $0x1,%XMM2,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	7	0.50	scal (12.5%)
AND $-0x80000000,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %EDX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
AND $0x7ffffffe,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
OR %RSI,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
AND $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $-0x80000000,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x1,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
XOR 0x1700(%RSP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
NEG %ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND %R8D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RDI,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV $-0x66f74f21,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RSI,0xa98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %ECX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
AND $0x7ffffffe,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
OR %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
AND $0x1,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $-0x80000000,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
XOR 0x1708(%RSP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
NEG %EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND %R8D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RSI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,0xaa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xab0(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
VPBROADCASTQ %RDX,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	1	scal (12.5%)
AND $0x7ffffffe,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x1,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
OR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
NEG %ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xe4,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
XOR 0x1710(%RSP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
AND %R8D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RSI,0xaa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 4c60 <main+0x1050>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	random.tcc:401-3367
Module	attention-aocc-znver5-256

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-406,412-420,455-463,3364-3367
/home/eoseret/llm-attention/attention_v2.cpp:166

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.00 to 0.28 cycles (14.29x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 1 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
2: multiply (1 inside FMA instructions)

The binary loop is loading 12 bytes (3 single precision FP elements). The binary loop is storing 8 bytes (2 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	25
nb uops	25
loop length	110
used x86 registers	5
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.13 cycles
front end	3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.50	2.50	2.50	2.50	2.50	2.50	0.75	0.75	0.75	0.75	1.00	1.00	0.50	0.50	0.00	0.00
cycles	2.50	2.50	2.50	2.50	2.50	2.50	0.75	0.75	0.75	0.75	1.00	1.00	0.50	0.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	3.13
Dispatch	2.50
Data deps.	4.00
Overall L1	4.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	6%
store	12%
mul	6%
add-sub	12%
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

1% of peak load performance is reached (3.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4d0c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
MOV %R12,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
INC %R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x200b,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R12,0x1718(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x398(%RSP,%RCX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
BEXTR %RDX,%RCX,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
XOR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %EDX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
SAL $0x7,%ECX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
AND $-0x62d3a980,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
SAL $0xf,%EDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
AND $-0x103a0000,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
SHR $0x12,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
XOR %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VCVTUSI2SS %RCX,%XMM5,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3-9	1	scal (12.5%)
VFMADD231SS %XMM2,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (6.3%)
VMULSS -0x3e66(%RIP),%XMM1,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (6.3%)
JE 4ec0 <main+0x12b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
CMP $0x270,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JB 4ca7 <main+0x1097>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A

Report Configuration

Vectorization

Details

Workaround

512-bits vectorization

Workaround

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code