OV - attention-aocc-znver5-256 - Loop 59 - attention-aocc-znver5-256

	Loop Id: 59	Module: attention-aocc-znver5-256	Source: attention_v2.cpp:26-33	Coverage: 0.51%

0x5040 MOV	0xc8(%RSP),%R9

0x5048 VCVTSD2SS	%XMM0,%XMM0,%XMM0

0x504c LEA	(%RSI,%RDI,1),%R8D

0x5050 INC	%RDI

0x5053 VMOVSS	%XMM0,(%R9,%R8,4)

0x5059 CMP	%R13,%RDI

0x505c JE	4ff0

0x505e VXORPS	%XMM0,%XMM0,%XMM0

0x5062 CMP	$0x10,%R13D

0x5066 JB	507c

0x5068 MOV	%EDI,%R8D

0x506b ADD	0xd8(%RSP),%R8D

0x5073 SETB	%R8B

0x5077 OR	%DL,%R8B

0x507a JE	50c0

0x507c XOR	%R8D,%R8D

0x507f MOV	%R14,%R9

0x5082 IMUL	%R8,%R9

0x5086 ADD	%RDI,%R9

0x5089 NOPL	(%RAX)

  (28) 0x5090 LEA	(%RAX,%R8,1),%R10D

  (28) 0x5094 INC	%R8

  (28) 0x5097 VMOVSS	(%RBX,%R10,4),%XMM1

  (28) 0x509d MOV	%R9D,%R10D

  (28) 0x50a0 VMOVSS	(%R11,%R10,4),%XMM2

  (28) 0x50a6 ADD	%R14,%R9

  (28) 0x50a9 VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (28) 0x50ad VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (28) 0x50b1 VFMADD231SD	%XMM2,%XMM1,%XMM0

  (28) 0x50b6 CMP	%R8,%R13

  (28) 0x50b9 JNE	5090

0x50bb JMP	5040

0x50c0 MOV	0x1a8(%RSP),%R10

0x50c8 VXORPS	%XMM0,%XMM0,%XMM0

0x50cc VXORPS	%XMM1,%XMM1,%XMM1

0x50d0 VXORPS	%XMM2,%XMM2,%XMM2

0x50d4 VPXOR	%XMM3,%XMM3,%XMM3

0x50d8 XOR	%R8D,%R8D

0x50db NOPL	(%RAX,%RAX,1)

  (60) 0x50e0 LEA	(%RAX,%R8,1),%R9D

  (60) 0x50e4 VCVTPS2PD	(%RBX,%R9,4),%YMM4

  (60) 0x50ea VCVTPS2PD	0x10(%RBX,%R9,4),%YMM5

  (60) 0x50f1 VCVTPS2PD	0x20(%RBX,%R9,4),%YMM6

  (60) 0x50f8 VCVTPS2PD	0x30(%RBX,%R9,4),%YMM7

  (60) 0x50ff LEA	(%RDI,%R8,1),%R9D

  (60) 0x5103 ADD	$0x10,%R8

  (60) 0x5107 VCVTPS2PD	(%R11,%R9,4),%YMM8

  (60) 0x510d VCVTPS2PD	0x10(%R11,%R9,4),%YMM9

  (60) 0x5114 VFMADD231PD	%YMM8,%YMM4,%YMM0

  (60) 0x5119 VFMADD231PD	%YMM9,%YMM5,%YMM1

  (60) 0x511e VCVTPS2PD	0x20(%R11,%R9,4),%YMM8

  (60) 0x5125 VCVTPS2PD	0x30(%R11,%R9,4),%YMM5

  (60) 0x512c VFMADD231PD	%YMM8,%YMM6,%YMM2

  (60) 0x5131 VFMADD231PD	%YMM5,%YMM7,%YMM3

  (60) 0x5136 CMP	%R8,%R10

  (60) 0x5139 JNE	50e0

0x513b VADDPD	%YMM0,%YMM1,%YMM0

0x513f VADDPD	%YMM2,%YMM3,%YMM1

0x5143 CMPQ	$0,0x1b0(%RSP)

0x514c MOV	%R10,%R8

0x514f VADDPD	%YMM0,%YMM1,%YMM0

0x5153 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x5159 VADDPD	%XMM1,%XMM0,%XMM0

0x515d VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x5162 VADDSD	%XMM1,%XMM0,%XMM0

0x5166 JNE	507f

0x516c JMP	5040

/home/eoseret/llm-attention/attention_v2.cpp: 26 - 33

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.55
CQA speedup if FP arith vectorized	1.77
CQA speedup if fully vectorized	5.76
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.34
CQA cycles if no scalar integer	2.16
CQA cycles if FP arith vectorized	1.89
CQA cycles if fully vectorized	0.58
Front-end cycles	3.34
P0 cycles	2.08
P1 cycles	2.08
P2 cycles	2.08
P3 cycles	2.08
P4 cycles	2.08
P5 cycles	2.08
P6 cycles	0.94
P7 cycles	0.94
P8 cycles	0.94
P9 cycles	0.94
P10 cycles	0.50
P11 cycles	0.50
P12 cycles	1.75
P13 cycles	1.75
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.75
Nb uops	26.75
Nb loads	2.75
Nb stores	1.00
Nb stack references	2.75
FLOP/cycle	2.24
Nb FLOP add-sub	7.50
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.69
Bytes prefetched	0.00
Bytes loaded	19.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	42.35
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	80.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	47.50
Vector-efficiency ratio all	18.38
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	37.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	17.34

Metric	Value
CQA speedup if no scalar integer	1.60
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	14.22
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	1.25
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.14
Front-end cycles	2.00
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	1.50
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	16.00
Nb loads	1.00
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.00
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	20.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	25.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.06

Metric	Value
CQA speedup if no scalar integer	1.91
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	14.61
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.63
CQA cycles if no scalar integer	1.38
CQA cycles if FP arith vectorized	2.63
CQA cycles if fully vectorized	0.18
Front-end cycles	2.63
P0 cycles	2.17
P1 cycles	2.17
P2 cycles	2.17
P3 cycles	2.17
P4 cycles	2.17
P5 cycles	2.17
P6 cycles	0.75
P7 cycles	0.75
P8 cycles	0.75
P9 cycles	0.75
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	2.00
Nb stores	1.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.10
Bytes prefetched	0.00
Bytes loaded	12.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	20.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	25.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.06

Metric	Value
CQA speedup if no scalar integer	1.38
CQA speedup if FP arith vectorized	2.87
CQA speedup if fully vectorized	4.13
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.13
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	1.44
CQA cycles if fully vectorized	1.00
Front-end cycles	4.13
P0 cycles	2.17
P1 cycles	2.17
P2 cycles	2.17
P3 cycles	2.17
P4 cycles	2.17
P5 cycles	2.17
P6 cycles	1.25
P7 cycles	1.25
P8 cycles	1.25
P9 cycles	1.25
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	3.00
P13 cycles	3.00
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	33.00
Nb uops	33.00
Nb loads	4.00
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	3.64
Nb FLOP add-sub	15.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.76
Bytes prefetched	0.00
Bytes loaded	28.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	64.71
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	80.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	70.00
Vector-efficiency ratio all	24.26
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	37.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.63

Metric	Value
CQA speedup if no scalar integer	1.54
CQA speedup if FP arith vectorized	3.08
CQA speedup if fully vectorized	4.63
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.54
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.63
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	1.50
CQA cycles if fully vectorized	1.00
Front-end cycles	4.63
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	2.50
P6 cycles	1.25
P7 cycles	1.25
P8 cycles	1.25
P9 cycles	1.25
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	3.00
P13 cycles	3.00
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	4.00
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	3.24
Nb FLOP add-sub	15.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.92
Bytes prefetched	0.00
Bytes loaded	28.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	3.00
Stride indirect	0.00
Vectorization ratio all	64.71
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	80.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	70.00
Vector-efficiency ratio all	24.26
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	37.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.63

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-aocc-znver5-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-27,30,33.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 18% of vector register length is used (average across all SSE/AVX instructions).

Details

42% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
80% of SSE/AVX addition or subtraction instructions are used in vector version.
47% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

0 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 0 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 1 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 7.5 FP arithmetical operations:

7.50: addition or subtraction

The binary loop is loading 19 bytes (2 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.33 FP operations per loaded or stored byte.

General properties

nb instructions	26.75
nb uops	26.75
loop length	112.50
used x86 registers	9
used mmx registers	0
used xmm registers	2.50
used ymm registers	2
used zmm registers	0
nb stack references	2.75

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	3.34 cycles
front end	3.34 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.08	2.08	2.08	2.08	2.08	2.08	0.94	0.94	0.94	0.94	0.50	0.50	1.75	1.75	0.50	0.50
cycles	2.08	2.08	2.08	2.08	2.08	2.08	0.94	0.94	0.94	0.94	0.50	0.50	1.75	1.75	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	3.34
Dispatch	2.42
Data deps.	0.00
Overall L1	3.34

Vectorization ratios

INT

all	12%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	55%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	80%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	67%

INT+FP

all	42%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	80%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	47%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	20%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	37%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	18%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	37%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.34 cycles. At this rate:

2% of peak load performance is reached (5.35 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.34 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-aocc-znver5-256

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.00 to 1.25 cycles (1.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.14 cycles (14.22x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	16
nb uops	16
loop length	62
used x86 registers	8
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.00 cycles
front end	2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.50	1.50	1.50	1.50	1.50	1.50	0.50	0.50	0.50	0.50	0.00	0.00	0.50	0.50	0.50	0.50
cycles	1.50	1.50	1.50	1.50	1.50	1.50	0.50	0.50	0.50	0.50	0.00	0.00	0.50	0.50	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	2.00
Dispatch	1.50
Data deps.	0.00
Overall L1	2.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	20%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Vector efficiency ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

1% of peak load performance is reached (4.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.00 to 1.50 cycles (1.33x speedup).

ASM code

In the binary file, the address of the loop is: 505e

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0xc8(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VCVTSD2SS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
LEA (%RSI,%RDI,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS %XMM0,(%R9,%R8,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (6.3%)
CMP %R13,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 4ff0 <main+0x13e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMP $0x10,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 507c <main+0x146c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
IMUL %R8,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %RDI,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 5040 <main+0x1430>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-aocc-znver5-256

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.63 to 1.38 cycles (1.91x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 12 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	21
nb uops	21
loop length	82
used x86 registers	9
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.63 cycles
front end	2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.17	2.17	2.17	2.17	2.17	2.17	0.75	0.75	0.75	0.75	0.00	0.00	0.50	0.50	0.50	0.50
cycles	2.17	2.17	2.17	2.17	2.17	2.17	0.75	0.75	0.75	0.75	0.00	0.00	0.50	0.50	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	2.63
Dispatch	2.17
Data deps.	0.00
Overall L1	2.63

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	20%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Vector efficiency ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.63 cycles. At this rate:

1% of peak load performance is reached (4.57 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.52 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 505e

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0xc8(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VCVTSD2SS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
LEA (%RSI,%RDI,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS %XMM0,(%R9,%R8,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (6.3%)
CMP %R13,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 4ff0 <main+0x13e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMP $0x10,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 507c <main+0x146c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV %EDI,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
ADD 0xd8(%RSP),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
SETB %R8B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
OR %DL,%R8B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 50c0 <main+0x14b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
IMUL %R8,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %RDI,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 5040 <main+0x1430>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-aocc-znver5-256

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.13 to 3.00 cycles (1.37x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 24% of vector register length is used (average across all SSE/AVX instructions).

Details

64% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
80% of SSE/AVX addition or subtraction instructions are used in vector version.
70% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 3 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 15 FP arithmetical operations:

15: addition or subtraction

The binary loop is loading 28 bytes (3 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.47 FP operations per loaded or stored byte.

General properties

nb instructions	33
nb uops	33
loop length	146
used x86 registers	9
used mmx registers	0
used xmm registers	4
used ymm registers	4
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.13 cycles
front end	4.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.17	2.17	2.17	2.17	2.17	2.17	1.25	1.25	1.25	1.25	1.00	1.00	3.00	3.00	0.50	0.50
cycles	2.17	2.17	2.17	2.17	2.17	2.17	1.25	1.25	1.25	1.25	1.00	1.00	3.00	3.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	4.13
Dispatch	3.00
Data deps.	0.00
Overall L1	4.13

Vectorization ratios

INT

all	25%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	76%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	80%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

INT+FP

all	64%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	80%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	70%

Vector efficiency ratios

INT

all	14%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	27%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	37%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

INT+FP

all	24%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	37%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.13 cycles. At this rate:

2% of peak load performance is reached (6.79 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.97 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 505e

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0xc8(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VCVTSD2SS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
LEA (%RSI,%RDI,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS %XMM0,(%R9,%R8,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
CMP %R13,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 4ff0 <main+0x13e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMP $0x10,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 507c <main+0x146c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV %EDI,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
ADD 0xd8(%RSP),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SETB %R8B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR %DL,%R8B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 50c0 <main+0x14b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x1a8(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPXOR %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VADDPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM2,%YMM3,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
CMPQ $0,0x1b0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VADDPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
JNE 507f <main+0x146f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
JMP 5040 <main+0x1430>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-aocc-znver5-256

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.63 to 3.00 cycles (1.54x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 24% of vector register length is used (average across all SSE/AVX instructions).

Details

64% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
80% of SSE/AVX addition or subtraction instructions are used in vector version.
70% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 15 FP arithmetical operations:

15: addition or subtraction

The binary loop is loading 28 bytes (3 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.47 FP operations per loaded or stored byte.

General properties

nb instructions	37
nb uops	37
loop length	160
used x86 registers	10
used mmx registers	0
used xmm registers	4
used ymm registers	4
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.63 cycles
front end	4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.50	2.50	2.50	2.50	2.50	2.50	1.25	1.25	1.25	1.25	1.00	1.00	3.00	3.00	0.50	0.50
cycles	2.50	2.50	2.50	2.50	2.50	2.50	1.25	1.25	1.25	1.25	1.00	1.00	3.00	3.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	4.63
Dispatch	3.00
Data deps.	0.00
Overall L1	4.63

Vectorization ratios

INT

all	25%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	76%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	80%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

INT+FP

all	64%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	80%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	70%

Vector efficiency ratios

INT

all	14%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	27%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	37%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

INT+FP

all	24%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	37%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.63 cycles. At this rate:

2% of peak load performance is reached (6.05 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.86 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 505e

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0xc8(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VCVTSD2SS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
LEA (%RSI,%RDI,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS %XMM0,(%R9,%R8,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
CMP %R13,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 4ff0 <main+0x13e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMP $0x10,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 507c <main+0x146c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV %EDI,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
ADD 0xd8(%RSP),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SETB %R8B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR %DL,%R8B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 50c0 <main+0x14b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV %R14,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
IMUL %R8,%R9	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %RDI,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 5040 <main+0x1430>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV 0x1a8(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VPXOR %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VADDPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM2,%YMM3,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
CMPQ $0,0x1b0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VADDPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
JNE 507f <main+0x146f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A

Report Configuration

Vectorization

Details

Workaround

512-bits vectorization

Workaround

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions