| Loop Id: 95 | Module: attention-clang-znver5-512 | Source: random.tcc:404-406 | Coverage: 0.06% |
|---|
| Loop Id: 95 | Module: attention-clang-znver5-512 | Source: random.tcc:404-406 | Coverage: 0.06% |
|---|
0x5540 VMOVDQU64 0x640(%RSP,%RCX,8),%ZMM3 [1] |
0x5548 VMOVDQU64 0x680(%RSP,%RCX,8),%ZMM4 [1] |
0x5550 VMOVDQU64 0x6c0(%RSP,%RCX,8),%ZMM5 [1] |
0x5558 VALIGNQ $0x7,%ZMM2,%ZMM3,%ZMM6 |
0x555f VMOVDQU64 0x700(%RSP,%RCX,8),%ZMM2 [1] |
0x5567 VALIGNQ $0x7,%ZMM3,%ZMM4,%ZMM7 |
0x556e VALIGNQ $0x7,%ZMM4,%ZMM5,%ZMM8 |
0x5575 VPANDQ %ZMM15,%ZMM3,%ZMM10 |
0x557b VPANDQ %ZMM15,%ZMM4,%ZMM11 |
0x5581 VPANDQ %ZMM15,%ZMM5,%ZMM12 |
0x5587 VPTESTMQ %ZMM16,%ZMM3,%K1 |
0x558d VPTESTMQ %ZMM16,%ZMM4,%K2 |
0x5593 VPTESTMQ %ZMM16,%ZMM5,%K3 |
0x5599 VPTERNLOGQ $-0x8,%ZMM14,%ZMM6,%ZMM10 |
0x55a0 VPTERNLOGQ $-0x8,%ZMM14,%ZMM7,%ZMM11 |
0x55a7 VPTERNLOGQ $-0x8,%ZMM14,%ZMM8,%ZMM12 |
0x55ae VPSRLQ $0x1,%ZMM10,%ZMM6 |
0x55b5 VPSRLQ $0x1,%ZMM11,%ZMM7 |
0x55bc VPSRLQ $0x1,%ZMM12,%ZMM8 |
0x55c3 VPXORQ 0x12a0(%RSP,%RCX,8),%ZMM6,%ZMM6 [1] |
0x55ce VPXORQ 0x12e0(%RSP,%RCX,8),%ZMM7,%ZMM7 [1] |
0x55d9 VPXORQ 0x1320(%RSP,%RCX,8),%ZMM8,%ZMM8 [1] |
0x55e4 VALIGNQ $0x7,%ZMM5,%ZMM2,%ZMM9 |
0x55eb VPANDQ %ZMM15,%ZMM2,%ZMM13 |
0x55f1 VPTESTMQ %ZMM16,%ZMM2,%K4 |
0x55f7 VPTERNLOGQ $-0x8,%ZMM14,%ZMM9,%ZMM13 |
0x55fe VPSRLQ $0x1,%ZMM13,%ZMM9 |
0x5605 VPXORQ 0x1360(%RSP,%RCX,8),%ZMM9,%ZMM9 [1] |
0x5610 VPXORQ %ZMM17,%ZMM6,%ZMM6{%K1} |
0x5616 VPXORQ %ZMM17,%ZMM7,%ZMM7{%K2} |
0x561c VPXORQ %ZMM17,%ZMM8,%ZMM8{%K3} |
0x5622 VMOVDQU64 %ZMM6,0x638(%RSP,%RCX,8) [1] |
0x562d VMOVDQU64 %ZMM7,0x678(%RSP,%RCX,8) [1] |
0x5638 VMOVDQU64 %ZMM8,0x6b8(%RSP,%RCX,8) [1] |
0x5643 VPXORQ %ZMM17,%ZMM9,%ZMM9{%K4} |
0x5649 VMOVDQU64 %ZMM9,0x6f8(%RSP,%RCX,8) [1] |
0x5654 ADD $0x20,%RCX |
0x5658 CMP $0xe0,%RCX |
0x565f JNE 5540 |
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 404 - 406 |
-------------------------------------------------------------------------------- |
404: | (_M_x[__k + 1] & __lower_mask)); |
405: _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1) |
406: ^ ((__y & 0x01) ? __a : 0)); |
| Coverage (%) | Name | Source Location | Module |
|---|
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.33 |
| Bottlenecks | P10, P11, P12, P13, |
| Function | main |
| Source | random.tcc:404-406 |
| Source loop unroll info | multi-versionned |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 7.00 |
| CQA cycles if no scalar integer | 7.00 |
| CQA cycles if FP arith vectorized | 7.00 |
| CQA cycles if fully vectorized | 7.00 |
| Front-end cycles | 5.25 |
| P0 cycles | 0.33 |
| P1 cycles | 0.33 |
| P2 cycles | 0.33 |
| P3 cycles | 0.33 |
| P4 cycles | 0.33 |
| P5 cycles | 0.33 |
| P6 cycles | 3.00 |
| P7 cycles | 3.00 |
| P8 cycles | 3.00 |
| P9 cycles | 3.00 |
| P10 cycles | 7.00 |
| P11 cycles | 7.00 |
| P12 cycles | 7.00 |
| P13 cycles | 7.00 |
| P14 cycles | 4.00 |
| P15 cycles | 4.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 39.00 |
| Nb uops | 42.00 |
| Nb loads | 8.00 |
| Nb stores | 4.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 109.71 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 512.00 |
| Bytes stored | 256.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 100.00 |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 100.00 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.33 |
| Bottlenecks | P10, P11, P12, P13, |
| Function | main |
| Source | random.tcc:404-406 |
| Source loop unroll info | multi-versionned |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 7.00 |
| CQA cycles if no scalar integer | 7.00 |
| CQA cycles if FP arith vectorized | 7.00 |
| CQA cycles if fully vectorized | 7.00 |
| Front-end cycles | 5.25 |
| P0 cycles | 0.33 |
| P1 cycles | 0.33 |
| P2 cycles | 0.33 |
| P3 cycles | 0.33 |
| P4 cycles | 0.33 |
| P5 cycles | 0.33 |
| P6 cycles | 3.00 |
| P7 cycles | 3.00 |
| P8 cycles | 3.00 |
| P9 cycles | 3.00 |
| P10 cycles | 7.00 |
| P11 cycles | 7.00 |
| P12 cycles | 7.00 |
| P13 cycles | 7.00 |
| P14 cycles | 4.00 |
| P15 cycles | 4.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 39.00 |
| Nb uops | 42.00 |
| Nb loads | 8.00 |
| Nb stores | 4.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 109.71 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 512.00 |
| Bytes stored | 256.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 100.00 |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 100.00 |
| Path / |
| Function | main |
| Source file and lines | random.tcc:404-406 |
| Module | attention-clang-znver5-512 |
| nb instructions | 39 |
| nb uops | 42 |
| loop length | 293 |
| used x86 registers | 2 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 16 |
| nb stack references | 0 |
| micro-operation queue | 5.25 cycles |
| front end | 5.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.33 | 0.33 | 0.33 | 0.33 | 0.33 | 0.33 | 3.00 | 3.00 | 3.00 | 3.00 | 7.00 | 7.00 | 7.00 | 7.00 | 4.00 | 4.00 |
| cycles | 0.33 | 0.33 | 0.33 | 0.33 | 0.33 | 0.33 | 3.00 | 3.00 | 3.00 | 3.00 | 7.00 | 7.00 | 7.00 | 7.00 | 4.00 | 4.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 5.25 |
| Dispatch | 7.00 |
| Data deps. | 1.00 |
| Overall L1 | 7.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVDQU64 0x640(%RSP,%RCX,8),%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VMOVDQU64 0x680(%RSP,%RCX,8),%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VMOVDQU64 0x6c0(%RSP,%RCX,8),%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VALIGNQ $0x7,%ZMM2,%ZMM3,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 5 | 0.50 | vect (100.0%) |
| VMOVDQU64 0x700(%RSP,%RCX,8),%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VALIGNQ $0x7,%ZMM3,%ZMM4,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 5 | 0.50 | vect (100.0%) |
| VALIGNQ $0x7,%ZMM4,%ZMM5,%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 5 | 0.50 | vect (100.0%) |
| VPANDQ %ZMM15,%ZMM3,%ZMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VPANDQ %ZMM15,%ZMM4,%ZMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VPANDQ %ZMM15,%ZMM5,%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VPTESTMQ %ZMM16,%ZMM3,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| VPTESTMQ %ZMM16,%ZMM4,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| VPTESTMQ %ZMM16,%ZMM5,%K3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| VPTERNLOGQ $-0x8,%ZMM14,%ZMM6,%ZMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VPTERNLOGQ $-0x8,%ZMM14,%ZMM7,%ZMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VPTERNLOGQ $-0x8,%ZMM14,%ZMM8,%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VPSRLQ $0x1,%ZMM10,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 1-2 | 0.50 | vect (100.0%) |
| VPSRLQ $0x1,%ZMM11,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 1-2 | 0.50 | vect (100.0%) |
| VPSRLQ $0x1,%ZMM12,%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 1-2 | 0.50 | vect (100.0%) |
| VPXORQ 0x12a0(%RSP,%RCX,8),%ZMM6,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.50 | vect (100.0%) |
| VPXORQ 0x12e0(%RSP,%RCX,8),%ZMM7,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.50 | vect (100.0%) |
| VPXORQ 0x1320(%RSP,%RCX,8),%ZMM8,%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.50 | vect (100.0%) |
| VALIGNQ $0x7,%ZMM5,%ZMM2,%ZMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 5 | 0.50 | vect (100.0%) |
| VPANDQ %ZMM15,%ZMM2,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VPTESTMQ %ZMM16,%ZMM2,%K4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| VPTERNLOGQ $-0x8,%ZMM14,%ZMM9,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VPSRLQ $0x1,%ZMM13,%ZMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 1-2 | 0.50 | vect (100.0%) |
| VPXORQ 0x1360(%RSP,%RCX,8),%ZMM9,%ZMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.50 | vect (100.0%) |
| VPXORQ %ZMM17,%ZMM6,%ZMM6{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VPXORQ %ZMM17,%ZMM7,%ZMM7{%K2} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VPXORQ %ZMM17,%ZMM8,%ZMM8{%K3} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VMOVDQU64 %ZMM6,0x638(%RSP,%RCX,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 1 | 1 | 4 | 1 | vect (100.0%) |
| VMOVDQU64 %ZMM7,0x678(%RSP,%RCX,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 1 | 1 | 4 | 1 | vect (100.0%) |
| VMOVDQU64 %ZMM8,0x6b8(%RSP,%RCX,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 1 | 1 | 4 | 1 | vect (100.0%) |
| VPXORQ %ZMM17,%ZMM9,%ZMM9{%K4} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VMOVDQU64 %ZMM9,0x6f8(%RSP,%RCX,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 1 | 1 | 4 | 1 | vect (100.0%) |
| ADD $0x20,%RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP $0xe0,%RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| JNE 5540 <main+0x1b90> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33-0.50 | N/A |
| Function | main |
| Source file and lines | random.tcc:404-406 |
| Module | attention-clang-znver5-512 |
| nb instructions | 39 |
| nb uops | 42 |
| loop length | 293 |
| used x86 registers | 2 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 16 |
| nb stack references | 0 |
| micro-operation queue | 5.25 cycles |
| front end | 5.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.33 | 0.33 | 0.33 | 0.33 | 0.33 | 0.33 | 3.00 | 3.00 | 3.00 | 3.00 | 7.00 | 7.00 | 7.00 | 7.00 | 4.00 | 4.00 |
| cycles | 0.33 | 0.33 | 0.33 | 0.33 | 0.33 | 0.33 | 3.00 | 3.00 | 3.00 | 3.00 | 7.00 | 7.00 | 7.00 | 7.00 | 4.00 | 4.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 5.25 |
| Dispatch | 7.00 |
| Data deps. | 1.00 |
| Overall L1 | 7.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVDQU64 0x640(%RSP,%RCX,8),%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VMOVDQU64 0x680(%RSP,%RCX,8),%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VMOVDQU64 0x6c0(%RSP,%RCX,8),%ZMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VALIGNQ $0x7,%ZMM2,%ZMM3,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 5 | 0.50 | vect (100.0%) |
| VMOVDQU64 0x700(%RSP,%RCX,8),%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 | vect (100.0%) |
| VALIGNQ $0x7,%ZMM3,%ZMM4,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 5 | 0.50 | vect (100.0%) |
| VALIGNQ $0x7,%ZMM4,%ZMM5,%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 5 | 0.50 | vect (100.0%) |
| VPANDQ %ZMM15,%ZMM3,%ZMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VPANDQ %ZMM15,%ZMM4,%ZMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VPANDQ %ZMM15,%ZMM5,%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VPTESTMQ %ZMM16,%ZMM3,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| VPTESTMQ %ZMM16,%ZMM4,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| VPTESTMQ %ZMM16,%ZMM5,%K3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| VPTERNLOGQ $-0x8,%ZMM14,%ZMM6,%ZMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VPTERNLOGQ $-0x8,%ZMM14,%ZMM7,%ZMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VPTERNLOGQ $-0x8,%ZMM14,%ZMM8,%ZMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VPSRLQ $0x1,%ZMM10,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 1-2 | 0.50 | vect (100.0%) |
| VPSRLQ $0x1,%ZMM11,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 1-2 | 0.50 | vect (100.0%) |
| VPSRLQ $0x1,%ZMM12,%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 1-2 | 0.50 | vect (100.0%) |
| VPXORQ 0x12a0(%RSP,%RCX,8),%ZMM6,%ZMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.50 | vect (100.0%) |
| VPXORQ 0x12e0(%RSP,%RCX,8),%ZMM7,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.50 | vect (100.0%) |
| VPXORQ 0x1320(%RSP,%RCX,8),%ZMM8,%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.50 | vect (100.0%) |
| VALIGNQ $0x7,%ZMM5,%ZMM2,%ZMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 5 | 0.50 | vect (100.0%) |
| VPANDQ %ZMM15,%ZMM2,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VPTESTMQ %ZMM16,%ZMM2,%K4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 | vect (100.0%) |
| VPTERNLOGQ $-0x8,%ZMM14,%ZMM9,%ZMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VPSRLQ $0x1,%ZMM13,%ZMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 1-2 | 0.50 | vect (100.0%) |
| VPXORQ 0x1360(%RSP,%RCX,8),%ZMM9,%ZMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.50 | vect (100.0%) |
| VPXORQ %ZMM17,%ZMM6,%ZMM6{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VPXORQ %ZMM17,%ZMM7,%ZMM7{%K2} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VPXORQ %ZMM17,%ZMM8,%ZMM8{%K3} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VMOVDQU64 %ZMM6,0x638(%RSP,%RCX,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 1 | 1 | 4 | 1 | vect (100.0%) |
| VMOVDQU64 %ZMM7,0x678(%RSP,%RCX,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 1 | 1 | 4 | 1 | vect (100.0%) |
| VMOVDQU64 %ZMM8,0x6b8(%RSP,%RCX,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 1 | 1 | 4 | 1 | vect (100.0%) |
| VPXORQ %ZMM17,%ZMM9,%ZMM9{%K4} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 1-2 | 0.25 | vect (100.0%) |
| VMOVDQU64 %ZMM9,0x6f8(%RSP,%RCX,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 1 | 1 | 4 | 1 | vect (100.0%) |
| ADD $0x20,%RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP $0xe0,%RCX | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| JNE 5540 <main+0x1b90> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33-0.50 | N/A |
