OV - attention-clang-znver5-512 - Loop 93 - attention-clang-znver5-512

	Loop Id: 93	Module: attention-clang-znver5-512	Source: attention_v2.cpp:164-167 [...]	Coverage: 0.11%

0x4b10 VMOVSS	0x44fc(%RIP),%XMM1

0x4b18 VXORPS	%XMM0,%XMM0,%XMM0

0x4b1c MOV	%R8,%RAX

0x4b1f JMP	4b95

  (100) 0x4b30 MOV	%R13,%RCX

  (100) 0x4b33 INC	%R13

  (100) 0x4b36 MOV	$0x200b,%EDX

  (100) 0x4b3b MOV	%R13,0x19b8(%RSP)

  (100) 0x4b43 MOV	0x638(%RSP,%RCX,8),%RCX

  (100) 0x4b4b BEXTR	%RDX,%RCX,%RDX

  (100) 0x4b50 XOR	%RCX,%RDX

  (100) 0x4b53 MOV	%EDX,%ECX

  (100) 0x4b55 SAL	$0x7,%ECX

  (100) 0x4b58 AND	$-0x62d3a980,%ECX

  (100) 0x4b5e XOR	%RDX,%RCX

  (100) 0x4b61 MOV	%ECX,%EDX

  (100) 0x4b63 SAL	$0xf,%EDX

  (100) 0x4b66 AND	$-0x103a0000,%EDX

  (100) 0x4b6c XOR	%RCX,%RDX

  (100) 0x4b6f MOV	%RDX,%RCX

  (100) 0x4b72 SHR	$0x12,%RCX

  (100) 0x4b76 XOR	%RDX,%RCX

  (100) 0x4b79 DEC	%RAX

  (100) 0x4b7c VCVTUSI2SS	%RCX,%XMM15,%XMM2

  (100) 0x4b82 VFMADD231SS	%XMM2,%XMM1,%XMM0

  (100) 0x4b87 VMULSS	0x4479(%RIP),%XMM1,%XMM1

  (100) 0x4b8f JE	4fb0

  (100) 0x4b95 CMP	$0x270,%R13

  (100) 0x4b9c JB	4b30

  (100) 0x4b9e VPBROADCASTQ	0x4498(%RIP),%ZMM14

  (100) 0x4ba8 VPBROADCASTQ	0x4496(%RIP),%ZMM15

  (100) 0x4bb2 VPBROADCASTQ	0x4494(%RIP),%ZMM16

  (100) 0x4bbc VPBROADCASTQ	0x4492(%RIP),%ZMM17

  (100) 0x4bc6 VPBROADCASTQ	%RBX,%ZMM2

  (100) 0x4bcc XOR	%ECX,%ECX

  (100) 0x4bce XCHG	%AX,%AX

    (101) 0x4bd0 VMOVDQU64	0x640(%RSP,%RCX,8),%ZMM3

    (101) 0x4bd8 VMOVDQU64	0x680(%RSP,%RCX,8),%ZMM4

    (101) 0x4be0 VMOVDQU64	0x6c0(%RSP,%RCX,8),%ZMM5

    (101) 0x4be8 VALIGNQ	$0x7,%ZMM2,%ZMM3,%ZMM6

    (101) 0x4bef VMOVDQU64	0x700(%RSP,%RCX,8),%ZMM2

    (101) 0x4bf7 VALIGNQ	$0x7,%ZMM3,%ZMM4,%ZMM7

    (101) 0x4bfe VALIGNQ	$0x7,%ZMM4,%ZMM5,%ZMM8

    (101) 0x4c05 VPANDQ	%ZMM15,%ZMM3,%ZMM10

    (101) 0x4c0b VPANDQ	%ZMM15,%ZMM4,%ZMM11

    (101) 0x4c11 VPANDQ	%ZMM15,%ZMM5,%ZMM12

    (101) 0x4c17 VPTESTMQ	%ZMM16,%ZMM3,%K1

    (101) 0x4c1d VPTESTMQ	%ZMM16,%ZMM4,%K2

    (101) 0x4c23 VPTESTMQ	%ZMM16,%ZMM5,%K3

    (101) 0x4c29 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM6,%ZMM10

    (101) 0x4c30 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM7,%ZMM11

    (101) 0x4c37 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM8,%ZMM12

    (101) 0x4c3e VPSRLQ	$0x1,%ZMM10,%ZMM6

    (101) 0x4c45 VPSRLQ	$0x1,%ZMM11,%ZMM7

    (101) 0x4c4c VPSRLQ	$0x1,%ZMM12,%ZMM8

    (101) 0x4c53 VPXORQ	0x12a0(%RSP,%RCX,8),%ZMM6,%ZMM6

    (101) 0x4c5e VPXORQ	0x12e0(%RSP,%RCX,8),%ZMM7,%ZMM7

    (101) 0x4c69 VPXORQ	0x1320(%RSP,%RCX,8),%ZMM8,%ZMM8

    (101) 0x4c74 VALIGNQ	$0x7,%ZMM5,%ZMM2,%ZMM9

    (101) 0x4c7b VPANDQ	%ZMM15,%ZMM2,%ZMM13

    (101) 0x4c81 VPTESTMQ	%ZMM16,%ZMM2,%K4

    (101) 0x4c87 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM9,%ZMM13

    (101) 0x4c8e VPSRLQ	$0x1,%ZMM13,%ZMM9

    (101) 0x4c95 VPXORQ	0x1360(%RSP,%RCX,8),%ZMM9,%ZMM9

    (101) 0x4ca0 VPXORQ	%ZMM17,%ZMM6,%ZMM6{%K1}

    (101) 0x4ca6 VPXORQ	%ZMM17,%ZMM7,%ZMM7{%K2}

    (101) 0x4cac VPXORQ	%ZMM17,%ZMM8,%ZMM8{%K3}

    (101) 0x4cb2 VMOVDQU64	%ZMM6,0x638(%RSP,%RCX,8)

    (101) 0x4cbd VMOVDQU64	%ZMM7,0x678(%RSP,%RCX,8)

    (101) 0x4cc8 VMOVDQU64	%ZMM8,0x6b8(%RSP,%RCX,8)

    (101) 0x4cd3 VPXORQ	%ZMM17,%ZMM9,%ZMM9{%K4}

    (101) 0x4cd9 VMOVDQU64	%ZMM9,0x6f8(%RSP,%RCX,8)

    (101) 0x4ce4 ADD	$0x20,%RCX

    (101) 0x4ce8 CMP	$0xe0,%RCX

    (101) 0x4cef JNE	4bd0

  (100) 0x4cf5 MOV	0xd40(%RSP),%RDX

  (100) 0x4cfd VEXTRACTI32X4	$0x3,%ZMM2,%XMM2

  (100) 0x4d04 MOV	0xd48(%RSP),%RCX

  (100) 0x4d0c VPBROADCASTQ	0x432b(%RIP),%XMM8

  (100) 0x4d15 VPBROADCASTQ	0x432a(%RIP),%XMM9

  (100) 0x4d1e VPBROADCASTQ	0x4329(%RIP),%XMM10

  (100) 0x4d27 VPBROADCASTQ	0x4328(%RIP),%XMM11

  (100) 0x4d30 VPEXTRQ	$0x1,%XMM2,%RSI

  (100) 0x4d36 AND	$-0x80000000,%RSI

  (100) 0x4d3d MOV	%EDX,%EDI

  (100) 0x4d3f AND	$0x7ffffffe,%EDI

  (100) 0x4d45 OR	%RSI,%RDI

  (100) 0x4d48 MOV	%EDX,%ESI

  (100) 0x4d4a AND	$0x1,%ESI

  (100) 0x4d4d AND	$-0x80000000,%RDX

  (100) 0x4d54 SHR	$0x1,%RDI

  (100) 0x4d57 XOR	0x19a0(%RSP),%RDI

  (100) 0x4d5f NEG	%ESI

  (100) 0x4d61 AND	%R12D,%ESI

  (100) 0x4d64 XOR	%RDI,%RSI

  (100) 0x4d67 MOV	%RSI,0xd38(%RSP)

  (100) 0x4d6f MOV	%ECX,%ESI

  (100) 0x4d71 AND	$0x7ffffffe,%ESI

  (100) 0x4d77 OR	%RDX,%RSI

  (100) 0x4d7a MOV	%ECX,%EDX

  (100) 0x4d7c AND	$0x1,%EDX

  (100) 0x4d7f AND	$-0x80000000,%RCX

  (100) 0x4d86 SHR	$0x1,%RSI

  (100) 0x4d89 XOR	0x19a8(%RSP),%RSI

  (100) 0x4d91 NEG	%EDX

  (100) 0x4d93 AND	%R12D,%EDX

  (100) 0x4d96 XOR	%RSI,%RDX

  (100) 0x4d99 MOV	%RDX,0xd40(%RSP)

  (100) 0x4da1 MOV	0xd50(%RSP),%RDX

  (100) 0x4da9 MOV	%EDX,%ESI

  (100) 0x4dab VPBROADCASTQ	%RDX,%XMM2

  (100) 0x4db1 AND	$0x7ffffffe,%EDX

  (100) 0x4db7 AND	$0x1,%ESI

  (100) 0x4dba OR	%RCX,%RDX

  (100) 0x4dbd NEG	%ESI

  (100) 0x4dbf MOV	$0xee,%ECX

  (100) 0x4dc4 SHR	$0x1,%RDX

  (100) 0x4dc7 XOR	0x19b0(%RSP),%RDX

  (100) 0x4dcf AND	%R12D,%ESI

  (100) 0x4dd2 XOR	%RDX,%RSI

  (100) 0x4dd5 MOV	%RSI,0xd48(%RSP)

  (100) 0x4ddd NOPL	(%RAX)

    (102) 0x4de0 VMOVDQU	0x5e8(%RSP,%RCX,8),%XMM3

    (102) 0x4de9 VMOVDQU	0x5f8(%RSP,%RCX,8),%XMM4

    (102) 0x4df2 VMOVDQU	0x608(%RSP,%RCX,8),%XMM5

    (102) 0x4dfb VMOVDQU	0x618(%RSP,%RCX,8),%XMM6

    (102) 0x4e04 VPALIGNR	$0x8,%XMM2,%XMM3,%XMM2

    (102) 0x4e0a VPAND	%XMM3,%XMM9,%XMM7

    (102) 0x4e0e VPTESTMQ	%XMM10,%XMM3,%K1

    (102) 0x4e14 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM7

    (102) 0x4e1b VPSRLQ	$0x1,%XMM7,%XMM2

    (102) 0x4e20 VPXOR	-0x138(%RSP,%RCX,8),%XMM2,%XMM2

    (102) 0x4e29 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (102) 0x4e2f VPTESTMQ	%XMM10,%XMM4,%K1

    (102) 0x4e35 VMOVDQU	%XMM2,0x5e0(%RSP,%RCX,8)

    (102) 0x4e3e VPALIGNR	$0x8,%XMM3,%XMM4,%XMM2

    (102) 0x4e44 VPAND	%XMM4,%XMM9,%XMM3

    (102) 0x4e48 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

    (102) 0x4e4f VPSRLQ	$0x1,%XMM3,%XMM2

    (102) 0x4e54 VPXOR	-0x128(%RSP,%RCX,8),%XMM2,%XMM2

    (102) 0x4e5d VPAND	%XMM5,%XMM9,%XMM3

    (102) 0x4e61 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (102) 0x4e67 VPTESTMQ	%XMM10,%XMM5,%K1

    (102) 0x4e6d VMOVDQU	%XMM2,0x5f0(%RSP,%RCX,8)

    (102) 0x4e76 VPALIGNR	$0x8,%XMM4,%XMM5,%XMM2

    (102) 0x4e7c VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

    (102) 0x4e83 VPSRLQ	$0x1,%XMM3,%XMM2

    (102) 0x4e88 VPXOR	-0x118(%RSP,%RCX,8),%XMM2,%XMM2

    (102) 0x4e91 VPAND	%XMM6,%XMM9,%XMM3

    (102) 0x4e95 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (102) 0x4e9b VPTESTMQ	%XMM10,%XMM6,%K1

    (102) 0x4ea1 VMOVDQU	%XMM2,0x600(%RSP,%RCX,8)

    (102) 0x4eaa VPALIGNR	$0x8,%XMM5,%XMM6,%XMM2

    (102) 0x4eb0 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

    (102) 0x4eb7 VPSRLQ	$0x1,%XMM3,%XMM2

    (102) 0x4ebc VPXOR	-0x108(%RSP,%RCX,8),%XMM2,%XMM2

    (102) 0x4ec5 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (102) 0x4ecb VMOVDQU	%XMM2,0x610(%RSP,%RCX,8)

    (102) 0x4ed4 VMOVDQU	0x628(%RSP,%RCX,8),%XMM3

    (102) 0x4edd VPALIGNR	$0x8,%XMM6,%XMM3,%XMM2

    (102) 0x4ee3 VPAND	%XMM3,%XMM9,%XMM4

    (102) 0x4ee7 VPTESTMQ	%XMM10,%XMM3,%K1

    (102) 0x4eed VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM4

    (102) 0x4ef4 VPSRLQ	$0x1,%XMM4,%XMM2

    (102) 0x4ef9 VPXOR	-0xf8(%RSP,%RCX,8),%XMM2,%XMM2

    (102) 0x4f02 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (102) 0x4f08 VMOVDQU	%XMM2,0x620(%RSP,%RCX,8)

    (102) 0x4f11 VMOVDQU	0x638(%RSP,%RCX,8),%XMM2

    (102) 0x4f1a VPALIGNR	$0x8,%XMM3,%XMM2,%XMM3

    (102) 0x4f20 VPAND	%XMM2,%XMM9,%XMM4

    (102) 0x4f24 VPTESTMQ	%XMM10,%XMM2,%K1

    (102) 0x4f2a VPTERNLOGQ	$-0x8,%XMM8,%XMM3,%XMM4

    (102) 0x4f31 VPSRLQ	$0x1,%XMM4,%XMM3

    (102) 0x4f36 VPXOR	-0xe8(%RSP,%RCX,8),%XMM3,%XMM3

    (102) 0x4f3f VPXORQ	%XMM11,%XMM3,%XMM3{%K1}

    (102) 0x4f45 VMOVDQU	%XMM3,0x630(%RSP,%RCX,8)

    (102) 0x4f4e ADD	$0xc,%RCX

    (102) 0x4f52 CMP	$0x27a,%RCX

    (102) 0x4f59 JNE	4de0

  (100) 0x4f5f MOV	0x19b0(%RSP),%RCX

  (100) 0x4f67 MOV	0x638(%RSP),%RBX

  (100) 0x4f6f XOR	%R13D,%R13D

  (100) 0x4f72 MOV	%EBX,%EDX

  (100) 0x4f74 AND	%R14,%RCX

  (100) 0x4f77 AND	$0x7ffffffe,%EDX

  (100) 0x4f7d OR	%RCX,%RDX

  (100) 0x4f80 MOV	%EBX,%ECX

  (100) 0x4f82 AND	$0x1,%ECX

  (100) 0x4f85 SHR	$0x1,%RDX

  (100) 0x4f88 XOR	0x1298(%RSP),%RDX

  (100) 0x4f90 NEG	%ECX

  (100) 0x4f92 AND	%R12D,%ECX

  (100) 0x4f95 XOR	%RDX,%RCX

  (100) 0x4f98 MOV	%RCX,0x19b0(%RSP)

  (100) 0x4fa0 JMP	4b30

0x4fb0 VDIVSS	%XMM1,%XMM0,%XMM0

0x4fb4 VMOVSS	0x4058(%RIP),%XMM2

0x4fbc VUCOMISS	%XMM2,%XMM0

0x4fc0 JAE	5956

0x4fc6 VMOVSS	%XMM0,(%R15,%R9,4)

0x4fcc VXORPS	%XMM0,%XMM0,%XMM0

0x4fd0 MOV	%R8,%RAX

0x4fd3 VMOVAPS	%XMM2,%XMM1

0x4fd7 JMP	5045

  (97) 0x4fe0 MOV	%R13,%RCX

  (97) 0x4fe3 INC	%R13

  (97) 0x4fe6 MOV	$0x200b,%EDX

  (97) 0x4feb MOV	%R13,0x19b8(%RSP)

  (97) 0x4ff3 MOV	0x638(%RSP,%RCX,8),%RCX

  (97) 0x4ffb BEXTR	%RDX,%RCX,%RDX

  (97) 0x5000 XOR	%RCX,%RDX

  (97) 0x5003 MOV	%EDX,%ECX

  (97) 0x5005 SAL	$0x7,%ECX

  (97) 0x5008 AND	$-0x62d3a980,%ECX

  (97) 0x500e XOR	%RDX,%RCX

  (97) 0x5011 MOV	%ECX,%EDX

  (97) 0x5013 SAL	$0xf,%EDX

  (97) 0x5016 AND	$-0x103a0000,%EDX

  (97) 0x501c XOR	%RCX,%RDX

  (97) 0x501f MOV	%RDX,%RCX

  (97) 0x5022 SHR	$0x12,%RCX

  (97) 0x5026 XOR	%RDX,%RCX

  (97) 0x5029 DEC	%RAX

  (97) 0x502c VCVTUSI2SS	%RCX,%XMM15,%XMM2

  (97) 0x5032 VFMADD231SS	%XMM2,%XMM1,%XMM0

  (97) 0x5037 VMULSS	0x3fc9(%RIP),%XMM1,%XMM1

  (97) 0x503f JE	5460

  (97) 0x5045 CMP	$0x270,%R13

  (97) 0x504c JB	4fe0

  (97) 0x504e VPBROADCASTQ	0x3fe8(%RIP),%ZMM14

  (97) 0x5058 VPBROADCASTQ	0x3fe6(%RIP),%ZMM15

  (97) 0x5062 VPBROADCASTQ	0x3fe4(%RIP),%ZMM16

  (97) 0x506c VPBROADCASTQ	0x3fe2(%RIP),%ZMM17

  (97) 0x5076 VPBROADCASTQ	%RBX,%ZMM2

  (97) 0x507c XOR	%ECX,%ECX

  (97) 0x507e XCHG	%AX,%AX

    (98) 0x5080 VMOVDQU64	0x640(%RSP,%RCX,8),%ZMM3

    (98) 0x5088 VMOVDQU64	0x680(%RSP,%RCX,8),%ZMM4

    (98) 0x5090 VMOVDQU64	0x6c0(%RSP,%RCX,8),%ZMM5

    (98) 0x5098 VALIGNQ	$0x7,%ZMM2,%ZMM3,%ZMM6

    (98) 0x509f VMOVDQU64	0x700(%RSP,%RCX,8),%ZMM2

    (98) 0x50a7 VALIGNQ	$0x7,%ZMM3,%ZMM4,%ZMM7

    (98) 0x50ae VALIGNQ	$0x7,%ZMM4,%ZMM5,%ZMM8

    (98) 0x50b5 VPANDQ	%ZMM15,%ZMM3,%ZMM10

    (98) 0x50bb VPANDQ	%ZMM15,%ZMM4,%ZMM11

    (98) 0x50c1 VPANDQ	%ZMM15,%ZMM5,%ZMM12

    (98) 0x50c7 VPTESTMQ	%ZMM16,%ZMM3,%K1

    (98) 0x50cd VPTESTMQ	%ZMM16,%ZMM4,%K2

    (98) 0x50d3 VPTESTMQ	%ZMM16,%ZMM5,%K3

    (98) 0x50d9 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM6,%ZMM10

    (98) 0x50e0 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM7,%ZMM11

    (98) 0x50e7 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM8,%ZMM12

    (98) 0x50ee VPSRLQ	$0x1,%ZMM10,%ZMM6

    (98) 0x50f5 VPSRLQ	$0x1,%ZMM11,%ZMM7

    (98) 0x50fc VPSRLQ	$0x1,%ZMM12,%ZMM8

    (98) 0x5103 VPXORQ	0x12a0(%RSP,%RCX,8),%ZMM6,%ZMM6

    (98) 0x510e VPXORQ	0x12e0(%RSP,%RCX,8),%ZMM7,%ZMM7

    (98) 0x5119 VPXORQ	0x1320(%RSP,%RCX,8),%ZMM8,%ZMM8

    (98) 0x5124 VALIGNQ	$0x7,%ZMM5,%ZMM2,%ZMM9

    (98) 0x512b VPANDQ	%ZMM15,%ZMM2,%ZMM13

    (98) 0x5131 VPTESTMQ	%ZMM16,%ZMM2,%K4

    (98) 0x5137 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM9,%ZMM13

    (98) 0x513e VPSRLQ	$0x1,%ZMM13,%ZMM9

    (98) 0x5145 VPXORQ	0x1360(%RSP,%RCX,8),%ZMM9,%ZMM9

    (98) 0x5150 VPXORQ	%ZMM17,%ZMM6,%ZMM6{%K1}

    (98) 0x5156 VPXORQ	%ZMM17,%ZMM7,%ZMM7{%K2}

    (98) 0x515c VPXORQ	%ZMM17,%ZMM8,%ZMM8{%K3}

    (98) 0x5162 VMOVDQU64	%ZMM6,0x638(%RSP,%RCX,8)

    (98) 0x516d VMOVDQU64	%ZMM7,0x678(%RSP,%RCX,8)

    (98) 0x5178 VMOVDQU64	%ZMM8,0x6b8(%RSP,%RCX,8)

    (98) 0x5183 VPXORQ	%ZMM17,%ZMM9,%ZMM9{%K4}

    (98) 0x5189 VMOVDQU64	%ZMM9,0x6f8(%RSP,%RCX,8)

    (98) 0x5194 ADD	$0x20,%RCX

    (98) 0x5198 CMP	$0xe0,%RCX

    (98) 0x519f JNE	5080

  (97) 0x51a5 MOV	0xd40(%RSP),%RDX

  (97) 0x51ad VEXTRACTI32X4	$0x3,%ZMM2,%XMM2

  (97) 0x51b4 MOV	0xd48(%RSP),%RCX

  (97) 0x51bc VPBROADCASTQ	0x3e7b(%RIP),%XMM8

  (97) 0x51c5 VPBROADCASTQ	0x3e7a(%RIP),%XMM9

  (97) 0x51ce VPBROADCASTQ	0x3e79(%RIP),%XMM10

  (97) 0x51d7 VPBROADCASTQ	0x3e78(%RIP),%XMM11

  (97) 0x51e0 VPEXTRQ	$0x1,%XMM2,%RSI

  (97) 0x51e6 AND	$-0x80000000,%RSI

  (97) 0x51ed MOV	%EDX,%EDI

  (97) 0x51ef AND	$0x7ffffffe,%EDI

  (97) 0x51f5 OR	%RSI,%RDI

  (97) 0x51f8 MOV	%EDX,%ESI

  (97) 0x51fa AND	$0x1,%ESI

  (97) 0x51fd AND	$-0x80000000,%RDX

  (97) 0x5204 SHR	$0x1,%RDI

  (97) 0x5207 XOR	0x19a0(%RSP),%RDI

  (97) 0x520f NEG	%ESI

  (97) 0x5211 AND	%R12D,%ESI

  (97) 0x5214 XOR	%RDI,%RSI

  (97) 0x5217 MOV	%RSI,0xd38(%RSP)

  (97) 0x521f MOV	%ECX,%ESI

  (97) 0x5221 AND	$0x7ffffffe,%ESI

  (97) 0x5227 OR	%RDX,%RSI

  (97) 0x522a MOV	%ECX,%EDX

  (97) 0x522c AND	$0x1,%EDX

  (97) 0x522f AND	$-0x80000000,%RCX

  (97) 0x5236 SHR	$0x1,%RSI

  (97) 0x5239 XOR	0x19a8(%RSP),%RSI

  (97) 0x5241 NEG	%EDX

  (97) 0x5243 AND	%R12D,%EDX

  (97) 0x5246 XOR	%RSI,%RDX

  (97) 0x5249 MOV	%RDX,0xd40(%RSP)

  (97) 0x5251 MOV	0xd50(%RSP),%RDX

  (97) 0x5259 MOV	%EDX,%ESI

  (97) 0x525b VPBROADCASTQ	%RDX,%XMM2

  (97) 0x5261 AND	$0x7ffffffe,%EDX

  (97) 0x5267 AND	$0x1,%ESI

  (97) 0x526a OR	%RCX,%RDX

  (97) 0x526d NEG	%ESI

  (97) 0x526f MOV	$0xee,%ECX

  (97) 0x5274 SHR	$0x1,%RDX

  (97) 0x5277 XOR	0x19b0(%RSP),%RDX

  (97) 0x527f AND	%R12D,%ESI

  (97) 0x5282 XOR	%RDX,%RSI

  (97) 0x5285 MOV	%RSI,0xd48(%RSP)

  (97) 0x528d NOPL	(%RAX)

    (99) 0x5290 VMOVDQU	0x5e8(%RSP,%RCX,8),%XMM3

    (99) 0x5299 VMOVDQU	0x5f8(%RSP,%RCX,8),%XMM4

    (99) 0x52a2 VMOVDQU	0x608(%RSP,%RCX,8),%XMM5

    (99) 0x52ab VMOVDQU	0x618(%RSP,%RCX,8),%XMM6

    (99) 0x52b4 VPALIGNR	$0x8,%XMM2,%XMM3,%XMM2

    (99) 0x52ba VPAND	%XMM3,%XMM9,%XMM7

    (99) 0x52be VPTESTMQ	%XMM10,%XMM3,%K1

    (99) 0x52c4 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM7

    (99) 0x52cb VPSRLQ	$0x1,%XMM7,%XMM2

    (99) 0x52d0 VPXOR	-0x138(%RSP,%RCX,8),%XMM2,%XMM2

    (99) 0x52d9 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (99) 0x52df VPTESTMQ	%XMM10,%XMM4,%K1

    (99) 0x52e5 VMOVDQU	%XMM2,0x5e0(%RSP,%RCX,8)

    (99) 0x52ee VPALIGNR	$0x8,%XMM3,%XMM4,%XMM2

    (99) 0x52f4 VPAND	%XMM4,%XMM9,%XMM3

    (99) 0x52f8 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

    (99) 0x52ff VPSRLQ	$0x1,%XMM3,%XMM2

    (99) 0x5304 VPXOR	-0x128(%RSP,%RCX,8),%XMM2,%XMM2

    (99) 0x530d VPAND	%XMM5,%XMM9,%XMM3

    (99) 0x5311 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (99) 0x5317 VPTESTMQ	%XMM10,%XMM5,%K1

    (99) 0x531d VMOVDQU	%XMM2,0x5f0(%RSP,%RCX,8)

    (99) 0x5326 VPALIGNR	$0x8,%XMM4,%XMM5,%XMM2

    (99) 0x532c VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

    (99) 0x5333 VPSRLQ	$0x1,%XMM3,%XMM2

    (99) 0x5338 VPXOR	-0x118(%RSP,%RCX,8),%XMM2,%XMM2

    (99) 0x5341 VPAND	%XMM6,%XMM9,%XMM3

    (99) 0x5345 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (99) 0x534b VPTESTMQ	%XMM10,%XMM6,%K1

    (99) 0x5351 VMOVDQU	%XMM2,0x600(%RSP,%RCX,8)

    (99) 0x535a VPALIGNR	$0x8,%XMM5,%XMM6,%XMM2

    (99) 0x5360 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

    (99) 0x5367 VPSRLQ	$0x1,%XMM3,%XMM2

    (99) 0x536c VPXOR	-0x108(%RSP,%RCX,8),%XMM2,%XMM2

    (99) 0x5375 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (99) 0x537b VMOVDQU	%XMM2,0x610(%RSP,%RCX,8)

    (99) 0x5384 VMOVDQU	0x628(%RSP,%RCX,8),%XMM3

    (99) 0x538d VPALIGNR	$0x8,%XMM6,%XMM3,%XMM2

    (99) 0x5393 VPAND	%XMM3,%XMM9,%XMM4

    (99) 0x5397 VPTESTMQ	%XMM10,%XMM3,%K1

    (99) 0x539d VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM4

    (99) 0x53a4 VPSRLQ	$0x1,%XMM4,%XMM2

    (99) 0x53a9 VPXOR	-0xf8(%RSP,%RCX,8),%XMM2,%XMM2

    (99) 0x53b2 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (99) 0x53b8 VMOVDQU	%XMM2,0x620(%RSP,%RCX,8)

    (99) 0x53c1 VMOVDQU	0x638(%RSP,%RCX,8),%XMM2

    (99) 0x53ca VPALIGNR	$0x8,%XMM3,%XMM2,%XMM3

    (99) 0x53d0 VPAND	%XMM2,%XMM9,%XMM4

    (99) 0x53d4 VPTESTMQ	%XMM10,%XMM2,%K1

    (99) 0x53da VPTERNLOGQ	$-0x8,%XMM8,%XMM3,%XMM4

    (99) 0x53e1 VPSRLQ	$0x1,%XMM4,%XMM3

    (99) 0x53e6 VPXOR	-0xe8(%RSP,%RCX,8),%XMM3,%XMM3

    (99) 0x53ef VPXORQ	%XMM11,%XMM3,%XMM3{%K1}

    (99) 0x53f5 VMOVDQU	%XMM3,0x630(%RSP,%RCX,8)

    (99) 0x53fe ADD	$0xc,%RCX

    (99) 0x5402 CMP	$0x27a,%RCX

    (99) 0x5409 JNE	5290

  (97) 0x540f MOV	0x19b0(%RSP),%RCX

  (97) 0x5417 MOV	0x638(%RSP),%RBX

  (97) 0x541f XOR	%R13D,%R13D

  (97) 0x5422 MOV	%EBX,%EDX

  (97) 0x5424 AND	%R14,%RCX

  (97) 0x5427 AND	$0x7ffffffe,%EDX

  (97) 0x542d OR	%RCX,%RDX

  (97) 0x5430 MOV	%EBX,%ECX

  (97) 0x5432 AND	$0x1,%ECX

  (97) 0x5435 SHR	$0x1,%RDX

  (97) 0x5438 XOR	0x1298(%RSP),%RDX

  (97) 0x5440 NEG	%ECX

  (97) 0x5442 AND	%R12D,%ECX

  (97) 0x5445 XOR	%RDX,%RCX

  (97) 0x5448 MOV	%RCX,0x19b0(%RSP)

  (97) 0x5450 JMP	4fe0

0x5460 VDIVSS	%XMM1,%XMM0,%XMM0

0x5464 VMOVSS	0x3ba8(%RIP),%XMM2

0x546c VUCOMISS	%XMM2,%XMM0

0x5470 JAE	5993

0x5476 MOV	0x178(%RSP),%RAX

0x547e VMOVAPS	%XMM2,%XMM1

0x5482 VMOVSS	%XMM0,(%RAX,%R9,4)

0x5488 VXORPS	%XMM0,%XMM0,%XMM0

0x548c MOV	%R8,%RAX

0x548f JMP	5505

  (94) 0x54a0 MOV	%R13,%RCX

  (94) 0x54a3 INC	%R13

  (94) 0x54a6 MOV	$0x200b,%EDX

  (94) 0x54ab MOV	%R13,0x19b8(%RSP)

  (94) 0x54b3 MOV	0x638(%RSP,%RCX,8),%RCX

  (94) 0x54bb BEXTR	%RDX,%RCX,%RDX

  (94) 0x54c0 XOR	%RCX,%RDX

  (94) 0x54c3 MOV	%EDX,%ECX

  (94) 0x54c5 SAL	$0x7,%ECX

  (94) 0x54c8 AND	$-0x62d3a980,%ECX

  (94) 0x54ce XOR	%RDX,%RCX

  (94) 0x54d1 MOV	%ECX,%EDX

  (94) 0x54d3 SAL	$0xf,%EDX

  (94) 0x54d6 AND	$-0x103a0000,%EDX

  (94) 0x54dc XOR	%RCX,%RDX

  (94) 0x54df MOV	%RDX,%RCX

  (94) 0x54e2 SHR	$0x12,%RCX

  (94) 0x54e6 XOR	%RDX,%RCX

  (94) 0x54e9 DEC	%RAX

  (94) 0x54ec VCVTUSI2SS	%RCX,%XMM15,%XMM2

  (94) 0x54f2 VFMADD231SS	%XMM2,%XMM1,%XMM0

  (94) 0x54f7 VMULSS	0x3b09(%RIP),%XMM1,%XMM1

  (94) 0x54ff JE	5920

  (94) 0x5505 CMP	$0x270,%R13

  (94) 0x550c JB	54a0

  (94) 0x550e VPBROADCASTQ	0x3b28(%RIP),%ZMM14

  (94) 0x5518 VPBROADCASTQ	0x3b26(%RIP),%ZMM15

  (94) 0x5522 VPBROADCASTQ	0x3b24(%RIP),%ZMM16

  (94) 0x552c VPBROADCASTQ	0x3b22(%RIP),%ZMM17

  (94) 0x5536 VPBROADCASTQ	%RBX,%ZMM2

  (94) 0x553c XOR	%ECX,%ECX

  (94) 0x553e XCHG	%AX,%AX

    (95) 0x5540 VMOVDQU64	0x640(%RSP,%RCX,8),%ZMM3

    (95) 0x5548 VMOVDQU64	0x680(%RSP,%RCX,8),%ZMM4

    (95) 0x5550 VMOVDQU64	0x6c0(%RSP,%RCX,8),%ZMM5

    (95) 0x5558 VALIGNQ	$0x7,%ZMM2,%ZMM3,%ZMM6

    (95) 0x555f VMOVDQU64	0x700(%RSP,%RCX,8),%ZMM2

    (95) 0x5567 VALIGNQ	$0x7,%ZMM3,%ZMM4,%ZMM7

    (95) 0x556e VALIGNQ	$0x7,%ZMM4,%ZMM5,%ZMM8

    (95) 0x5575 VPANDQ	%ZMM15,%ZMM3,%ZMM10

    (95) 0x557b VPANDQ	%ZMM15,%ZMM4,%ZMM11

    (95) 0x5581 VPANDQ	%ZMM15,%ZMM5,%ZMM12

    (95) 0x5587 VPTESTMQ	%ZMM16,%ZMM3,%K1

    (95) 0x558d VPTESTMQ	%ZMM16,%ZMM4,%K2

    (95) 0x5593 VPTESTMQ	%ZMM16,%ZMM5,%K3

    (95) 0x5599 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM6,%ZMM10

    (95) 0x55a0 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM7,%ZMM11

    (95) 0x55a7 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM8,%ZMM12

    (95) 0x55ae VPSRLQ	$0x1,%ZMM10,%ZMM6

    (95) 0x55b5 VPSRLQ	$0x1,%ZMM11,%ZMM7

    (95) 0x55bc VPSRLQ	$0x1,%ZMM12,%ZMM8

    (95) 0x55c3 VPXORQ	0x12a0(%RSP,%RCX,8),%ZMM6,%ZMM6

    (95) 0x55ce VPXORQ	0x12e0(%RSP,%RCX,8),%ZMM7,%ZMM7

    (95) 0x55d9 VPXORQ	0x1320(%RSP,%RCX,8),%ZMM8,%ZMM8

    (95) 0x55e4 VALIGNQ	$0x7,%ZMM5,%ZMM2,%ZMM9

    (95) 0x55eb VPANDQ	%ZMM15,%ZMM2,%ZMM13

    (95) 0x55f1 VPTESTMQ	%ZMM16,%ZMM2,%K4

    (95) 0x55f7 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM9,%ZMM13

    (95) 0x55fe VPSRLQ	$0x1,%ZMM13,%ZMM9

    (95) 0x5605 VPXORQ	0x1360(%RSP,%RCX,8),%ZMM9,%ZMM9

    (95) 0x5610 VPXORQ	%ZMM17,%ZMM6,%ZMM6{%K1}

    (95) 0x5616 VPXORQ	%ZMM17,%ZMM7,%ZMM7{%K2}

    (95) 0x561c VPXORQ	%ZMM17,%ZMM8,%ZMM8{%K3}

    (95) 0x5622 VMOVDQU64	%ZMM6,0x638(%RSP,%RCX,8)

    (95) 0x562d VMOVDQU64	%ZMM7,0x678(%RSP,%RCX,8)

    (95) 0x5638 VMOVDQU64	%ZMM8,0x6b8(%RSP,%RCX,8)

    (95) 0x5643 VPXORQ	%ZMM17,%ZMM9,%ZMM9{%K4}

    (95) 0x5649 VMOVDQU64	%ZMM9,0x6f8(%RSP,%RCX,8)

    (95) 0x5654 ADD	$0x20,%RCX

    (95) 0x5658 CMP	$0xe0,%RCX

    (95) 0x565f JNE	5540

  (94) 0x5665 MOV	0xd40(%RSP),%RDX

  (94) 0x566d VEXTRACTI32X4	$0x3,%ZMM2,%XMM2

  (94) 0x5674 MOV	0xd48(%RSP),%RCX

  (94) 0x567c VPBROADCASTQ	0x39bb(%RIP),%XMM8

  (94) 0x5685 VPBROADCASTQ	0x39ba(%RIP),%XMM9

  (94) 0x568e VPBROADCASTQ	0x39b9(%RIP),%XMM10

  (94) 0x5697 VPBROADCASTQ	0x39b8(%RIP),%XMM11

  (94) 0x56a0 VPEXTRQ	$0x1,%XMM2,%RSI

  (94) 0x56a6 AND	$-0x80000000,%RSI

  (94) 0x56ad MOV	%EDX,%EDI

  (94) 0x56af AND	$0x7ffffffe,%EDI

  (94) 0x56b5 OR	%RSI,%RDI

  (94) 0x56b8 MOV	%EDX,%ESI

  (94) 0x56ba AND	$0x1,%ESI

  (94) 0x56bd AND	$-0x80000000,%RDX

  (94) 0x56c4 SHR	$0x1,%RDI

  (94) 0x56c7 XOR	0x19a0(%RSP),%RDI

  (94) 0x56cf NEG	%ESI

  (94) 0x56d1 AND	%R12D,%ESI

  (94) 0x56d4 XOR	%RDI,%RSI

  (94) 0x56d7 MOV	%RSI,0xd38(%RSP)

  (94) 0x56df MOV	%ECX,%ESI

  (94) 0x56e1 AND	$0x7ffffffe,%ESI

  (94) 0x56e7 OR	%RDX,%RSI

  (94) 0x56ea MOV	%ECX,%EDX

  (94) 0x56ec AND	$0x1,%EDX

  (94) 0x56ef AND	$-0x80000000,%RCX

  (94) 0x56f6 SHR	$0x1,%RSI

  (94) 0x56f9 XOR	0x19a8(%RSP),%RSI

  (94) 0x5701 NEG	%EDX

  (94) 0x5703 AND	%R12D,%EDX

  (94) 0x5706 XOR	%RSI,%RDX

  (94) 0x5709 MOV	%RDX,0xd40(%RSP)

  (94) 0x5711 MOV	0xd50(%RSP),%RDX

  (94) 0x5719 MOV	%EDX,%ESI

  (94) 0x571b VPBROADCASTQ	%RDX,%XMM2

  (94) 0x5721 AND	$0x7ffffffe,%EDX

  (94) 0x5727 AND	$0x1,%ESI

  (94) 0x572a OR	%RCX,%RDX

  (94) 0x572d NEG	%ESI

  (94) 0x572f MOV	$0xee,%ECX

  (94) 0x5734 SHR	$0x1,%RDX

  (94) 0x5737 XOR	0x19b0(%RSP),%RDX

  (94) 0x573f AND	%R12D,%ESI

  (94) 0x5742 XOR	%RDX,%RSI

  (94) 0x5745 MOV	%RSI,0xd48(%RSP)

  (94) 0x574d NOPL	(%RAX)

    (96) 0x5750 VMOVDQU	0x5e8(%RSP,%RCX,8),%XMM3

    (96) 0x5759 VMOVDQU	0x5f8(%RSP,%RCX,8),%XMM4

    (96) 0x5762 VMOVDQU	0x608(%RSP,%RCX,8),%XMM5

    (96) 0x576b VMOVDQU	0x618(%RSP,%RCX,8),%XMM6

    (96) 0x5774 VPALIGNR	$0x8,%XMM2,%XMM3,%XMM2

    (96) 0x577a VPAND	%XMM3,%XMM9,%XMM7

    (96) 0x577e VPTESTMQ	%XMM10,%XMM3,%K1

    (96) 0x5784 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM7

    (96) 0x578b VPSRLQ	$0x1,%XMM7,%XMM2

    (96) 0x5790 VPXOR	-0x138(%RSP,%RCX,8),%XMM2,%XMM2

    (96) 0x5799 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (96) 0x579f VPTESTMQ	%XMM10,%XMM4,%K1

    (96) 0x57a5 VMOVDQU	%XMM2,0x5e0(%RSP,%RCX,8)

    (96) 0x57ae VPALIGNR	$0x8,%XMM3,%XMM4,%XMM2

    (96) 0x57b4 VPAND	%XMM4,%XMM9,%XMM3

    (96) 0x57b8 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

    (96) 0x57bf VPSRLQ	$0x1,%XMM3,%XMM2

    (96) 0x57c4 VPXOR	-0x128(%RSP,%RCX,8),%XMM2,%XMM2

    (96) 0x57cd VPAND	%XMM5,%XMM9,%XMM3

    (96) 0x57d1 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (96) 0x57d7 VPTESTMQ	%XMM10,%XMM5,%K1

    (96) 0x57dd VMOVDQU	%XMM2,0x5f0(%RSP,%RCX,8)

    (96) 0x57e6 VPALIGNR	$0x8,%XMM4,%XMM5,%XMM2

    (96) 0x57ec VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

    (96) 0x57f3 VPSRLQ	$0x1,%XMM3,%XMM2

    (96) 0x57f8 VPXOR	-0x118(%RSP,%RCX,8),%XMM2,%XMM2

    (96) 0x5801 VPAND	%XMM6,%XMM9,%XMM3

    (96) 0x5805 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (96) 0x580b VPTESTMQ	%XMM10,%XMM6,%K1

    (96) 0x5811 VMOVDQU	%XMM2,0x600(%RSP,%RCX,8)

    (96) 0x581a VPALIGNR	$0x8,%XMM5,%XMM6,%XMM2

    (96) 0x5820 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

    (96) 0x5827 VPSRLQ	$0x1,%XMM3,%XMM2

    (96) 0x582c VPXOR	-0x108(%RSP,%RCX,8),%XMM2,%XMM2

    (96) 0x5835 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (96) 0x583b VMOVDQU	%XMM2,0x610(%RSP,%RCX,8)

    (96) 0x5844 VMOVDQU	0x628(%RSP,%RCX,8),%XMM3

    (96) 0x584d VPALIGNR	$0x8,%XMM6,%XMM3,%XMM2

    (96) 0x5853 VPAND	%XMM3,%XMM9,%XMM4

    (96) 0x5857 VPTESTMQ	%XMM10,%XMM3,%K1

    (96) 0x585d VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM4

    (96) 0x5864 VPSRLQ	$0x1,%XMM4,%XMM2

    (96) 0x5869 VPXOR	-0xf8(%RSP,%RCX,8),%XMM2,%XMM2

    (96) 0x5872 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (96) 0x5878 VMOVDQU	%XMM2,0x620(%RSP,%RCX,8)

    (96) 0x5881 VMOVDQU	0x638(%RSP,%RCX,8),%XMM2

    (96) 0x588a VPALIGNR	$0x8,%XMM3,%XMM2,%XMM3

    (96) 0x5890 VPAND	%XMM2,%XMM9,%XMM4

    (96) 0x5894 VPTESTMQ	%XMM10,%XMM2,%K1

    (96) 0x589a VPTERNLOGQ	$-0x8,%XMM8,%XMM3,%XMM4

    (96) 0x58a1 VPSRLQ	$0x1,%XMM4,%XMM3

    (96) 0x58a6 VPXOR	-0xe8(%RSP,%RCX,8),%XMM3,%XMM3

    (96) 0x58af VPXORQ	%XMM11,%XMM3,%XMM3{%K1}

    (96) 0x58b5 VMOVDQU	%XMM3,0x630(%RSP,%RCX,8)

    (96) 0x58be ADD	$0xc,%RCX

    (96) 0x58c2 CMP	$0x27a,%RCX

    (96) 0x58c9 JNE	5750

  (94) 0x58cf MOV	0x19b0(%RSP),%RCX

  (94) 0x58d7 MOV	0x638(%RSP),%RBX

  (94) 0x58df XOR	%R13D,%R13D

  (94) 0x58e2 MOV	%EBX,%EDX

  (94) 0x58e4 AND	%R14,%RCX

  (94) 0x58e7 AND	$0x7ffffffe,%EDX

  (94) 0x58ed OR	%RCX,%RDX

  (94) 0x58f0 MOV	%EBX,%ECX

  (94) 0x58f2 AND	$0x1,%ECX

  (94) 0x58f5 SHR	$0x1,%RDX

  (94) 0x58f8 XOR	0x1298(%RSP),%RDX

  (94) 0x5900 NEG	%ECX

  (94) 0x5902 AND	%R12D,%ECX

  (94) 0x5905 XOR	%RDX,%RCX

  (94) 0x5908 MOV	%RCX,0x19b0(%RSP)

  (94) 0x5910 JMP	54a0

0x5920 VDIVSS	%XMM1,%XMM0,%XMM0

0x5924 VUCOMISS	0x36e8(%RIP),%XMM0

0x592c JAE	59d0

0x5932 MOV	0x1f0(%RSP),%RAX

0x593a VMOVSS	%XMM0,(%RAX,%R9,4)

0x5940 INC	%R9

0x5943 CMP	0x4f0(%RSP),%R9

0x594b JNE	4b10

0x5956 VXORPS	%XMM1,%XMM1,%XMM1

0x595a VMOVAPS	%XMM2,%XMM0

0x595e MOV	%R8,0x2c0(%RSP)

0x5966 MOV	%R9,0x200(%RSP)

0x596e VZEROUPPER

0x5971 CALL	10a0 <nextafterf@plt>

0x5976 VMOVSS	0x3696(%RIP),%XMM2

0x597e MOV	0x200(%RSP),%R9

0x5986 MOV	0x2c0(%RSP),%R8

0x598e JMP	4fc6

0x5993 VXORPS	%XMM1,%XMM1,%XMM1

0x5997 VMOVAPS	%XMM2,%XMM0

0x599b MOV	%R8,0x2c0(%RSP)

0x59a3 MOV	%R9,0x200(%RSP)

0x59ab VZEROUPPER

0x59ae CALL	10a0 <nextafterf@plt>

0x59b3 VMOVSS	0x3659(%RIP),%XMM2

0x59bb MOV	0x200(%RSP),%R9

0x59c3 MOV	0x2c0(%RSP),%R8

0x59cb JMP	5476

0x59d0 VMOVSS	0x363c(%RIP),%XMM0

0x59d8 VXORPS	%XMM1,%XMM1,%XMM1

0x59dc MOV	%R8,0x2c0(%RSP)

0x59e4 MOV	%R9,0x200(%RSP)

0x59ec VZEROUPPER

0x59ef CALL	10a0 <nextafterf@plt>

0x59f4 MOV	0x200(%RSP),%R9

0x59fc MOV	0x2c0(%RSP),%R8

0x5a04 JMP	5932

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath: 1661 - 1661

--------------------------------------------------------------------------------

1661:   { return __builtin_nextafterf(__x, __y); }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 401 - 3370

--------------------------------------------------------------------------------

401:       for (size_t __k = 0; __k < (__n - __m); ++__k)

402:         {

403: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

404: 			   | (_M_x[__k + 1] & __lower_mask));

405: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

406: 		       ^ ((__y & 0x01) ? __a : 0));

407:         }

408:

409:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

410: 	{

411: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

412: 			   | (_M_x[__k + 1] & __lower_mask));

413: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

414: 		       ^ ((__y & 0x01) ? __a : 0));

415: 	}

416:

417:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

418: 		       | (_M_x[0] & __lower_mask));

419:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

420: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

455:       if (_M_p >= state_size)

456: 	_M_gen_rand();

457:

458:       // Calculate o(x(i)).

459:       result_type __z = _M_x[_M_p++];

460:       __z ^= (__z >> __u) & __d;

461:       __z ^= (__z << __s) & __b;

462:       __z ^= (__z << __t) & __c;

463:       __z ^= (__z >> __l);

[...]

3364:       for (size_t __k = __m; __k != 0; --__k)

3365: 	{

3366: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3367: 	  __tmp *= __r;

3368: 	}

3369:       __ret = __sum / __tmp;

3370:       if (__builtin_expect(__ret >= _RealType(1), 0))

/home/eoseret/llm-attention/attention_v2.cpp: 164 - 167

--------------------------------------------------------------------------------

164:       for (size_t i = 0; i < elemsW; ++i) {

165:          h_WQ[i] = dist(rng);

166:          h_WK[i] = dist(rng);

167:          h_WV[i] = dist(rng);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.10
CQA speedup if FP arith vectorized	1.70
CQA speedup if fully vectorized	12.31
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	micro-operation queue,
Function	main
Source	cmath:1661-1661,random.tcc:3369-3370,attention_v2.cpp:164-167
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.25
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	4.84
CQA cycles if fully vectorized	0.67
Front-end cycles	8.25
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	3.33
P4 cycles	3.33
P5 cycles	3.33
P6 cycles	6.25
P7 cycles	6.25
P8 cycles	6.25
P9 cycles	6.25
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	3.00
P15 cycles	3.00
DIV/SQRT cycles	7.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	66.00
Nb loads	16.00
Nb stores	9.00
Nb stack references	5.00
FLOP/cycle	0.36
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.39
Bytes prefetched	0.00
Bytes loaded	100.00
Bytes stored	60.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	35.14
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	81.25
Vector-efficiency ratio all	14.36
Vector-efficiency ratio load	8.13
Vector-efficiency ratio store	10.42
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	21.48

Metric	Value
CQA speedup if no scalar integer	1.10
CQA speedup if FP arith vectorized	1.70
CQA speedup if fully vectorized	12.31
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	micro-operation queue,
Function	main
Source	cmath:1661-1661,random.tcc:3369-3370,attention_v2.cpp:164-167
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.25
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	4.84
CQA cycles if fully vectorized	0.67
Front-end cycles	8.25
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	3.33
P4 cycles	3.33
P5 cycles	3.33
P6 cycles	6.25
P7 cycles	6.25
P8 cycles	6.25
P9 cycles	6.25
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	3.00
P15 cycles	3.00
DIV/SQRT cycles	7.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	66.00
Nb loads	16.00
Nb stores	9.00
Nb stack references	5.00
FLOP/cycle	0.36
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.39
Bytes prefetched	0.00
Bytes loaded	100.00
Bytes stored	60.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	35.14
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	81.25
Vector-efficiency ratio all	14.36
Vector-efficiency ratio load	8.13
Vector-efficiency ratio store	10.42
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	21.48

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:164-167
Module	attention-clang-znver5-512

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3364-3370
/home/eoseret/llm-attention/attention_v2.cpp:164-167

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 64 paths individually, rerun with max-paths=64
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 64 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.25 to 7.50 cycles (1.10x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 8.25 to 0.67 cycles (12.31x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

nextafterf@plt: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISS: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: divide

The binary loop is loading 100 bytes (25 single precision FP elements). The binary loop is storing 60 bytes (15 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	60
nb uops	66
loop length	335
used x86 registers	5
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.25 cycles
front end	8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	3.33	3.33	3.33	6.25	6.25	6.25	6.25	1.50	1.50	1.50	1.50	3.00	3.00
cycles	0.67	0.67	0.67	3.33	3.33	3.33	6.25	6.25	6.25	6.25	1.50	1.50	1.50	1.50	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

7.50

Cycles summary

Front-end	8.25
Dispatch	6.25
DIV/SQRT	7.50
Overall L1	8.25

Vectorization ratios

INT

all	25%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	40%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	76%

INT+FP

all	35%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	81%

Vector efficiency ratios

INT

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	13%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	20%

INT+FP

all	14%
load	8%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.25 cycles. At this rate:

4% of peak load performance is reached (12.12 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 4b10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVSS 0x44fc(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 4b95 <main+0x11e5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
VMOVSS 0x4058(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VUCOMISS %XMM2,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	0.50	scal (6.3%)
JAE 5956 <main+0x1fa6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VMOVSS %XMM0,(%R15,%R9,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVAPS %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 5045 <main+0x1695>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
VMOVSS 0x3ba8(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VUCOMISS %XMM2,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	0.50	scal (6.3%)
JAE 5993 <main+0x1fe3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x178(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVAPS %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 5505 <main+0x1b55>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
VUCOMISS 0x36e8(%RIP),%XMM0	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	7	0.50	scal (6.3%)
JAE 59d0 <main+0x2020>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x1f0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x4f0(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JNE 4b10 <main+0x1160>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,0x2c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x200(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 10a0 <nextafterf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVSS 0x3696(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV 0x200(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x2c0(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JMP 4fc6 <main+0x1616>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,0x2c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x200(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 10a0 <nextafterf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVSS 0x3659(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV 0x200(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x2c0(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JMP 5476 <main+0x1ac6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VMOVSS 0x363c(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,0x2c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x200(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 10a0 <nextafterf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV 0x200(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x2c0(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JMP 5932 <main+0x1f82>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:164-167
Module	attention-clang-znver5-512

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3364-3370
/home/eoseret/llm-attention/attention_v2.cpp:164-167

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 64 paths individually, rerun with max-paths=64
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.25 to 7.50 cycles (1.10x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

nextafterf@plt: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISS: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: divide

The binary loop is loading 100 bytes (25 single precision FP elements). The binary loop is storing 60 bytes (15 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	60
nb uops	66
loop length	335
used x86 registers	5
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.25 cycles
front end	8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	3.33	3.33	3.33	6.25	6.25	6.25	6.25	1.50	1.50	1.50	1.50	3.00	3.00
cycles	0.67	0.67	0.67	3.33	3.33	3.33	6.25	6.25	6.25	6.25	1.50	1.50	1.50	1.50	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

7.50

Cycles summary

Front-end	8.25
Dispatch	6.25
DIV/SQRT	7.50
Overall L1	8.25

Vectorization ratios

INT

all	25%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	40%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	76%

INT+FP

all	35%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	81%

Vector efficiency ratios

INT

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	13%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	20%

INT+FP

all	14%
load	8%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.25 cycles. At this rate:

4% of peak load performance is reached (12.12 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 4b10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVSS 0x44fc(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 4b95 <main+0x11e5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
VMOVSS 0x4058(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VUCOMISS %XMM2,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	0.50	scal (6.3%)
JAE 5956 <main+0x1fa6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VMOVSS %XMM0,(%R15,%R9,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVAPS %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 5045 <main+0x1695>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
VMOVSS 0x3ba8(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VUCOMISS %XMM2,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	0.50	scal (6.3%)
JAE 5993 <main+0x1fe3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x178(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVAPS %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 5505 <main+0x1b55>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
VUCOMISS 0x36e8(%RIP),%XMM0	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	7	0.50	scal (6.3%)
JAE 59d0 <main+0x2020>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x1f0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x4f0(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JNE 4b10 <main+0x1160>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,0x2c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x200(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 10a0 <nextafterf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVSS 0x3696(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV 0x200(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x2c0(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JMP 4fc6 <main+0x1616>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,0x2c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x200(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 10a0 <nextafterf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVSS 0x3659(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV 0x200(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x2c0(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JMP 5476 <main+0x1ac6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VMOVSS 0x363c(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,0x2c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x200(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 10a0 <nextafterf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV 0x200(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x2c0(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JMP 5932 <main+0x1f82>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code