OV - attention-clang-znver5-512 - Loop 89 - attention-clang-znver5-512

	Loop Id: 89	Module: attention-clang-znver5-512	Source: attention_v2.cpp:26-33	Coverage: 0.63%

0x5a90 MOV	0x200(%RSP),%RAX

0x5a98 MOV	0x98(%RSP),%RDX

0x5aa0 VCVTSD2SS	%XMM0,%XMM0,%XMM0

0x5aa4 LEA	(%RAX,%RSI,1),%R9D

0x5aa8 INC	%RSI

0x5aab VMOVSS	%XMM0,(%RDX,%R9,4)

0x5ab1 MOV	0x30(%RSP),%R9

0x5ab6 CMP	%R9,%RSI

0x5ab9 JE	5a30

0x5abf CMP	$0x3,%R9D

0x5ac3 JBE	5ae2

0x5ac5 MOV	%ESI,%R9D

0x5ac8 ADD	0xb8(%RSP),%R9D

0x5ad0 SETB	%R9B

0x5ad4 OR	0x180(%RSP),%R9B

0x5adc JE	88b4

0x5ae2 CMPQ	$0x7,0xb8(%RSP)

0x5aeb VXORPS	%XMM0,%XMM0,%XMM0

0x5aef MOV	%RSI,0x2c0(%RSP)

0x5af7 JAE	5b10

0x5af9 MOV	0x88(%RSP),%R14

0x5b01 MOV	0x70(%RSP),%R8

0x5b06 XOR	%R9D,%R9D

0x5b09 JMP	5c94

0x5b10 MOV	%RSI,%R10

0x5b13 MOV	0x370(%RSP),%RAX

0x5b1b MOV	0x418(%RSP),%RDI

0x5b23 MOV	0x410(%RSP),%RSI

0x5b2b MOV	0x408(%RSP),%R12

0x5b33 MOV	0x400(%RSP),%R13

0x5b3b MOV	0x3f8(%RSP),%R15

0x5b43 MOV	0x88(%RSP),%R14

0x5b4b MOV	0x70(%RSP),%R8

0x5b50 MOV	0x3f0(%RSP),%RDX

0x5b58 XOR	%R9D,%R9D

0x5b5b NOPL	(%RAX,%RAX,1)

  (42) 0x5b60 LEA	(%RCX,%R9,1),%R11D

  (42) 0x5b64 VMOVSS	(%R8,%R11,4),%XMM1

  (42) 0x5b6a MOV	%R10D,%R11D

  (42) 0x5b6d VMOVSS	(%R14,%R11,4),%XMM2

  (42) 0x5b73 LEA	0x1(%RCX,%R9,1),%R11D

  (42) 0x5b78 VMOVSS	(%R8,%R11,4),%XMM3

  (42) 0x5b7e LEA	(%RBX,%R10,1),%R11D

  (42) 0x5b82 LEA	0x6(%RCX,%R9,1),%EBX

  (42) 0x5b87 VMOVSS	(%R14,%R11,4),%XMM4

  (42) 0x5b8d LEA	0x2(%RCX,%R9,1),%R11D

  (42) 0x5b92 VMOVSS	(%R8,%RBX,4),%XMM13

  (42) 0x5b98 MOV	0x38(%RSP),%RBX

  (42) 0x5b9d VMOVSS	(%R8,%R11,4),%XMM5

  (42) 0x5ba3 LEA	(%RSI,%R10,1),%R11D

  (42) 0x5ba7 VMOVSS	(%R14,%R11,4),%XMM6

  (42) 0x5bad LEA	0x3(%RCX,%R9,1),%R11D

  (42) 0x5bb2 VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (42) 0x5bb6 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (42) 0x5bba VMOVSS	(%R8,%R11,4),%XMM7

  (42) 0x5bc0 LEA	(%RDX,%R10,1),%R11D

  (42) 0x5bc4 VMOVSS	(%R14,%R11,4),%XMM8

  (42) 0x5bca LEA	0x4(%RCX,%R9,1),%R11D

  (42) 0x5bcf VFMADD213SD	%XMM0,%XMM1,%XMM2

  (42) 0x5bd4 VCVTSS2SD	%XMM3,%XMM3,%XMM0

  (42) 0x5bd8 VMOVSS	(%R8,%R11,4),%XMM9

  (42) 0x5bde LEA	(%R15,%R10,1),%R11D

  (42) 0x5be2 VMOVSS	(%R14,%R11,4),%XMM10

  (42) 0x5be8 LEA	0x5(%RCX,%R9,1),%R11D

  (42) 0x5bed VCVTSS2SD	%XMM4,%XMM4,%XMM1

  (42) 0x5bf1 VMOVSS	(%R8,%R11,4),%XMM11

  (42) 0x5bf7 LEA	(%R13,%R10,1),%R11D

  (42) 0x5bfc VMOVSS	(%R14,%R11,4),%XMM12

  (42) 0x5c02 LEA	(%R12,%R10,1),%R11D

  (42) 0x5c06 VMOVSS	(%R14,%R11,4),%XMM14

  (42) 0x5c0c LEA	0x7(%RCX,%R9,1),%R11D

  (42) 0x5c11 ADD	$0x8,%R9

  (42) 0x5c15 VFMADD213SD	%XMM2,%XMM0,%XMM1

  (42) 0x5c1a VCVTSS2SD	%XMM5,%XMM5,%XMM0

  (42) 0x5c1e VMOVSS	(%R8,%R11,4),%XMM15

  (42) 0x5c24 LEA	(%RDI,%R10,1),%R11D

  (42) 0x5c28 ADD	%RAX,%R10

  (42) 0x5c2b VMOVSS	(%R14,%R11,4),%XMM16

  (42) 0x5c32 VCVTSS2SD	%XMM6,%XMM6,%XMM2

  (42) 0x5c36 VFMADD213SD	%XMM1,%XMM0,%XMM2

  (42) 0x5c3b VCVTSS2SD	%XMM7,%XMM7,%XMM0

  (42) 0x5c3f VCVTSS2SD	%XMM8,%XMM8,%XMM1

  (42) 0x5c44 VFMADD213SD	%XMM2,%XMM0,%XMM1

  (42) 0x5c49 VCVTSS2SD	%XMM9,%XMM9,%XMM0

  (42) 0x5c4e VCVTSS2SD	%XMM10,%XMM10,%XMM2

  (42) 0x5c53 VFMADD213SD	%XMM1,%XMM0,%XMM2

  (42) 0x5c58 VCVTSS2SD	%XMM11,%XMM11,%XMM0

  (42) 0x5c5d VCVTSS2SD	%XMM12,%XMM12,%XMM1

  (42) 0x5c62 VFMADD213SD	%XMM2,%XMM0,%XMM1

  (42) 0x5c67 VCVTSS2SD	%XMM13,%XMM13,%XMM0

  (42) 0x5c6c VCVTSS2SD	%XMM14,%XMM14,%XMM2

  (42) 0x5c71 VFMADD213SD	%XMM1,%XMM0,%XMM2

  (42) 0x5c76 VCVTSS2SD	%XMM15,%XMM15,%XMM1

  (42) 0x5c7b VCVTSS2SD	%XMM16,%XMM16,%XMM0

  (42) 0x5c81 VFMADD213SD	%XMM2,%XMM1,%XMM0

  (42) 0x5c86 CMP	%R9,0x380(%RSP)

  (42) 0x5c8e JNE	5b60

0x5c94 CMPQ	$0,0x378(%RSP)

0x5c9d MOV	0x2c0(%RSP),%RSI

0x5ca5 JE	5a90

0x5cab MOV	0x378(%RSP),%R11

0x5cb3 MOV	%RBX,%R10

0x5cb6 IMUL	%R9,%R10

0x5cba ADD	%ECX,%R9D

0x5cbd ADD	%RSI,%R10

  (90) 0x5cc0 MOV	%R9D,%EBX

  (90) 0x5cc3 VMOVSS	(%R8,%RBX,4),%XMM1

  (90) 0x5cc9 MOV	%R10D,%EBX

  (90) 0x5ccc VMOVSS	(%R14,%RBX,4),%XMM2

  (90) 0x5cd2 MOV	0x38(%RSP),%RBX

  (90) 0x5cd7 INC	%R9D

  (90) 0x5cda ADD	%RBX,%R10

  (90) 0x5cdd DEC	%R11

  (90) 0x5ce0 VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (90) 0x5ce4 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (90) 0x5ce8 VFMADD231SD	%XMM2,%XMM1,%XMM0

  (90) 0x5ced JNE	5cc0

0x5cef JMP	5a90

/home/eoseret/llm-attention/attention_v2.cpp: 26 - 33

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.93
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	10.35
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.83
Bottlenecks	micro-operation queue, P6, P7, P8, P9,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.50
CQA cycles if no scalar integer	1.88
CQA cycles if FP arith vectorized	5.50
CQA cycles if fully vectorized	0.53
Front-end cycles	5.50
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	5.50
P7 cycles	5.50
P8 cycles	5.50
P9 cycles	5.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	44.00
Nb loads	20.00
Nb stores	2.00
Nb stack references	16.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.27
Bytes prefetched	0.00
Bytes loaded	149.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	5.88
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	16.67
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.54

Metric	Value
CQA speedup if no scalar integer	2.93
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	10.35
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.83
Bottlenecks	micro-operation queue, P6, P7, P8, P9,
Function	main
Source	attention_v2.cpp:26-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.50
CQA cycles if no scalar integer	1.88
CQA cycles if FP arith vectorized	5.50
CQA cycles if fully vectorized	0.53
Front-end cycles	5.50
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	5.50
P7 cycles	5.50
P8 cycles	5.50
P9 cycles	5.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	44.00
Nb loads	20.00
Nb stores	2.00
Nb stack references	16.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.27
Bytes prefetched	0.00
Bytes loaded	149.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	5.88
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	16.67
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.54

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-clang-znver5-512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-27,30,33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.50 to 1.88 cycles (2.93x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.50 to 0.53 cycles (10.35x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 5.50 to 3.00 cycles (1.83x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 149 bytes. The binary loop is storing 12 bytes.

General properties

nb instructions	45
nb uops	44
loop length	255
used x86 registers	15
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	16

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.50 cycles
front end	5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.00	3.00	3.00	3.00	3.00	3.00	5.50	5.50	5.50	5.50	0.00	0.00	0.50	0.50	0.50	0.50
cycles	3.00	3.00	3.00	3.00	3.00	3.00	5.50	5.50	5.50	5.50	0.00	0.00	0.50	0.50	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.50
Dispatch	5.50
Overall L1	5.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.50 cycles. At this rate:

10% of peak load performance is reached (27.09 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.18 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.50 to 3.00 cycles (1.83x speedup).

ASM code

In the binary file, the address of the loop is: 5abf

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0x200(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x98(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VCVTSD2SS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
LEA (%RAX,%RSI,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS %XMM0,(%RDX,%R9,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (6.3%)
MOV 0x30(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R9,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5a30 <main+0x2080>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
CMP $0x3,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JBE 5ae2 <main+0x2132>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV %ESI,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
ADD 0xb8(%RSP),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
SETB %R9B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
OR 0x180(%RSP),%R9B	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JE 88b4 <main+0x4f04>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
CMPQ $0x7,0xb8(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RSI,0x2c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
JAE 5b10 <main+0x2160>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x88(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x70(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 5c94 <main+0x22e4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0x370(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x418(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x410(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x408(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x400(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x3f8(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x88(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x70(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x3f0(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
CMPQ $0,0x378(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV 0x2c0(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JE 5a90 <main+0x20e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x378(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %RBX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
IMUL %R9,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %ECX,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RSI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 5a90 <main+0x20e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-clang-znver5-512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-27,30,33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.50 to 1.88 cycles (2.93x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 5.50 to 3.00 cycles (1.83x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 149 bytes. The binary loop is storing 12 bytes.

General properties

nb instructions	45
nb uops	44
loop length	255
used x86 registers	15
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	16

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.50 cycles
front end	5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.00	3.00	3.00	3.00	3.00	3.00	5.50	5.50	5.50	5.50	0.00	0.00	0.50	0.50	0.50	0.50
cycles	3.00	3.00	3.00	3.00	3.00	3.00	5.50	5.50	5.50	5.50	0.00	0.00	0.50	0.50	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.50
Dispatch	5.50
Overall L1	5.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	12%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.50 cycles. At this rate:

10% of peak load performance is reached (27.09 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.18 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 5abf

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0x200(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x98(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VCVTSD2SS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
LEA (%RAX,%RSI,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS %XMM0,(%RDX,%R9,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (6.3%)
MOV 0x30(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R9,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5a30 <main+0x2080>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
CMP $0x3,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JBE 5ae2 <main+0x2132>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV %ESI,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
ADD 0xb8(%RSP),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
SETB %R9B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
OR 0x180(%RSP),%R9B	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JE 88b4 <main+0x4f04>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
CMPQ $0x7,0xb8(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RSI,0x2c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
JAE 5b10 <main+0x2160>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x88(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x70(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 5c94 <main+0x22e4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0x370(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x418(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x410(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x408(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x400(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x3f8(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x88(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x70(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x3f0(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
CMPQ $0,0x378(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
MOV 0x2c0(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JE 5a90 <main+0x20e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x378(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %RBX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
IMUL %R9,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %ECX,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RSI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 5a90 <main+0x20e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code