OV - attention-clang-znver5-512 - Loop 64 - attention-clang-znver5-512

0x67f5 MOV	0x500(%RSP),%R12D

0x67fd MOV	0x38(%RSP),%RSI

0x6802 INC	%R12D

0x6805 ADD	%RSI,%RAX

0x6808 CMP	%EDX,%R12D

0x680b JE	6c42

0x6811 MOV	%R12D,%ECX

0x6814 IMUL	%ESI,%ECX

0x6817 MOV	%R12D,%ESI

0x681a IMUL	%EDX,%ESI

0x681d ADD	0xb8(%RSP),%ECX

0x6824 MOV	%R12D,0x500(%RSP)

0x682c MOV	%RSI,0x160(%RSP)

0x6834 SETB	%CL

0x6837 OR	0x7f(%RSP),%CL

0x683b XOR	%R12D,%R12D

0x683e MOV	%CL,0x40(%RSP)

0x6842 JMP	688d

  (65) 0x6844 VCVTSD2SS	%XMM0,%XMM0,%XMM0

  (65) 0x6848 VDIVSS	0x424(%RSP),%XMM0,%XMM0

  (65) 0x6851 MOV	0xc0(%RSP),%R12

  (65) 0x6859 MOV	0x160(%RSP),%RCX

  (65) 0x6861 MOV	0x148(%RSP),%RDX

  (65) 0x6869 MOV	0x90(%RSP),%R13

  (65) 0x6871 ADD	%R12D,%ECX

  (65) 0x6874 INC	%R12

  (65) 0x6877 VMOVSS	%XMM0,(%RDX,%RCX,4)

  (65) 0x687c MOV	0x80(%RSP),%RDX

  (65) 0x6884 CMP	%R13,%R12

  (65) 0x6887 JE	67f5

  (65) 0x688d CMPL	$0x4,0x30(%RSP)

  (65) 0x6892 VPXOR	%XMM0,%XMM0,%XMM0

  (65) 0x6896 MOV	%R12,0xc0(%RSP)

  (65) 0x689e JB	68b7

  (65) 0x68a0 MOV	%R12D,%ECX

  (65) 0x68a3 ADD	0xb8(%RSP),%ECX

  (65) 0x68aa SETB	%CL

  (65) 0x68ad OR	0x40(%RSP),%CL

  (65) 0x68b1 JE	6af6

  (65) 0x68b7 XOR	%ECX,%ECX

  (65) 0x68b9 MOV	0x38(%RSP),%RDX

  (65) 0x68be SUB	%ECX,%EDX

  (65) 0x68c0 AND	$0x7,%EDX

  (65) 0x68c3 JE	691c

  (65) 0x68c5 MOV	0x80(%RSP),%R9

  (65) 0x68cd MOV	0x98(%RSP),%R11

  (65) 0x68d5 MOV	%RCX,%R8

  (65) 0x68d8 MOV	%R9,%RSI

  (65) 0x68db IMUL	%RCX,%RSI

  (65) 0x68df ADD	0xc0(%RSP),%RSI

  (65) 0x68e7 NOPW	(%RAX,%RAX,1)

    (67) 0x68f0 LEA	(%RAX,%R8,1),%EDI

    (67) 0x68f4 INC	%R8

    (67) 0x68f7 VMOVSS	(%R11,%RDI,4),%XMM1

    (67) 0x68fd MOV	%ESI,%EDI

    (67) 0x68ff VMOVSS	(%R15,%RDI,4),%XMM2

    (67) 0x6905 ADD	%R9,%RSI

    (67) 0x6908 DEC	%RDX

    (67) 0x690b VCVTSS2SD	%XMM1,%XMM1,%XMM1

    (67) 0x690f VCVTSS2SD	%XMM2,%XMM2,%XMM2

    (67) 0x6913 VFMADD231SD	%XMM2,%XMM1,%XMM0

    (67) 0x6918 JNE	68f0

  (65) 0x691a JMP	6927

  (65) 0x691c MOV	0x98(%RSP),%R11

  (65) 0x6924 MOV	%RCX,%R8

  (65) 0x6927 MOV	0x30(%RSP),%R14

  (65) 0x692c MOV	0x4e0(%RSP),%RBX

  (65) 0x6934 SUB	%R14,%RCX

  (65) 0x6937 CMP	$-0x8,%RCX

  (65) 0x693b JA	6844

  (65) 0x6941 MOV	0x80(%RSP),%RDI

  (65) 0x6949 LEA	0x7(%R8),%RCX

  (65) 0x694d LEA	0x4(%R8),%R12

  (65) 0x6951 LEA	0x3(%R8),%R13

  (65) 0x6955 LEA	0x1(%R8),%RDX

  (65) 0x6959 IMUL	%RDI,%RCX

  (65) 0x695d MOV	%RDI,%RSI

  (65) 0x6960 IMUL	%RDI,%R12

  (65) 0x6964 IMUL	%RDI,%R13

  (65) 0x6968 IMUL	%RDI,%RDX

  (65) 0x696c IMUL	%R8,%RSI

  (65) 0x6970 MOV	%RCX,0x2c0(%RSP)

  (65) 0x6978 LEA	0x6(%R8),%RCX

  (65) 0x697c IMUL	%RDI,%RCX

  (65) 0x6980 MOV	%RCX,0x200(%RSP)

  (65) 0x6988 LEA	0x5(%R8),%RCX

  (65) 0x698c IMUL	%RDI,%RCX

  (65) 0x6990 MOV	%RCX,0x180(%RSP)

  (65) 0x6998 LEA	0x2(%R8),%RCX

  (65) 0x699c IMUL	%RDI,%RCX

  (65) 0x69a0 MOV	0xc0(%RSP),%RDI

  (65) 0x69a8 NOPL	(%RAX,%RAX,1)

    (66) 0x69b0 LEA	(%RAX,%R8,1),%R9D

    (66) 0x69b4 LEA	0x6(%RAX,%R8,1),%R10D

    (66) 0x69b9 VMOVSS	(%R11,%R9,4),%XMM1

    (66) 0x69bf LEA	(%RSI,%RDI,1),%R9D

    (66) 0x69c3 VMOVSS	(%R15,%R9,4),%XMM2

    (66) 0x69c9 LEA	0x1(%RAX,%R8,1),%R9D

    (66) 0x69ce VMOVSS	(%R11,%R10,4),%XMM13

    (66) 0x69d4 VMOVSS	(%R11,%R9,4),%XMM3

    (66) 0x69da LEA	(%RDX,%RDI,1),%R9D

    (66) 0x69de VMOVSS	(%R15,%R9,4),%XMM4

    (66) 0x69e4 LEA	0x2(%RAX,%R8,1),%R9D

    (66) 0x69e9 VMOVSS	(%R11,%R9,4),%XMM5

    (66) 0x69ef LEA	(%RCX,%RDI,1),%R9D

    (66) 0x69f3 VMOVSS	(%R15,%R9,4),%XMM6

    (66) 0x69f9 LEA	0x3(%RAX,%R8,1),%R9D

    (66) 0x69fe VCVTSS2SD	%XMM1,%XMM1,%XMM1

    (66) 0x6a02 VCVTSS2SD	%XMM2,%XMM2,%XMM2

    (66) 0x6a06 VMOVSS	(%R11,%R9,4),%XMM7

    (66) 0x6a0c LEA	(%R13,%RDI,1),%R9D

    (66) 0x6a11 VMOVSS	(%R15,%R9,4),%XMM8

    (66) 0x6a17 LEA	0x4(%RAX,%R8,1),%R9D

    (66) 0x6a1c VFMADD213SD	%XMM0,%XMM1,%XMM2

    (66) 0x6a21 VCVTSS2SD	%XMM3,%XMM3,%XMM0

    (66) 0x6a25 VMOVSS	(%R11,%R9,4),%XMM9

    (66) 0x6a2b LEA	(%R12,%RDI,1),%R9D

    (66) 0x6a2f VMOVSS	(%R15,%R9,4),%XMM10

    (66) 0x6a35 LEA	0x5(%RAX,%R8,1),%R9D

    (66) 0x6a3a VCVTSS2SD	%XMM4,%XMM4,%XMM1

    (66) 0x6a3e VMOVSS	(%R11,%R9,4),%XMM11

    (66) 0x6a44 MOV	0x180(%RSP),%R9

    (66) 0x6a4c VFMADD213SD	%XMM2,%XMM0,%XMM1

    (66) 0x6a51 VCVTSS2SD	%XMM5,%XMM5,%XMM0

    (66) 0x6a55 LEA	(%R9,%RDI,1),%R9D

    (66) 0x6a59 VCVTSS2SD	%XMM6,%XMM6,%XMM2

    (66) 0x6a5d VMOVSS	(%R15,%R9,4),%XMM12

    (66) 0x6a63 MOV	0x200(%RSP),%R9

    (66) 0x6a6b VFMADD213SD	%XMM1,%XMM0,%XMM2

    (66) 0x6a70 VCVTSS2SD	%XMM7,%XMM7,%XMM0

    (66) 0x6a74 ADD	%EDI,%R9D

    (66) 0x6a77 VCVTSS2SD	%XMM8,%XMM8,%XMM1

    (66) 0x6a7c VMOVSS	(%R15,%R9,4),%XMM14

    (66) 0x6a82 LEA	0x7(%RAX,%R8,1),%R9D

    (66) 0x6a87 ADD	$0x8,%R8

    (66) 0x6a8b VMOVSS	(%R11,%R9,4),%XMM15

    (66) 0x6a91 MOV	0x2c0(%RSP),%R9

    (66) 0x6a99 VFMADD213SD	%XMM2,%XMM0,%XMM1

    (66) 0x6a9e VCVTSS2SD	%XMM9,%XMM9,%XMM0

    (66) 0x6aa3 VCVTSS2SD	%XMM10,%XMM10,%XMM2

    (66) 0x6aa8 ADD	%EDI,%R9D

    (66) 0x6aab ADD	%RBX,%RDI

    (66) 0x6aae VMOVSS	(%R15,%R9,4),%XMM16

    (66) 0x6ab5 VFMADD213SD	%XMM1,%XMM0,%XMM2

    (66) 0x6aba VCVTSS2SD	%XMM11,%XMM11,%XMM0

    (66) 0x6abf VCVTSS2SD	%XMM12,%XMM12,%XMM1

    (66) 0x6ac4 VFMADD213SD	%XMM2,%XMM0,%XMM1

    (66) 0x6ac9 VCVTSS2SD	%XMM13,%XMM13,%XMM0

    (66) 0x6ace VCVTSS2SD	%XMM14,%XMM14,%XMM2

    (66) 0x6ad3 VFMADD213SD	%XMM1,%XMM0,%XMM2

    (66) 0x6ad8 VCVTSS2SD	%XMM15,%XMM15,%XMM1

    (66) 0x6add VCVTSS2SD	%XMM16,%XMM16,%XMM0

    (66) 0x6ae3 VFMADD213SD	%XMM2,%XMM1,%XMM0

    (66) 0x6ae8 CMP	%R8,%R14

    (66) 0x6aeb JNE	69b0

  (65) 0x6af1 JMP	6844

  (65) 0x6af6 CMPL	$0x20,0x30(%RSP)

  (65) 0x6afb JAE	6b0c

  (65) 0x6afd MOV	0x98(%RSP),%RSI

  (65) 0x6b05 XOR	%EDX,%EDX

  (65) 0x6b07 JMP	6be9

  (65) 0x6b0c MOV	0x98(%RSP),%RSI

  (65) 0x6b14 MOV	0x4d0(%RSP),%RDI

  (65) 0x6b1c VPXOR	%XMM0,%XMM0,%XMM0

  (65) 0x6b20 XOR	%ECX,%ECX

  (65) 0x6b22 VPXOR	%XMM1,%XMM1,%XMM1

  (65) 0x6b26 VXORPS	%XMM2,%XMM2,%XMM2

  (65) 0x6b2a VXORPS	%XMM3,%XMM3,%XMM3

    (68) 0x6b2e LEA	(%RAX,%RCX,1),%EDX

    (68) 0x6b31 VCVTPS2PD	(%RSI,%RDX,4),%ZMM4

    (68) 0x6b38 VCVTPS2PD	0x20(%RSI,%RDX,4),%ZMM5

    (68) 0x6b40 VCVTPS2PD	0x40(%RSI,%RDX,4),%ZMM6

    (68) 0x6b48 VCVTPS2PD	0x60(%RSI,%RDX,4),%ZMM7

    (68) 0x6b50 LEA	(%R12,%RCX,1),%EDX

    (68) 0x6b54 ADD	$0x20,%RCX

    (68) 0x6b58 VCVTPS2PD	(%R15,%RDX,4),%ZMM8

    (68) 0x6b5f VCVTPS2PD	0x20(%R15,%RDX,4),%ZMM9

    (68) 0x6b67 VFMADD231PD	%ZMM8,%ZMM4,%ZMM0

    (68) 0x6b6d VFMADD231PD	%ZMM9,%ZMM5,%ZMM1

    (68) 0x6b73 VCVTPS2PD	0x40(%R15,%RDX,4),%ZMM8

    (68) 0x6b7b VCVTPS2PD	0x60(%R15,%RDX,4),%ZMM5

    (68) 0x6b83 VFMADD231PD	%ZMM8,%ZMM6,%ZMM2

    (68) 0x6b89 VFMADD231PD	%ZMM5,%ZMM7,%ZMM3

    (68) 0x6b8f CMP	%RCX,%RDI

    (68) 0x6b92 JNE	6b2e

  (65) 0x6b94 VADDPD	%ZMM0,%ZMM1,%ZMM0

  (65) 0x6b9a VADDPD	%ZMM2,%ZMM3,%ZMM2

  (65) 0x6ba0 VADDPD	%ZMM0,%ZMM2,%ZMM0

  (65) 0x6ba6 VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

  (65) 0x6bad VADDPD	%ZMM1,%ZMM0,%ZMM0

  (65) 0x6bb3 VEXTRACTF128	$0x1,%YMM0,%XMM1

  (65) 0x6bb9 VADDPD	%XMM1,%XMM0,%XMM0

  (65) 0x6bbd VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (65) 0x6bc2 VADDSD	%XMM1,%XMM0,%XMM0

  (65) 0x6bc6 CMP	%EDI,0x30(%RSP)

  (65) 0x6bca JE	6844

  (65) 0x6bd0 TESTB	$0x1c,0x38(%RSP)

  (65) 0x6bd5 MOV	0x98(%RSP),%RSI

  (65) 0x6bdd MOV	%RDI,%RDX

  (65) 0x6be0 MOV	%RDI,%RCX

  (65) 0x6be3 JE	68b9

  (65) 0x6be9 MOV	0x340(%RSP),%RDI

  (65) 0x6bf1 MOV	0xc0(%RSP),%R8

  (65) 0x6bf9 VMOVQ	%XMM0,%XMM0

    (69) 0x6bfd LEA	(%RAX,%RDX,1),%ECX

    (69) 0x6c00 VCVTPS2PD	(%RSI,%RCX,4),%YMM1

    (69) 0x6c05 LEA	(%R8,%RDX,1),%ECX

    (69) 0x6c09 ADD	$0x4,%RDX

    (69) 0x6c0d VCVTPS2PD	(%R15,%RCX,4),%YMM2

    (69) 0x6c13 VFMADD231PD	%YMM2,%YMM1,%YMM0

    (69) 0x6c18 CMP	%RDX,%RDI

    (69) 0x6c1b JNE	6bfd

  (65) 0x6c1d VEXTRACTF128	$0x1,%YMM0,%XMM1

  (65) 0x6c23 MOV	%RDI,%RCX

  (65) 0x6c26 VADDPD	%XMM1,%XMM0,%XMM0

  (65) 0x6c2a VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (65) 0x6c2f VADDSD	%XMM1,%XMM0,%XMM0

  (65) 0x6c33 CMP	%EDI,0x30(%RSP)

  (65) 0x6c37 JE	6844

  (65) 0x6c3d JMP	68b9

/home/eoseret/llm-attention/attention_v2.cpp: 26 - 254

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

254:       start = std::chrono::steady_clock::now();

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.71
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:254-254
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.25
CQA cycles if no scalar integer	2.25
CQA cycles if FP arith vectorized	2.25
CQA cycles if fully vectorized	0.16
Front-end cycles	2.25
P0 cycles	1.67
P1 cycles	1.67
P2 cycles	1.67
P3 cycles	1.67
P4 cycles	1.67
P5 cycles	1.67
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	1.75
P9 cycles	1.75
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	4.00
Nb stores	3.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.33
Bytes prefetched	0.00
Bytes loaded	17.00
Bytes stored	13.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.13
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	9.38
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.71
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:254-254
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.25
CQA cycles if no scalar integer	2.25
CQA cycles if FP arith vectorized	2.25
CQA cycles if fully vectorized	0.16
Front-end cycles	2.25
P0 cycles	1.67
P1 cycles	1.67
P2 cycles	1.67
P3 cycles	1.67
P4 cycles	1.67
P5 cycles	1.67
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	1.75
P9 cycles	1.75
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	4.00
Nb stores	3.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.33
Bytes prefetched	0.00
Bytes loaded	17.00
Bytes stored	13.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.13
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	9.38
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-254
Module	attention-clang-znver5-512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33,254.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26,254.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 23 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.25 to 0.16 cycles (13.71x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 17 bytes. The binary loop is storing 13 bytes.

General properties

nb instructions	18
nb uops	18
loop length	79
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.25 cycles
front end	2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.67	1.67	1.67	1.67	1.67	1.67	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.67	1.67	1.67	1.67	1.67	1.67	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.25
Dispatch	1.75
Overall L1	2.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	9%
store	9%
mul	6%
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.25 cycles. At this rate:

2% of peak load performance is reached (7.56 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.78 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.25 to 1.75 cycles (1.29x speedup).

ASM code

In the binary file, the address of the loop is: 6811

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV 0x500(%RSP),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x38(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
INC %R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMP %EDX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JE 6c42 <main+0x3292>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-0.50	N/A
MOV %R12D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV %R12D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
IMUL %EDX,%ESI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD 0xb8(%RSP),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV %R12D,0x500(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %RSI,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SETB %CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
OR 0x7f(%RSP),%CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %CL,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	N/A
JMP 688d <main+0x2edd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:26-254
Module	attention-clang-znver5-512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33,254.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26,254.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 23 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.25 to 0.16 cycles (13.71x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 17 bytes. The binary loop is storing 13 bytes.

General properties

nb instructions	18
nb uops	18
loop length	79
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.25 cycles
front end	2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.67	1.67	1.67	1.67	1.67	1.67	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.67	1.67	1.67	1.67	1.67	1.67	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.25
Dispatch	1.75
Overall L1	2.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	9%
store	9%
mul	6%
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.25 cycles. At this rate:

2% of peak load performance is reached (7.56 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.78 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.25 to 1.75 cycles (1.29x speedup).

ASM code

In the binary file, the address of the loop is: 6811

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV 0x500(%RSP),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x38(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
INC %R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMP %EDX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JE 6c42 <main+0x3292>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-0.50	N/A
MOV %R12D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV %R12D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
IMUL %EDX,%ESI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD 0xb8(%RSP),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV %R12D,0x500(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %RSI,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SETB %CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
OR 0x7f(%RSP),%CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %CL,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	N/A
JMP 688d <main+0x2edd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code