OV - attention-clang-znver5-512 - Loop 58 - attention-clang-znver5-512

	Loop Id: 58	Module: attention-clang-znver5-512	Source: attention_v2.cpp:43-61	Coverage: 0.40%

0x6caf MOV	0x2b0(%RSP),%RCX

0x6cb7 MOV	0x1d8(%RSP),%RAX

0x6cbf MOV	0xa8(%RSP),%RSI

0x6cc7 MOV	0x430(%RSP),%RDX

0x6ccf MOV	0x398(%RSP),%RDI

0x6cd7 MOV	%RBX,0x428(%RSP)

0x6cdf VMOVSS	%XMM2,(%RAX,%R15,4)

0x6ce5 MOV	%R14,%R15

0x6ce8 INC	%RCX

0x6ceb ADD	%RSI,%RDX

0x6cee ADD	%RSI,%R15

0x6cf1 ADD	%RSI,%RDI

0x6cf4 CMP	%R13,%RBX

0x6cf7 JE	8078

0x6cfd MOV	%RCX,%RSI

0x6d00 MOV	%RCX,%R14

0x6d03 AND	$-0x8,%RSI

0x6d07 AND	$-0x40,%R14

0x6d0b MOV	%RCX,%RBX

0x6d0e MOV	%RDI,0x398(%RSP)

0x6d16 CMP	$0x8,%RCX

0x6d1a JAE	6d2b

0x6d1c VMOVSS	0x22e0(%RIP),%XMM1

0x6d24 XOR	%EAX,%EAX

0x6d26 JMP	6e1d

0x6d2b CMP	$0x40,%RBX

0x6d2f JAE	6d40

0x6d31 VMOVSS	0x22cb(%RIP),%XMM1

0x6d39 XOR	%EAX,%EAX

0x6d3b JMP	6dd8

0x6d40 VBROADCASTSS	0x22ba(%RIP),%ZMM3

0x6d4a MOV	$0x7fffffffffffffc0,%RCX

0x6d54 MOV	%RBX,%RAX

0x6d57 AND	%RCX,%RAX

0x6d5a XOR	%ECX,%ECX

0x6d5c VMOVAPS	%ZMM3,%ZMM0

0x6d62 VMOVAPS	%ZMM3,%ZMM1

0x6d68 VMOVAPS	%ZMM3,%ZMM2

  (47) 0x6d6e VMAXPS	-0xc0(%RDX,%RCX,4),%ZMM0,%ZMM0

  (47) 0x6d76 VMAXPS	-0x80(%RDX,%RCX,4),%ZMM1,%ZMM1

  (47) 0x6d7e VMAXPS	-0x40(%RDX,%RCX,4),%ZMM2,%ZMM2

  (47) 0x6d86 VMAXPS	(%RDX,%RCX,4),%ZMM3,%ZMM3

  (47) 0x6d8d ADD	$0x40,%RCX

  (47) 0x6d91 CMP	%RCX,%R14

  (47) 0x6d94 JNE	6d6e

0x6d96 VMAXPS	%ZMM1,%ZMM0,%ZMM0

0x6d9c VMAXPS	%ZMM3,%ZMM2,%ZMM1

0x6da2 VMAXPS	%ZMM1,%ZMM0,%ZMM0

0x6da8 VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

0x6daf VMAXPS	%YMM1,%YMM0,%YMM0

0x6db3 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x6db9 VMAXPS	%XMM1,%XMM0,%XMM0

0x6dbd VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x6dc2 VMAXPS	%XMM1,%XMM0,%XMM0

0x6dc6 VMOVSHDUP	%XMM0,%XMM1

0x6dca VMAXSS	%XMM1,%XMM0,%XMM1

0x6dce CMP	%RAX,%RBX

0x6dd1 JE	6e2b

0x6dd3 TEST	$0x38,%BL

0x6dd6 JE	6e1d

0x6dd8 MOV	%RAX,%RCX

0x6ddb MOV	$0x7fffffffffffffc0,%RAX

0x6de5 VBROADCASTSS	%XMM1,%YMM0

0x6dea ADD	$0x38,%RAX

0x6dee AND	%RBX,%RAX

  (63) 0x6df1 VMAXPS	(%R15,%RCX,4),%YMM0,%YMM0

  (63) 0x6df7 ADD	$0x8,%RCX

  (63) 0x6dfb CMP	%RCX,%RSI

  (63) 0x6dfe JNE	6df1

0x6e00 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x6e06 VMAXPS	%XMM1,%XMM0,%XMM0

0x6e0a VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x6e0f VMAXPS	%XMM1,%XMM0,%XMM0

0x6e13 VMOVSHDUP	%XMM0,%XMM1

0x6e17 VMAXSS	%XMM1,%XMM0,%XMM1

0x6e1b JMP	6e26

  (62) 0x6e1d VMAXSS	(%R15,%RAX,4),%XMM1,%XMM1

  (62) 0x6e23 INC	%RAX

  (62) 0x6e26 CMP	%RAX,%RBX

  (62) 0x6e29 JNE	6e1d

0x6e2b MOV	%RBX,0x2b0(%RSP)

0x6e33 VMOVAPS	%XMM1,0x160(%RSP)

0x6e3c MOV	%RDX,0x430(%RSP)

0x6e44 CMP	$0x7,%RBX

0x6e48 JA	6e56

0x6e4a VXORPS	%XMM2,%XMM2,%XMM2

0x6e4e XOR	%R14D,%R14D

0x6e51 JMP	7b56

0x6e56 CMP	$0x40,%RBX

0x6e5a JAE	6e68

0x6e5c VXORPS	%XMM2,%XMM2,%XMM2

0x6e60 XOR	%R14D,%R14D

0x6e63 JMP	7985

0x6e68 VBROADCASTSS	%XMM1,%ZMM0

0x6e6e MOV	$0x7fffffffffffffc0,%RAX

0x6e78 MOV	%RSI,0x478(%RSP)

0x6e80 VXORPS	%XMM1,%XMM1,%XMM1

0x6e84 AND	%RAX,%RBX

0x6e87 MOV	%RBX,0x390(%RSP)

0x6e8f VMOVAPS	%ZMM0,0x19c0(%RSP)

0x6e97 VXORPS	%XMM0,%XMM0,%XMM0

0x6e9b XOR	%EBX,%EBX

0x6e9d VMOVAPS	%ZMM0,0x500(%RSP)

0x6ea5 VMOVAPS	%ZMM0,0x540(%RSP)

0x6ead VMOVAPS	%ZMM0,0x5c0(%RSP)

  (48) 0x6eb5 VMOVUPS	-0xc0(%RDX,%RBX,4),%ZMM0

  (48) 0x6ebd VMOVAPS	0x19c0(%RSP),%ZMM4

  (48) 0x6ec5 VMOVUPS	(%RDX,%RBX,4),%ZMM3

  (48) 0x6ecc VMOVAPS	%ZMM1,0x1a00(%RSP)

  (48) 0x6ed4 VMOVUPS	-0x80(%RDX,%RBX,4),%ZMM1

  (48) 0x6edc VMOVUPS	-0x40(%RDX,%RBX,4),%ZMM2

  (48) 0x6ee4 VSUBPS	%ZMM4,%ZMM0,%ZMM5

  (48) 0x6eea VSUBPS	%ZMM4,%ZMM3,%ZMM0

  (48) 0x6ef0 VSUBPS	%ZMM4,%ZMM1,%ZMM6

  (48) 0x6ef6 VSUBPS	%ZMM4,%ZMM2,%ZMM1

  (48) 0x6efc VMOVAPS	%ZMM0,0x2c0(%RSP)

  (48) 0x6f04 VEXTRACTF32X4	$0x3,%ZMM5,%XMM0

  (48) 0x6f0b VMOVAPS	%ZMM5,0xc0(%RSP)

  (48) 0x6f13 VMOVAPS	%ZMM6,0x180(%RSP)

  (48) 0x6f1b VMOVAPS	%ZMM1,0x200(%RSP)

  (48) 0x6f23 VMOVAPS	%XMM0,0x40(%RSP)

  (48) 0x6f29 VZEROUPPER

  (48) 0x6f2c CALL	1160 <expf@plt>

  (48) 0x6f31 VMOVAPS	%XMM0,0x260(%RSP)

  (48) 0x6f3a VMOVSHDUP	0x40(%RSP),%XMM0

  (48) 0x6f40 CALL	1160 <expf@plt>

  (48) 0x6f45 VMOVAPS	0x260(%RSP),%XMM1

  (48) 0x6f4e VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (48) 0x6f54 VMOVAPS	%XMM0,0x260(%RSP)

  (48) 0x6f5d VPERMILPD	$0x1,0x40(%RSP),%XMM0

  (48) 0x6f65 CALL	1160 <expf@plt>

  (48) 0x6f6a VMOVAPS	0x260(%RSP),%XMM1

  (48) 0x6f73 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (48) 0x6f79 VMOVAPS	%XMM0,0x260(%RSP)

  (48) 0x6f82 VPERMILPS	$-0x1,0x40(%RSP),%XMM0

  (48) 0x6f8a CALL	1160 <expf@plt>

  (48) 0x6f8f VMOVAPS	0x260(%RSP),%XMM1

  (48) 0x6f98 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (48) 0x6f9e VMOVAPS	%XMM0,0x260(%RSP)

  (48) 0x6fa7 VMOVAPS	0xc0(%RSP),%ZMM0

  (48) 0x6faf VEXTRACTF32X4	$0x2,%ZMM0,%XMM0

  (48) 0x6fb6 VMOVAPS	%XMM0,0x40(%RSP)

  (48) 0x6fbc VZEROUPPER

  (48) 0x6fbf CALL	1160 <expf@plt>

  (48) 0x6fc4 VMOVAPS	%XMM0,0x150(%RSP)

  (48) 0x6fcd VMOVSHDUP	0x40(%RSP),%XMM0

  (48) 0x6fd3 CALL	1160 <expf@plt>

  (48) 0x6fd8 VMOVAPS	0x150(%RSP),%XMM1

  (48) 0x6fe1 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (48) 0x6fe7 VMOVAPS	%XMM0,0x150(%RSP)

  (48) 0x6ff0 VPERMILPD	$0x1,0x40(%RSP),%XMM0

  (48) 0x6ff8 CALL	1160 <expf@plt>

  (48) 0x6ffd VMOVAPS	0x150(%RSP),%XMM1

  (48) 0x7006 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (48) 0x700c VMOVAPS	%XMM0,0x150(%RSP)

  (48) 0x7015 VPERMILPS	$-0x1,0x40(%RSP),%XMM0

  (48) 0x701d CALL	1160 <expf@plt>

  (48) 0x7022 VMOVAPS	0x150(%RSP),%XMM1

  (48) 0x702b VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (48) 0x7031 VINSERTF128	$0x1,0x260(%RSP),%YMM0,%YMM0

  (48) 0x703c VMOVAPS	%YMM0,0x260(%RSP)

  (48) 0x7045 VMOVAPS	0xc0(%RSP),%ZMM0

  (48) 0x704d VEXTRACTF128	$0x1,%YMM0,%XMM0

  (48) 0x7053 VMOVAPS	%XMM0,0x40(%RSP)

  (48) 0x7059 VZEROUPPER

  (48) 0x705c CALL	1160 <expf@plt>

  (48) 0x7061 VMOVAPS	%XMM0,0x150(%RSP)

  (48) 0x706a VMOVSHDUP	0x40(%RSP),%XMM0

  (48) 0x7070 CALL	1160 <expf@plt>

  (48) 0x7075 VMOVAPS	0x150(%RSP),%XMM1

  (48) 0x707e VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (48) 0x7084 VMOVAPS	%XMM0,0x150(%RSP)

  (48) 0x708d VPERMILPD	$0x1,0x40(%RSP),%XMM0

  (48) 0x7095 CALL	1160 <expf@plt>

  (48) 0x709a VMOVAPS	0x150(%RSP),%XMM1

  (48) 0x70a3 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (48) 0x70a9 VMOVAPS	%XMM0,0x150(%RSP)

  (48) 0x70b2 VPERMILPS	$-0x1,0x40(%RSP),%XMM0

  (48) 0x70ba CALL	1160 <expf@plt>

  (48) 0x70bf VMOVAPS	0x150(%RSP),%XMM1

  (48) 0x70c8 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (48) 0x70ce VMOVAPS	%XMM0,0x40(%RSP)

  (48) 0x70d4 VMOVAPS	0xc0(%RSP),%ZMM0

  (48) 0x70dc VZEROUPPER

  (48) 0x70df CALL	1160 <expf@plt>

  (48) 0x70e4 VMOVAPS	%XMM0,0x150(%RSP)

  (48) 0x70ed VMOVSHDUP	0xc0(%RSP),%XMM0

  (48) 0x70f6 CALL	1160 <expf@plt>

  (48) 0x70fb VMOVAPS	0x150(%RSP),%XMM1

  (48) 0x7104 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (48) 0x710a VMOVAPS	%XMM0,0x150(%RSP)

  (48) 0x7113 VPERMILPD	$0x1,0xc0(%RSP),%XMM0

  (48) 0x711e CALL	1160 <expf@plt>

  (48) 0x7123 VMOVAPS	0x150(%RSP),%XMM1

  (48) 0x712c VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (48) 0x7132 VMOVAPS	%XMM0,0x150(%RSP)

  (48) 0x713b VPERMILPS	$-0x1,0xc0(%RSP),%XMM0

  (48) 0x7146 CALL	1160 <expf@plt>

  (48) 0x714b VMOVAPS	0x150(%RSP),%XMM1

  (48) 0x7154 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (48) 0x715a VINSERTF128	$0x1,0x40(%RSP),%YMM0,%YMM0

  (48) 0x7162 VMOVAPS	0x500(%RSP),%ZMM1

  (48) 0x716a VINSERTF64X4	$0x1,0x260(%RSP),%ZMM0,%ZMM0

  (48) 0x7173 VADDPS	%ZMM1,%ZMM0,%ZMM1

  (48) 0x7179 VMOVAPS	0x180(%RSP),%ZMM0

  (48) 0x7181 VMOVAPS	%ZMM1,0x500(%RSP)

  (48) 0x7189 VEXTRACTF32X4	$0x3,%ZMM0,%XMM0

  (48) 0x7190 VMOVAPS	%XMM0,0xc0(%RSP)

  (48) 0x7199 VZEROUPPER

  (48) 0x719c CALL	1160 <expf@plt>

  (48) 0x71a1 VMOVAPS	%XMM0,0x40(%RSP)

  (48) 0x71a7 VMOVSHDUP	0xc0(%RSP),%XMM0

  (48) 0x71b0 CALL	1160 <expf@plt>

  (48) 0x71b5 VMOVAPS	0x40(%RSP),%XMM1

  (48) 0x71bb VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (48) 0x71c1 VMOVAPS	%XMM0,0x40(%RSP)

  (48) 0x71c7 VPERMILPD	$0x1,0xc0(%RSP),%XMM0

  (48) 0x71d2 CALL	1160 <expf@plt>

  (48) 0x71d7 VMOVAPS	0x40(%RSP),%XMM1

  (48) 0x71dd VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (48) 0x71e3 VMOVAPS	%XMM0,0x40(%RSP)

  (48) 0x71e9 VPERMILPS	$-0x1,0xc0(%RSP),%XMM0

  (48) 0x71f4 CALL	1160 <expf@plt>

  (48) 0x71f9 VMOVAPS	0x40(%RSP),%XMM1

  (48) 0x71ff VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (48) 0x7205 VMOVAPS	%XMM0,0x40(%RSP)

  (48) 0x720b VMOVAPS	0x180(%RSP),%ZMM0

  (48) 0x7213 VEXTRACTF32X4	$0x2,%ZMM0,%XMM0

  (48) 0x721a VMOVAPS	%XMM0,0xc0(%RSP)

  (48) 0x7223 VZEROUPPER

  (48) 0x7226 CALL	1160 <expf@plt>

  (48) 0x722b VMOVAPS	%XMM0,0x260(%RSP)

  (48) 0x7234 VMOVSHDUP	0xc0(%RSP),%XMM0

  (48) 0x723d CALL	1160 <expf@plt>

  (48) 0x7242 VMOVAPS	0x260(%RSP),%XMM1

  (48) 0x724b VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (48) 0x7251 VMOVAPS	%XMM0,0x260(%RSP)

  (48) 0x725a VPERMILPD	$0x1,0xc0(%RSP),%XMM0

  (48) 0x7265 CALL	1160 <expf@plt>

  (48) 0x726a VMOVAPS	0x260(%RSP),%XMM1

  (48) 0x7273 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (48) 0x7279 VMOVAPS	%XMM0,0x260(%RSP)

  (48) 0x7282 VPERMILPS	$-0x1,0xc0(%RSP),%XMM0

  (48) 0x728d CALL	1160 <expf@plt>

  (48) 0x7292 VMOVAPS	0x260(%RSP),%XMM1

  (48) 0x729b VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (48) 0x72a1 VINSERTF128	$0x1,0x40(%RSP),%YMM0,%YMM0

  (48) 0x72a9 VMOVAPS	%YMM0,0x40(%RSP)

  (48) 0x72af VMOVAPS	0x180(%RSP),%ZMM0

  (48) 0x72b7 VEXTRACTF128	$0x1,%YMM0,%XMM0

  (48) 0x72bd VMOVAPS	%XMM0,0xc0(%RSP)

  (48) 0x72c6 VZEROUPPER

  (48) 0x72c9 CALL	1160 <expf@plt>

  (48) 0x72ce VMOVAPS	%XMM0,0x260(%RSP)

  (48) 0x72d7 VMOVSHDUP	0xc0(%RSP),%XMM0

  (48) 0x72e0 CALL	1160 <expf@plt>

  (48) 0x72e5 VMOVAPS	0x260(%RSP),%XMM1

  (48) 0x72ee VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (48) 0x72f4 VMOVAPS	%XMM0,0x260(%RSP)

  (48) 0x72fd VPERMILPD	$0x1,0xc0(%RSP),%XMM0

  (48) 0x7308 CALL	1160 <expf@plt>

  (48) 0x730d VMOVAPS	0x260(%RSP),%XMM1

  (48) 0x7316 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (48) 0x731c VMOVAPS	%XMM0,0x260(%RSP)

  (48) 0x7325 VPERMILPS	$-0x1,0xc0(%RSP),%XMM0

  (48) 0x7330 CALL	1160 <expf@plt>

  (48) 0x7335 VMOVAPS	0x260(%RSP),%XMM1

  (48) 0x733e VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (48) 0x7344 VMOVAPS	%XMM0,0xc0(%RSP)

  (48) 0x734d VMOVAPS	0x180(%RSP),%ZMM0

  (48) 0x7355 VZEROUPPER

  (48) 0x7358 CALL	1160 <expf@plt>

  (48) 0x735d VMOVAPS	%XMM0,0x260(%RSP)

  (48) 0x7366 VMOVSHDUP	0x180(%RSP),%XMM0

  (48) 0x736f CALL	1160 <expf@plt>

  (48) 0x7374 VMOVAPS	0x260(%RSP),%XMM1

  (48) 0x737d VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (48) 0x7383 VMOVAPS	%XMM0,0x260(%RSP)

  (48) 0x738c VPERMILPD	$0x1,0x180(%RSP),%XMM0

  (48) 0x7397 CALL	1160 <expf@plt>

  (48) 0x739c VMOVAPS	0x260(%RSP),%XMM1

  (48) 0x73a5 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (48) 0x73ab VMOVAPS	%XMM0,0x260(%RSP)

  (48) 0x73b4 VPERMILPS	$-0x1,0x180(%RSP),%XMM0

  (48) 0x73bf CALL	1160 <expf@plt>

  (48) 0x73c4 VMOVAPS	0x260(%RSP),%XMM1

  (48) 0x73cd VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (48) 0x73d3 VINSERTF128	$0x1,0xc0(%RSP),%YMM0,%YMM0

  (48) 0x73de VMOVAPS	0x540(%RSP),%ZMM1

  (48) 0x73e6 VINSERTF64X4	$0x1,0x40(%RSP),%ZMM0,%ZMM0

  (48) 0x73ef VADDPS	%ZMM1,%ZMM0,%ZMM1

  (48) 0x73f5 VMOVAPS	0x200(%RSP),%ZMM0

  (48) 0x73fd VMOVAPS	%ZMM1,0x540(%RSP)

  (48) 0x7405 VEXTRACTF32X4	$0x3,%ZMM0,%XMM0

  (48) 0x740c VMOVAPS	%XMM0,0x180(%RSP)

  (48) 0x7415 VZEROUPPER

  (48) 0x7418 CALL	1160 <expf@plt>

  (48) 0x741d VMOVAPS	%XMM0,0xc0(%RSP)

  (48) 0x7426 VMOVSHDUP	0x180(%RSP),%XMM0

  (48) 0x742f CALL	1160 <expf@plt>

  (48) 0x7434 VMOVAPS	0xc0(%RSP),%XMM1

  (48) 0x743d VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (48) 0x7443 VMOVAPS	%XMM0,0xc0(%RSP)

  (48) 0x744c VPERMILPD	$0x1,0x180(%RSP),%XMM0

  (48) 0x7457 CALL	1160 <expf@plt>

  (48) 0x745c VMOVAPS	0xc0(%RSP),%XMM1

  (48) 0x7465 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (48) 0x746b VMOVAPS	%XMM0,0xc0(%RSP)

  (48) 0x7474 VPERMILPS	$-0x1,0x180(%RSP),%XMM0

  (48) 0x747f CALL	1160 <expf@plt>

  (48) 0x7484 VMOVAPS	0xc0(%RSP),%XMM1

  (48) 0x748d VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (48) 0x7493 VMOVAPS	%XMM0,0xc0(%RSP)

  (48) 0x749c VMOVAPS	0x200(%RSP),%ZMM0

  (48) 0x74a4 VEXTRACTF32X4	$0x2,%ZMM0,%XMM0

  (48) 0x74ab VMOVAPS	%XMM0,0x180(%RSP)

  (48) 0x74b4 VZEROUPPER

  (48) 0x74b7 CALL	1160 <expf@plt>

  (48) 0x74bc VMOVAPS	%XMM0,0x40(%RSP)

  (48) 0x74c2 VMOVSHDUP	0x180(%RSP),%XMM0

  (48) 0x74cb CALL	1160 <expf@plt>

  (48) 0x74d0 VMOVAPS	0x40(%RSP),%XMM1

  (48) 0x74d6 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (48) 0x74dc VMOVAPS	%XMM0,0x40(%RSP)

  (48) 0x74e2 VPERMILPD	$0x1,0x180(%RSP),%XMM0

  (48) 0x74ed CALL	1160 <expf@plt>

  (48) 0x74f2 VMOVAPS	0x40(%RSP),%XMM1

  (48) 0x74f8 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (48) 0x74fe VMOVAPS	%XMM0,0x40(%RSP)

  (48) 0x7504 VPERMILPS	$-0x1,0x180(%RSP),%XMM0

  (48) 0x750f CALL	1160 <expf@plt>

  (48) 0x7514 VMOVAPS	0x40(%RSP),%XMM1

  (48) 0x751a VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (48) 0x7520 VINSERTF128	$0x1,0xc0(%RSP),%YMM0,%YMM0

  (48) 0x752b VMOVAPS	%YMM0,0xc0(%RSP)

  (48) 0x7534 VMOVAPS	0x200(%RSP),%ZMM0

  (48) 0x753c VEXTRACTF128	$0x1,%YMM0,%XMM0

  (48) 0x7542 VMOVAPS	%XMM0,0x180(%RSP)

  (48) 0x754b VZEROUPPER

  (48) 0x754e CALL	1160 <expf@plt>

  (48) 0x7553 VMOVAPS	%XMM0,0x40(%RSP)

  (48) 0x7559 VMOVSHDUP	0x180(%RSP),%XMM0

  (48) 0x7562 CALL	1160 <expf@plt>

  (48) 0x7567 VMOVAPS	0x40(%RSP),%XMM1

  (48) 0x756d VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (48) 0x7573 VMOVAPS	%XMM0,0x40(%RSP)

  (48) 0x7579 VPERMILPD	$0x1,0x180(%RSP),%XMM0

  (48) 0x7584 CALL	1160 <expf@plt>

  (48) 0x7589 VMOVAPS	0x40(%RSP),%XMM1

  (48) 0x758f VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (48) 0x7595 VMOVAPS	%XMM0,0x40(%RSP)

  (48) 0x759b VPERMILPS	$-0x1,0x180(%RSP),%XMM0

  (48) 0x75a6 CALL	1160 <expf@plt>

  (48) 0x75ab VMOVAPS	0x40(%RSP),%XMM1

  (48) 0x75b1 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (48) 0x75b7 VMOVAPS	%XMM0,0x180(%RSP)

  (48) 0x75c0 VMOVAPS	0x200(%RSP),%ZMM0

  (48) 0x75c8 VZEROUPPER

  (48) 0x75cb CALL	1160 <expf@plt>

  (48) 0x75d0 VMOVAPS	%XMM0,0x40(%RSP)

  (48) 0x75d6 VMOVSHDUP	0x200(%RSP),%XMM0

  (48) 0x75df CALL	1160 <expf@plt>

  (48) 0x75e4 VMOVAPS	0x40(%RSP),%XMM1

  (48) 0x75ea VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (48) 0x75f0 VMOVAPS	%XMM0,0x40(%RSP)

  (48) 0x75f6 VPERMILPD	$0x1,0x200(%RSP),%XMM0

  (48) 0x7601 CALL	1160 <expf@plt>

  (48) 0x7606 VMOVAPS	0x40(%RSP),%XMM1

  (48) 0x760c VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (48) 0x7612 VMOVAPS	%XMM0,0x40(%RSP)

  (48) 0x7618 VPERMILPS	$-0x1,0x200(%RSP),%XMM0

  (48) 0x7623 CALL	1160 <expf@plt>

  (48) 0x7628 VMOVAPS	0x40(%RSP),%XMM1

  (48) 0x762e VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (48) 0x7634 VINSERTF128	$0x1,0x180(%RSP),%YMM0,%YMM0

  (48) 0x763f VMOVAPS	0x5c0(%RSP),%ZMM1

  (48) 0x7647 VINSERTF64X4	$0x1,0xc0(%RSP),%ZMM0,%ZMM0

  (48) 0x7650 VADDPS	%ZMM1,%ZMM0,%ZMM1

  (48) 0x7656 VMOVAPS	0x2c0(%RSP),%ZMM0

  (48) 0x765e VMOVAPS	%ZMM1,0x5c0(%RSP)

  (48) 0x7666 VEXTRACTF32X4	$0x3,%ZMM0,%XMM0

  (48) 0x766d VMOVAPS	%XMM0,0x200(%RSP)

  (48) 0x7676 VZEROUPPER

  (48) 0x7679 CALL	1160 <expf@plt>

  (48) 0x767e VMOVAPS	%XMM0,0x180(%RSP)

  (48) 0x7687 VMOVSHDUP	0x200(%RSP),%XMM0

  (48) 0x7690 CALL	1160 <expf@plt>

  (48) 0x7695 VMOVAPS	0x180(%RSP),%XMM1

  (48) 0x769e VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (48) 0x76a4 VMOVAPS	%XMM0,0x180(%RSP)

  (48) 0x76ad VPERMILPD	$0x1,0x200(%RSP),%XMM0

  (48) 0x76b8 CALL	1160 <expf@plt>

  (48) 0x76bd VMOVAPS	0x180(%RSP),%XMM1

  (48) 0x76c6 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (48) 0x76cc VMOVAPS	%XMM0,0x180(%RSP)

  (48) 0x76d5 VPERMILPS	$-0x1,0x200(%RSP),%XMM0

  (48) 0x76e0 CALL	1160 <expf@plt>

  (48) 0x76e5 VMOVAPS	0x180(%RSP),%XMM1

  (48) 0x76ee VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (48) 0x76f4 VMOVAPS	%XMM0,0x180(%RSP)

  (48) 0x76fd VMOVAPS	0x2c0(%RSP),%ZMM0

  (48) 0x7705 VEXTRACTF32X4	$0x2,%ZMM0,%XMM0

  (48) 0x770c VMOVAPS	%XMM0,0x200(%RSP)

  (48) 0x7715 VZEROUPPER

  (48) 0x7718 CALL	1160 <expf@plt>

  (48) 0x771d VMOVAPS	%XMM0,0xc0(%RSP)

  (48) 0x7726 VMOVSHDUP	0x200(%RSP),%XMM0

  (48) 0x772f CALL	1160 <expf@plt>

  (48) 0x7734 VMOVAPS	0xc0(%RSP),%XMM1

  (48) 0x773d VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (48) 0x7743 VMOVAPS	%XMM0,0xc0(%RSP)

  (48) 0x774c VPERMILPD	$0x1,0x200(%RSP),%XMM0

  (48) 0x7757 CALL	1160 <expf@plt>

  (48) 0x775c VMOVAPS	0xc0(%RSP),%XMM1

  (48) 0x7765 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (48) 0x776b VMOVAPS	%XMM0,0xc0(%RSP)

  (48) 0x7774 VPERMILPS	$-0x1,0x200(%RSP),%XMM0

  (48) 0x777f CALL	1160 <expf@plt>

  (48) 0x7784 VMOVAPS	0xc0(%RSP),%XMM1

  (48) 0x778d VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (48) 0x7793 VINSERTF128	$0x1,0x180(%RSP),%YMM0,%YMM0

  (48) 0x779e VMOVAPS	%YMM0,0x180(%RSP)

  (48) 0x77a7 VMOVAPS	0x2c0(%RSP),%ZMM0

  (48) 0x77af VEXTRACTF128	$0x1,%YMM0,%XMM0

  (48) 0x77b5 VMOVAPS	%XMM0,0x200(%RSP)

  (48) 0x77be VZEROUPPER

  (48) 0x77c1 CALL	1160 <expf@plt>

  (48) 0x77c6 VMOVAPS	%XMM0,0xc0(%RSP)

  (48) 0x77cf VMOVSHDUP	0x200(%RSP),%XMM0

  (48) 0x77d8 CALL	1160 <expf@plt>

  (48) 0x77dd VMOVAPS	0xc0(%RSP),%XMM1

  (48) 0x77e6 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (48) 0x77ec VMOVAPS	%XMM0,0xc0(%RSP)

  (48) 0x77f5 VPERMILPD	$0x1,0x200(%RSP),%XMM0

  (48) 0x7800 CALL	1160 <expf@plt>

  (48) 0x7805 VMOVAPS	0xc0(%RSP),%XMM1

  (48) 0x780e VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (48) 0x7814 VMOVAPS	%XMM0,0xc0(%RSP)

  (48) 0x781d VPERMILPS	$-0x1,0x200(%RSP),%XMM0

  (48) 0x7828 CALL	1160 <expf@plt>

  (48) 0x782d VMOVAPS	0xc0(%RSP),%XMM1

  (48) 0x7836 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (48) 0x783c VMOVAPS	%XMM0,0x200(%RSP)

  (48) 0x7845 VMOVAPS	0x2c0(%RSP),%ZMM0

  (48) 0x784d VZEROUPPER

  (48) 0x7850 CALL	1160 <expf@plt>

  (48) 0x7855 VMOVAPS	%XMM0,0xc0(%RSP)

  (48) 0x785e VMOVSHDUP	0x2c0(%RSP),%XMM0

  (48) 0x7867 CALL	1160 <expf@plt>

  (48) 0x786c VMOVAPS	0xc0(%RSP),%XMM1

  (48) 0x7875 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (48) 0x787b VMOVAPS	%XMM0,0xc0(%RSP)

  (48) 0x7884 VPERMILPD	$0x1,0x2c0(%RSP),%XMM0

  (48) 0x788f CALL	1160 <expf@plt>

  (48) 0x7894 VMOVAPS	0xc0(%RSP),%XMM1

  (48) 0x789d VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (48) 0x78a3 VMOVAPS	%XMM0,0xc0(%RSP)

  (48) 0x78ac VPERMILPS	$-0x1,0x2c0(%RSP),%XMM0

  (48) 0x78b7 CALL	1160 <expf@plt>

  (48) 0x78bc VMOVAPS	0xc0(%RSP),%XMM2

  (48) 0x78c5 VMOVAPS	0x1a00(%RSP),%ZMM1

  (48) 0x78cd MOV	0x430(%RSP),%RDX

  (48) 0x78d5 ADD	$0x40,%RBX

  (48) 0x78d9 VINSERTPS	$0x30,%XMM0,%XMM2,%XMM0

  (48) 0x78df VINSERTF128	$0x1,0x200(%RSP),%YMM0,%YMM0

  (48) 0x78ea VINSERTF64X4	$0x1,0x180(%RSP),%ZMM0,%ZMM0

  (48) 0x78f3 VADDPS	%ZMM1,%ZMM0,%ZMM1

  (48) 0x78f9 CMP	%RBX,%R14

  (48) 0x78fc JNE	6eb5

0x7902 VMOVAPS	0x540(%RSP),%ZMM0

0x790a MOV	0x2b0(%RSP),%RBX

0x7912 MOV	0x390(%RSP),%R14

0x791a VADDPS	0x500(%RSP),%ZMM0,%ZMM0

0x7922 VADDPS	0x5c0(%RSP),%ZMM0,%ZMM0

0x792a VADDPS	%ZMM0,%ZMM1,%ZMM0

0x7930 VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

0x7937 VADDPS	%ZMM1,%ZMM0,%ZMM0

0x793d VEXTRACTF128	$0x1,%YMM0,%XMM1

0x7943 VADDPS	%XMM1,%XMM0,%XMM0

0x7947 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x794c VADDPS	%XMM1,%XMM0,%XMM0

0x7950 VMOVSHDUP	%XMM0,%XMM1

0x7954 VADDSS	%XMM1,%XMM0,%XMM2

0x7958 CMP	%R14,%RBX

0x795b JNE	796b

0x795d VMOVAPS	0x160(%RSP),%XMM1

0x7966 JMP	7b8f

0x796b VMOVAPS	0x160(%RSP),%XMM1

0x7974 MOV	0x478(%RSP),%RSI

0x797c TEST	$0x38,%BL

0x797f JE	7b56

0x7985 MOV	$0x7fffffffffffffc0,%RCX

0x798f VXORPS	%XMM0,%XMM0,%XMM0

0x7993 VMOVSS	%XMM2,%XMM0,%XMM2

0x7997 VBROADCASTSS	%XMM1,%YMM0

0x799c MOV	%RBX,%RAX

0x799f MOV	%R14,%RBX

0x79a2 ADD	$0x38,%RCX

0x79a6 AND	%RAX,%RCX

0x79a9 VMOVAPS	%YMM0,0x40(%RSP)

0x79af MOV	%RCX,0x390(%RSP)

  (61) 0x79b7 VMOVUPS	(%R15,%RBX,4),%YMM0

  (61) 0x79bd VMOVAPS	%YMM2,0x180(%RSP)

  (61) 0x79c6 MOV	%RSI,%R14

  (61) 0x79c9 VSUBPS	0x40(%RSP),%YMM0,%YMM0

  (61) 0x79cf VMOVAPS	%YMM0,0x2c0(%RSP)

  (61) 0x79d8 VEXTRACTF128	$0x1,%YMM0,%XMM0

  (61) 0x79de VMOVAPS	%XMM0,0x200(%RSP)

  (61) 0x79e7 VZEROUPPER

  (61) 0x79ea CALL	1160 <expf@plt>

  (61) 0x79ef VMOVAPS	%XMM0,0xc0(%RSP)

  (61) 0x79f8 VMOVSHDUP	0x200(%RSP),%XMM0

  (61) 0x7a01 CALL	1160 <expf@plt>

  (61) 0x7a06 VMOVAPS	0xc0(%RSP),%XMM1

  (61) 0x7a0f VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (61) 0x7a15 VMOVAPS	%XMM0,0xc0(%RSP)

  (61) 0x7a1e VPERMILPD	$0x1,0x200(%RSP),%XMM0

  (61) 0x7a29 CALL	1160 <expf@plt>

  (61) 0x7a2e VMOVAPS	0xc0(%RSP),%XMM1

  (61) 0x7a37 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (61) 0x7a3d VMOVAPS	%XMM0,0xc0(%RSP)

  (61) 0x7a46 VPERMILPS	$-0x1,0x200(%RSP),%XMM0

  (61) 0x7a51 CALL	1160 <expf@plt>

  (61) 0x7a56 VMOVAPS	0xc0(%RSP),%XMM1

  (61) 0x7a5f VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (61) 0x7a65 VMOVAPS	%XMM0,0x200(%RSP)

  (61) 0x7a6e VMOVAPS	0x2c0(%RSP),%YMM0

  (61) 0x7a77 VZEROUPPER

  (61) 0x7a7a CALL	1160 <expf@plt>

  (61) 0x7a7f VMOVAPS	%XMM0,0xc0(%RSP)

  (61) 0x7a88 VMOVSHDUP	0x2c0(%RSP),%XMM0

  (61) 0x7a91 CALL	1160 <expf@plt>

  (61) 0x7a96 VMOVAPS	0xc0(%RSP),%XMM1

  (61) 0x7a9f VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (61) 0x7aa5 VMOVAPS	%XMM0,0xc0(%RSP)

  (61) 0x7aae VPERMILPD	$0x1,0x2c0(%RSP),%XMM0

  (61) 0x7ab9 CALL	1160 <expf@plt>

  (61) 0x7abe VMOVAPS	0xc0(%RSP),%XMM1

  (61) 0x7ac7 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (61) 0x7acd VMOVAPS	%XMM0,0xc0(%RSP)

  (61) 0x7ad6 VPERMILPS	$-0x1,0x2c0(%RSP),%XMM0

  (61) 0x7ae1 CALL	1160 <expf@plt>

  (61) 0x7ae6 VMOVAPS	0xc0(%RSP),%XMM1

  (61) 0x7aef VMOVAPS	0x180(%RSP),%YMM2

  (61) 0x7af8 ADD	$0x8,%RBX

  (61) 0x7afc MOV	%R14,%RSI

  (61) 0x7aff VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (61) 0x7b05 VINSERTF128	$0x1,0x200(%RSP),%YMM0,%YMM0

  (61) 0x7b10 VADDPS	%YMM2,%YMM0,%YMM2

  (61) 0x7b14 CMP	%RBX,%R14

  (61) 0x7b17 JNE	79b7

0x7b1d VEXTRACTF128	$0x1,%YMM2,%XMM0

0x7b23 MOV	0x2b0(%RSP),%RBX

0x7b2b MOV	0x390(%RSP),%R14

0x7b33 VADDPS	%XMM0,%XMM2,%XMM0

0x7b37 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x7b3c VADDPS	%XMM1,%XMM0,%XMM0

0x7b40 VMOVSHDUP	%XMM0,%XMM1

0x7b44 VADDSS	%XMM1,%XMM0,%XMM2

0x7b48 VMOVAPS	0x160(%RSP),%XMM1

0x7b51 CMP	%R14,%RBX

0x7b54 JE	7b8f

  (49) 0x7b56 VMOVSS	(%R15,%R14,4),%XMM0

  (49) 0x7b5c VMOVAPS	%XMM2,0x2c0(%RSP)

  (49) 0x7b65 VSUBSS	%XMM1,%XMM0,%XMM0

  (49) 0x7b69 VZEROUPPER

  (49) 0x7b6c CALL	1160 <expf@plt>

  (49) 0x7b71 VMOVAPS	0x2c0(%RSP),%XMM2

  (49) 0x7b7a VMOVAPS	0x160(%RSP),%XMM1

  (49) 0x7b83 INC	%R14

  (49) 0x7b86 VADDSS	%XMM2,%XMM0,%XMM2

  (49) 0x7b8a CMP	%R14,%RBX

  (49) 0x7b8d JNE	7b56

0x7b8f VMOVAPS	%XMM2,0x2c0(%RSP)

0x7b98 CMP	$0x3,%RBX

0x7b9c JA	7bb0

0x7b9e MOV	0x398(%RSP),%RCX

0x7ba6 MOV	%RBX,%R14

0x7ba9 XOR	%EBX,%EBX

0x7bab JMP	7fcd

0x7bb0 MOV	0x398(%RSP),%R14

0x7bb8 CMP	$0x10,%RBX

0x7bbc JAE	7bcb

0x7bbe MOV	%R14,%RCX

0x7bc1 MOV	%RBX,%R14

0x7bc4 XOR	%EBX,%EBX

0x7bc6 JMP	7eb8

0x7bcb MOV	%RBX,%RAX

0x7bce AND	$-0x10,%RAX

0x7bd2 MOV	$0x7fffffffffffffc0,%RCX

0x7bdc VBROADCASTSS	%XMM2,%ZMM0

0x7be2 VBROADCASTSS	%XMM1,%ZMM1

0x7be8 XOR	%R13D,%R13D

0x7beb MOV	%RAX,0x500(%RSP)

0x7bf3 MOV	%RBX,%RAX

0x7bf6 LEA	0x30(%RCX),%RBX

0x7bfa AND	%RAX,%RBX

0x7bfd VMOVAPS	%ZMM0,0x540(%RSP)

0x7c05 VMOVAPS	%ZMM1,0x5c0(%RSP)

  (50) 0x7c0d VMOVUPS	(%R15,%R13,4),%ZMM0

  (50) 0x7c14 VSUBPS	0x5c0(%RSP),%ZMM0,%ZMM0

  (50) 0x7c1c VMOVAPS	%ZMM0,0x200(%RSP)

  (50) 0x7c24 VEXTRACTF32X4	$0x3,%ZMM0,%XMM0

  (50) 0x7c2b VMOVAPS	%XMM0,0x180(%RSP)

  (50) 0x7c34 VZEROUPPER

  (50) 0x7c37 CALL	1160 <expf@plt>

  (50) 0x7c3c VMOVAPS	%XMM0,0xc0(%RSP)

  (50) 0x7c45 VMOVSHDUP	0x180(%RSP),%XMM0

  (50) 0x7c4e CALL	1160 <expf@plt>

  (50) 0x7c53 VMOVAPS	0xc0(%RSP),%XMM1

  (50) 0x7c5c VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (50) 0x7c62 VMOVAPS	%XMM0,0xc0(%RSP)

  (50) 0x7c6b VPERMILPD	$0x1,0x180(%RSP),%XMM0

  (50) 0x7c76 CALL	1160 <expf@plt>

  (50) 0x7c7b VMOVAPS	0xc0(%RSP),%XMM1

  (50) 0x7c84 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (50) 0x7c8a VMOVAPS	%XMM0,0xc0(%RSP)

  (50) 0x7c93 VPERMILPS	$-0x1,0x180(%RSP),%XMM0

  (50) 0x7c9e CALL	1160 <expf@plt>

  (50) 0x7ca3 VMOVAPS	0xc0(%RSP),%XMM1

  (50) 0x7cac VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (50) 0x7cb2 VMOVAPS	%XMM0,0xc0(%RSP)

  (50) 0x7cbb VMOVAPS	0x200(%RSP),%ZMM0

  (50) 0x7cc3 VEXTRACTF32X4	$0x2,%ZMM0,%XMM0

  (50) 0x7cca VMOVAPS	%XMM0,0x180(%RSP)

  (50) 0x7cd3 VZEROUPPER

  (50) 0x7cd6 CALL	1160 <expf@plt>

  (50) 0x7cdb VMOVAPS	%XMM0,0x40(%RSP)

  (50) 0x7ce1 VMOVSHDUP	0x180(%RSP),%XMM0

  (50) 0x7cea CALL	1160 <expf@plt>

  (50) 0x7cef VMOVAPS	0x40(%RSP),%XMM1

  (50) 0x7cf5 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (50) 0x7cfb VMOVAPS	%XMM0,0x40(%RSP)

  (50) 0x7d01 VPERMILPD	$0x1,0x180(%RSP),%XMM0

  (50) 0x7d0c CALL	1160 <expf@plt>

  (50) 0x7d11 VMOVAPS	0x40(%RSP),%XMM1

  (50) 0x7d17 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (50) 0x7d1d VMOVAPS	%XMM0,0x40(%RSP)

  (50) 0x7d23 VPERMILPS	$-0x1,0x180(%RSP),%XMM0

  (50) 0x7d2e CALL	1160 <expf@plt>

  (50) 0x7d33 VMOVAPS	0x40(%RSP),%XMM1

  (50) 0x7d39 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (50) 0x7d3f VINSERTF128	$0x1,0xc0(%RSP),%YMM0,%YMM0

  (50) 0x7d4a VMOVAPS	%YMM0,0xc0(%RSP)

  (50) 0x7d53 VMOVAPS	0x200(%RSP),%ZMM0

  (50) 0x7d5b VEXTRACTF128	$0x1,%YMM0,%XMM0

  (50) 0x7d61 VMOVAPS	%XMM0,0x180(%RSP)

  (50) 0x7d6a VZEROUPPER

  (50) 0x7d6d CALL	1160 <expf@plt>

  (50) 0x7d72 VMOVAPS	%XMM0,0x40(%RSP)

  (50) 0x7d78 VMOVSHDUP	0x180(%RSP),%XMM0

  (50) 0x7d81 CALL	1160 <expf@plt>

  (50) 0x7d86 VMOVAPS	0x40(%RSP),%XMM1

  (50) 0x7d8c VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (50) 0x7d92 VMOVAPS	%XMM0,0x40(%RSP)

  (50) 0x7d98 VPERMILPD	$0x1,0x180(%RSP),%XMM0

  (50) 0x7da3 CALL	1160 <expf@plt>

  (50) 0x7da8 VMOVAPS	0x40(%RSP),%XMM1

  (50) 0x7dae VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (50) 0x7db4 VMOVAPS	%XMM0,0x40(%RSP)

  (50) 0x7dba VPERMILPS	$-0x1,0x180(%RSP),%XMM0

  (50) 0x7dc5 CALL	1160 <expf@plt>

  (50) 0x7dca VMOVAPS	0x40(%RSP),%XMM1

  (50) 0x7dd0 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (50) 0x7dd6 VMOVAPS	%XMM0,0x180(%RSP)

  (50) 0x7ddf VMOVAPS	0x200(%RSP),%ZMM0

  (50) 0x7de7 VZEROUPPER

  (50) 0x7dea CALL	1160 <expf@plt>

  (50) 0x7def VMOVAPS	%XMM0,0x40(%RSP)

  (50) 0x7df5 VMOVSHDUP	0x200(%RSP),%XMM0

  (50) 0x7dfe CALL	1160 <expf@plt>

  (50) 0x7e03 VMOVAPS	0x40(%RSP),%XMM1

  (50) 0x7e09 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (50) 0x7e0f VMOVAPS	%XMM0,0x40(%RSP)

  (50) 0x7e15 VPERMILPD	$0x1,0x200(%RSP),%XMM0

  (50) 0x7e20 CALL	1160 <expf@plt>

  (50) 0x7e25 VMOVAPS	0x40(%RSP),%XMM1

  (50) 0x7e2b VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (50) 0x7e31 VMOVAPS	%XMM0,0x40(%RSP)

  (50) 0x7e37 VPERMILPS	$-0x1,0x200(%RSP),%XMM0

  (50) 0x7e42 CALL	1160 <expf@plt>

  (50) 0x7e47 VMOVAPS	0x40(%RSP),%XMM1

  (50) 0x7e4d VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (50) 0x7e53 VINSERTF128	$0x1,0x180(%RSP),%YMM0,%YMM0

  (50) 0x7e5e VINSERTF64X4	$0x1,0xc0(%RSP),%ZMM0,%ZMM0

  (50) 0x7e67 VDIVPS	0x540(%RSP),%ZMM0,%ZMM0

  (50) 0x7e6f VMOVUPS	%ZMM0,(%R14,%R13,4)

  (50) 0x7e76 ADD	$0x10,%R13

  (50) 0x7e7a CMP	%R13,0x500(%RSP)

  (50) 0x7e82 JNE	7c0d

0x7e88 VMOVAPS	0x160(%RSP),%XMM1

0x7e91 VMOVAPS	0x2c0(%RSP),%XMM2

0x7e9a MOV	%R14,%RCX

0x7e9d MOV	0x2b0(%RSP),%R14

0x7ea5 CMP	%RBX,%R14

0x7ea8 JE	800a

0x7eae TEST	$0xc,%R14B

0x7eb2 JE	7fcd

0x7eb8 MOV	%R14,%RAX

0x7ebb AND	$-0x4,%RAX

0x7ebf VBROADCASTSS	%XMM2,%XMM0

0x7ec4 VBROADCASTSS	%XMM1,%XMM1

0x7ec9 MOV	%RBX,%R13

0x7ecc MOV	%RAX,0xc0(%RSP)

0x7ed4 MOV	$0x7fffffffffffffc0,%RAX

0x7ede LEA	0x3c(%RAX),%RBX

0x7ee2 VMOVAPS	%XMM0,0x40(%RSP)

0x7ee8 VMOVAPS	%XMM1,0x500(%RSP)

0x7ef1 AND	%R14,%RBX

0x7ef4 MOV	%RCX,%R14

  (60) 0x7ef7 VMOVUPS	(%R15,%R13,4),%XMM0

  (60) 0x7efd VSUBPS	0x500(%RSP),%XMM0,%XMM0

  (60) 0x7f06 VMOVAPS	%XMM0,0x200(%RSP)

  (60) 0x7f0f VZEROUPPER

  (60) 0x7f12 CALL	1160 <expf@plt>

  (60) 0x7f17 VMOVAPS	%XMM0,0x180(%RSP)

  (60) 0x7f20 VMOVSHDUP	0x200(%RSP),%XMM0

  (60) 0x7f29 CALL	1160 <expf@plt>

  (60) 0x7f2e VMOVAPS	0x180(%RSP),%XMM1

  (60) 0x7f37 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

  (60) 0x7f3d VMOVAPS	%XMM0,0x180(%RSP)

  (60) 0x7f46 VPERMILPD	$0x1,0x200(%RSP),%XMM0

  (60) 0x7f51 CALL	1160 <expf@plt>

  (60) 0x7f56 VMOVAPS	0x180(%RSP),%XMM1

  (60) 0x7f5f VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

  (60) 0x7f65 VMOVAPS	%XMM0,0x180(%RSP)

  (60) 0x7f6e VPERMILPS	$-0x1,0x200(%RSP),%XMM0

  (60) 0x7f79 CALL	1160 <expf@plt>

  (60) 0x7f7e VMOVAPS	0x180(%RSP),%XMM1

  (60) 0x7f87 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

  (60) 0x7f8d VDIVPS	0x40(%RSP),%XMM0,%XMM0

  (60) 0x7f93 VMOVUPS	%XMM0,(%R14,%R13,4)

  (60) 0x7f99 ADD	$0x4,%R13

  (60) 0x7f9d CMP	%R13,0xc0(%RSP)

  (60) 0x7fa5 JNE	7ef7

0x7fab VMOVAPS	0x160(%RSP),%XMM1

0x7fb4 VMOVAPS	0x2c0(%RSP),%XMM2

0x7fbd MOV	%R14,%RCX

0x7fc0 MOV	0x2b0(%RSP),%R14

0x7fc8 CMP	%RBX,%R14

0x7fcb JE	800a

  (59) 0x7fcd VMOVSS	(%R15,%RBX,4),%XMM0

  (59) 0x7fd3 MOV	%RCX,%R13

  (59) 0x7fd6 VSUBSS	%XMM1,%XMM0,%XMM0

  (59) 0x7fda VZEROUPPER

  (59) 0x7fdd CALL	1160 <expf@plt>

  (59) 0x7fe2 VMOVAPS	0x2c0(%RSP),%XMM2

  (59) 0x7feb VMOVAPS	0x160(%RSP),%XMM1

  (59) 0x7ff4 MOV	%R13,%RCX

  (59) 0x7ff7 VDIVSS	%XMM2,%XMM0,%XMM0

  (59) 0x7ffb VMOVSS	%XMM0,(%R13,%RBX,4)

  (59) 0x8002 INC	%RBX

  (59) 0x8005 CMP	%RBX,%R14

  (59) 0x8008 JNE	7fcd

0x800a MOV	%R15,%R14

0x800d MOV	0x428(%RSP),%R15

0x8015 MOV	0x90(%RSP),%R13

0x801d LEA	0x1(%R15),%RBX

0x8021 CMP	%R13,%RBX

0x8024 JAE	6caf

0x802a MOV	0x4b0(%RSP),%RDI

0x8032 MOV	0x4b8(%RSP),%RDX

0x803a SUB	%R15D,%EDX

0x803d MOV	$0x3fffffffc,%RAX

0x8047 XOR	%ESI,%ESI

0x8049 SAL	$0x2,%RDX

0x804d AND	%RAX,%RDX

0x8050 ADD	$0x4,%RDX

0x8054 IMUL	%R15,%RDI

0x8058 ADD	$0x4,%RDI

0x805c AND	%RAX,%RDI

0x805f ADD	%R12,%RDI

0x8062 VZEROUPPER

0x8065 CALL	1090 <memset@plt>

0x806a VMOVAPS	0x2c0(%RSP),%XMM2

0x8073 JMP	6caf

/home/eoseret/llm-attention/attention_v2.cpp: 43 - 61

--------------------------------------------------------------------------------

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.06
CQA speedup if FP arith vectorized	1.02
CQA speedup if fully vectorized	1.58
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.02
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:43-44,attention_v2.cpp:47-47,attention_v2.cpp:52-52,attention_v2.cpp:55-55,attention_v2.cpp:58-61
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	26.75
CQA cycles if no scalar integer	13.00
CQA cycles if FP arith vectorized	26.12
CQA cycles if fully vectorized	16.88
Front-end cycles	26.75
P0 cycles	12.50
P1 cycles	12.50
P2 cycles	12.50
P3 cycles	12.50
P4 cycles	12.50
P5 cycles	12.50
P6 cycles	13.25
P7 cycles	13.25
P8 cycles	13.25
P9 cycles	13.25
P10 cycles	10.50
P11 cycles	10.50
P12 cycles	10.50
P13 cycles	10.50
P14 cycles	9.00
P15 cycles	9.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	207.00
Nb uops	214.00
Nb loads	32.00
Nb stores	21.00
Nb stack references	19.00
FLOP/cycle	3.07
Nb FLOP add-sub	82.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	38.58
Bytes prefetched	0.00
Bytes loaded	476.00
Bytes stored	556.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	43.70
Vectorization ratio load	42.31
Vectorization ratio store	52.38
Vectorization ratio mul	NA
Vectorization ratio add_sub	61.54
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	39.74
Vector-efficiency ratio all	26.67
Vector-efficiency ratio load	25.72
Vector-efficiency ratio store	41.37
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	41.83
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	22.12

Metric	Value
CQA speedup if no scalar integer	2.06
CQA speedup if FP arith vectorized	1.02
CQA speedup if fully vectorized	1.58
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.02
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:43-44,attention_v2.cpp:47-47,attention_v2.cpp:52-52,attention_v2.cpp:55-55,attention_v2.cpp:58-61
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	26.75
CQA cycles if no scalar integer	13.00
CQA cycles if FP arith vectorized	26.12
CQA cycles if fully vectorized	16.88
Front-end cycles	26.75
P0 cycles	12.50
P1 cycles	12.50
P2 cycles	12.50
P3 cycles	12.50
P4 cycles	12.50
P5 cycles	12.50
P6 cycles	13.25
P7 cycles	13.25
P8 cycles	13.25
P9 cycles	13.25
P10 cycles	10.50
P11 cycles	10.50
P12 cycles	10.50
P13 cycles	10.50
P14 cycles	9.00
P15 cycles	9.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	207.00
Nb uops	214.00
Nb loads	32.00
Nb stores	21.00
Nb stack references	19.00
FLOP/cycle	3.07
Nb FLOP add-sub	82.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	38.58
Bytes prefetched	0.00
Bytes loaded	476.00
Bytes stored	556.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	43.70
Vectorization ratio load	42.31
Vectorization ratio store	52.38
Vectorization ratio mul	NA
Vectorization ratio add_sub	61.54
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	39.74
Vector-efficiency ratio all	26.67
Vector-efficiency ratio load	25.72
Vector-efficiency ratio store	41.37
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	41.83
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	22.12

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:43-61
Module	attention-clang-znver5-512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-61.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-44,47,52,55,58-61.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 490 paths individually, rerun with max-paths=490
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 490 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 26.75 to 13.00 cycles (2.06x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 26% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 26.75 to 16.88 cycles (1.58x speedup).

Details

43% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

42% of SSE/AVX loads are used in vector version.
52% of SSE/AVX stores are used in vector version.
61% of SSE/AVX addition or subtraction instructions are used in vector version.
39% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

memset@plt: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVAPS: 6 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:52
- /home/eoseret/llm-attention/attention_v2.cpp:52
- /home/eoseret/llm-attention/attention_v2.cpp:52
- /home/eoseret/llm-attention/attention_v2.cpp:52
- /home/eoseret/llm-attention/attention_v2.cpp:55
- /home/eoseret/llm-attention/attention_v2.cpp:55

Vector unaligned load/store instructions

Detected 6 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:47
- /home/eoseret/llm-attention/attention_v2.cpp:47
- /home/eoseret/llm-attention/attention_v2.cpp:52
- /home/eoseret/llm-attention/attention_v2.cpp:52
VEXTRACTF64X4: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:47
- /home/eoseret/llm-attention/attention_v2.cpp:52

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 8 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time). 1 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time). 7 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 82 FP arithmetical operations:

82: addition or subtraction

The binary loop is loading 476 bytes (119 single precision FP elements). The binary loop is storing 556 bytes (139 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	207
nb uops	214
loop length	1068
used x86 registers	11
used mmx registers	0
used xmm registers	3
used ymm registers	3
used zmm registers	4
nb stack references	19

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	26.75 cycles
front end	26.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	12.50	12.50	12.50	12.50	12.50	12.50	13.25	13.25	13.25	13.25	10.50	10.50	10.50	10.50	9.00	9.00
cycles	12.50	12.50	12.50	12.50	12.50	12.50	13.25	13.25	13.25	13.25	10.50	10.50	10.50	10.50	9.00	9.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	26.75
Dispatch	13.25
Overall L1	26.75

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	2%

all	78%
load	78%
store	91%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	80%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	73%

INT+FP

all	43%
load	42%
store	52%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	61%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	39%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	38%
load	37%
store	63%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	51%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

INT+FP

all	26%
load	25%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	41%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 26.75 cycles. At this rate:

6% of peak load performance is reached (17.79 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (20.79 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 26.75 to 13.25 cycles (2.02x speedup).

ASM code

In the binary file, the address of the loop is: 6cfd

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0x2b0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x1d8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xa8(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x430(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x398(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,0x428(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSS %XMM2,(%RAX,%R15,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
MOV %R14,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
INC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RSI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RSI,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RSI,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 8078 <main+0x46c8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
AND $-0x8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x40,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
MOV %RDI,0x398(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 6d2b <main+0x337b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VMOVSS 0x22e0(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 6e1d <main+0x346d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
CMP $0x40,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 6d40 <main+0x3390>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VMOVSS 0x22cb(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 6dd8 <main+0x3428>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VBROADCASTSS 0x22ba(%RIP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1-2	0.50	scal (6.3%)
MOV $0x7fffffffffffffc0,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
AND %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPS %ZMM3,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPS %ZMM3,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPS %ZMM3,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMAXPS %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMAXPS %ZMM3,%ZMM2,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMAXPS %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25	vect (50.0%)
VMAXPS %YMM1,%YMM0,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
VMAXSS %XMM1,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (6.3%)
CMP %RAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 6e2b <main+0x347b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
TEST $0x38,%BL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 6e1d <main+0x346d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV $0x7fffffffffffffc0,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VBROADCASTSS %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1-2	0.50	scal (6.3%)
ADD $0x38,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
VMAXSS %XMM1,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (6.3%)
JMP 6e26 <main+0x3476>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV %RBX,0x2b0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPS %XMM1,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %RDX,0x430(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x7,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 6e56 <main+0x34a6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 7b56 <main+0x41a6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
CMP $0x40,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 6e68 <main+0x34b8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 7985 <main+0x3fd5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VBROADCASTSS %XMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1-2	0.50	scal (6.3%)
MOV $0x7fffffffffffffc0,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSI,0x478(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
AND %RAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RBX,0x390(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPS %ZMM0,0x19c0(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVAPS %ZMM0,0x500(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMOVAPS %ZMM0,0x540(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMOVAPS %ZMM0,0x5c0(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMOVAPS 0x540(%RSP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x2b0(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x390(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VADDPS 0x500(%RSP),%ZMM0,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPS 0x5c0(%RSP),%ZMM0,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPS %ZMM0,%ZMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25	vect (50.0%)
VADDPS %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (6.3%)
CMP %R14,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 796b <main+0x3fbb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VMOVAPS 0x160(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
JMP 7b8f <main+0x41df>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VMOVAPS 0x160(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV 0x478(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
TEST $0x38,%BL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 7b56 <main+0x41a6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV $0x7fffffffffffffc0,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS %XMM2,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0-2	0.25	scal (6.3%)
VBROADCASTSS %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1-2	0.50	scal (6.3%)
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV %R14,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
ADD $0x38,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %YMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
MOV %RCX,0x390(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VEXTRACTF128 $0x1,%YMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (25.0%)
MOV 0x2b0(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x390(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VADDPS %XMM0,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (6.3%)
VMOVAPS 0x160(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
CMP %R14,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 7b8f <main+0x41df>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VMOVAPS %XMM2,0x2c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
CMP $0x3,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 7bb0 <main+0x4200>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x398(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 7fcd <main+0x461d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV 0x398(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP $0x10,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 7bcb <main+0x421b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV %R14,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV %RBX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 7eb8 <main+0x4508>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
AND $-0x10,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x7fffffffffffffc0,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VBROADCASTSS %XMM2,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1-2	0.50	scal (6.3%)
VBROADCASTSS %XMM1,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1-2	0.50	scal (6.3%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %RAX,0x500(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
LEA 0x30(%RCX),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVAPS %ZMM0,0x540(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMOVAPS %ZMM1,0x5c0(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMOVAPS 0x160(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPS 0x2c0(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV %R14,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0x2b0(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %RBX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 800a <main+0x465a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
TEST $0xc,%R14B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 7fcd <main+0x461d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
AND $-0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VBROADCASTSS %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1-2	0.50	scal (6.3%)
VBROADCASTSS %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1-2	0.50	scal (6.3%)
MOV %RBX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
MOV %RAX,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV $0x7fffffffffffffc0,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA 0x3c(%RAX),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPS %XMM1,0x500(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
AND %R14,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
VMOVAPS 0x160(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPS 0x2c0(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV %R14,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0x2b0(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %RBX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 800a <main+0x465a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV %R15,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
MOV 0x428(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x90(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
LEA 0x1(%R15),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 6caf <main+0x32ff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x4b0(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x4b8(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
SUB %R15D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x3fffffffc,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SAL $0x2,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
AND %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R15,%RDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD $0x4,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R12,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1090 <memset@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0x2c0(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
JMP 6caf <main+0x32ff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:43-61
Module	attention-clang-znver5-512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-61.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-44,47,52,55,58-61.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 490 paths individually, rerun with max-paths=490
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

43% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

42% of SSE/AVX loads are used in vector version.
52% of SSE/AVX stores are used in vector version.
61% of SSE/AVX addition or subtraction instructions are used in vector version.
39% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

memset@plt: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVAPS: 6 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:52
- /home/eoseret/llm-attention/attention_v2.cpp:52
- /home/eoseret/llm-attention/attention_v2.cpp:52
- /home/eoseret/llm-attention/attention_v2.cpp:52
- /home/eoseret/llm-attention/attention_v2.cpp:55
- /home/eoseret/llm-attention/attention_v2.cpp:55

Vector unaligned load/store instructions

Detected 6 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:47
- /home/eoseret/llm-attention/attention_v2.cpp:47
- /home/eoseret/llm-attention/attention_v2.cpp:52
- /home/eoseret/llm-attention/attention_v2.cpp:52
VEXTRACTF64X4: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:47
- /home/eoseret/llm-attention/attention_v2.cpp:52

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 82 FP arithmetical operations:

82: addition or subtraction

The binary loop is loading 476 bytes (119 single precision FP elements). The binary loop is storing 556 bytes (139 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	207
nb uops	214
loop length	1068
used x86 registers	11
used mmx registers	0
used xmm registers	3
used ymm registers	3
used zmm registers	4
nb stack references	19

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	26.75 cycles
front end	26.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	12.50	12.50	12.50	12.50	12.50	12.50	13.25	13.25	13.25	13.25	10.50	10.50	10.50	10.50	9.00	9.00
cycles	12.50	12.50	12.50	12.50	12.50	12.50	13.25	13.25	13.25	13.25	10.50	10.50	10.50	10.50	9.00	9.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	26.75
Dispatch	13.25
Overall L1	26.75

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	2%

all	78%
load	78%
store	91%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	80%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	73%

INT+FP

all	43%
load	42%
store	52%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	61%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	39%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	38%
load	37%
store	63%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	51%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

INT+FP

all	26%
load	25%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	41%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 26.75 cycles. At this rate:

6% of peak load performance is reached (17.79 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (20.79 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 6cfd

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0x2b0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x1d8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xa8(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x430(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x398(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,0x428(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSS %XMM2,(%RAX,%R15,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
MOV %R14,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
INC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RSI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RSI,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RSI,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 8078 <main+0x46c8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
AND $-0x8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $-0x40,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
MOV %RDI,0x398(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 6d2b <main+0x337b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VMOVSS 0x22e0(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 6e1d <main+0x346d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
CMP $0x40,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 6d40 <main+0x3390>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VMOVSS 0x22cb(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 6dd8 <main+0x3428>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VBROADCASTSS 0x22ba(%RIP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1-2	0.50	scal (6.3%)
MOV $0x7fffffffffffffc0,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
AND %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPS %ZMM3,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPS %ZMM3,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPS %ZMM3,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMAXPS %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMAXPS %ZMM3,%ZMM2,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMAXPS %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25	vect (50.0%)
VMAXPS %YMM1,%YMM0,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
VMAXSS %XMM1,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (6.3%)
CMP %RAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 6e2b <main+0x347b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
TEST $0x38,%BL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 6e1d <main+0x346d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV $0x7fffffffffffffc0,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VBROADCASTSS %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1-2	0.50	scal (6.3%)
ADD $0x38,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
VMAXSS %XMM1,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (6.3%)
JMP 6e26 <main+0x3476>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV %RBX,0x2b0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPS %XMM1,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %RDX,0x430(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x7,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 6e56 <main+0x34a6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 7b56 <main+0x41a6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
CMP $0x40,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 6e68 <main+0x34b8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 7985 <main+0x3fd5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VBROADCASTSS %XMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1-2	0.50	scal (6.3%)
MOV $0x7fffffffffffffc0,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RSI,0x478(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
AND %RAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RBX,0x390(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPS %ZMM0,0x19c0(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVAPS %ZMM0,0x500(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMOVAPS %ZMM0,0x540(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMOVAPS %ZMM0,0x5c0(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMOVAPS 0x540(%RSP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x2b0(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x390(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VADDPS 0x500(%RSP),%ZMM0,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPS 0x5c0(%RSP),%ZMM0,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPS %ZMM0,%ZMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25	vect (50.0%)
VADDPS %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (6.3%)
CMP %R14,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 796b <main+0x3fbb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VMOVAPS 0x160(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
JMP 7b8f <main+0x41df>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VMOVAPS 0x160(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV 0x478(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
TEST $0x38,%BL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 7b56 <main+0x41a6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV $0x7fffffffffffffc0,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS %XMM2,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0-2	0.25	scal (6.3%)
VBROADCASTSS %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1-2	0.50	scal (6.3%)
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV %R14,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
ADD $0x38,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %YMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
MOV %RCX,0x390(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VEXTRACTF128 $0x1,%YMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (25.0%)
MOV 0x2b0(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x390(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VADDPS %XMM0,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (6.3%)
VMOVAPS 0x160(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
CMP %R14,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 7b8f <main+0x41df>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VMOVAPS %XMM2,0x2c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
CMP $0x3,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 7bb0 <main+0x4200>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x398(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 7fcd <main+0x461d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV 0x398(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP $0x10,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 7bcb <main+0x421b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV %R14,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV %RBX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 7eb8 <main+0x4508>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
AND $-0x10,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x7fffffffffffffc0,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VBROADCASTSS %XMM2,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1-2	0.50	scal (6.3%)
VBROADCASTSS %XMM1,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1-2	0.50	scal (6.3%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %RAX,0x500(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
LEA 0x30(%RCX),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVAPS %ZMM0,0x540(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMOVAPS %ZMM1,0x5c0(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMOVAPS 0x160(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPS 0x2c0(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV %R14,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0x2b0(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %RBX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 800a <main+0x465a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
TEST $0xc,%R14B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 7fcd <main+0x461d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
AND $-0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VBROADCASTSS %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1-2	0.50	scal (6.3%)
VBROADCASTSS %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1-2	0.50	scal (6.3%)
MOV %RBX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
MOV %RAX,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV $0x7fffffffffffffc0,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA 0x3c(%RAX),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPS %XMM1,0x500(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
AND %R14,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
VMOVAPS 0x160(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVAPS 0x2c0(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV %R14,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0x2b0(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %RBX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 800a <main+0x465a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV %R15,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
MOV 0x428(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x90(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
LEA 0x1(%R15),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 6caf <main+0x32ff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x4b0(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x4b8(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
SUB %R15D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x3fffffffc,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SAL $0x2,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
AND %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R15,%RDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD $0x4,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R12,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1090 <memset@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0x2c0(%RSP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
JMP 6caf <main+0x32ff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code