OV - attention-clang-znver5-512 - Loop 50 - attention-clang-znver5-512

	Loop Id: 50	Module: attention-clang-znver5-512	Source: attention_v2.cpp:55-56	Coverage: 0.86%

0x7c0d VMOVUPS	(%R15,%R13,4),%ZMM0    [2]

0x7c14 VSUBPS	0x5c0(%RSP),%ZMM0,%ZMM0    [1]

0x7c1c VMOVAPS	%ZMM0,0x200(%RSP)    [1]

0x7c24 VEXTRACTF32X4	$0x3,%ZMM0,%XMM0

0x7c2b VMOVAPS	%XMM0,0x180(%RSP)    [1]

0x7c34 VZEROUPPER

0x7c37 CALL	1160 <expf@plt>

0x7c3c VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x7c45 VMOVSHDUP	0x180(%RSP),%XMM0    [1]

0x7c4e CALL	1160 <expf@plt>

0x7c53 VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x7c5c VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x7c62 VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x7c6b VPERMILPD	$0x1,0x180(%RSP),%XMM0    [1]

0x7c76 CALL	1160 <expf@plt>

0x7c7b VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x7c84 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x7c8a VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x7c93 VPERMILPS	$-0x1,0x180(%RSP),%XMM0    [1]

0x7c9e CALL	1160 <expf@plt>

0x7ca3 VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x7cac VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x7cb2 VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x7cbb VMOVAPS	0x200(%RSP),%ZMM0    [1]

0x7cc3 VEXTRACTF32X4	$0x2,%ZMM0,%XMM0

0x7cca VMOVAPS	%XMM0,0x180(%RSP)    [1]

0x7cd3 VZEROUPPER

0x7cd6 CALL	1160 <expf@plt>

0x7cdb VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x7ce1 VMOVSHDUP	0x180(%RSP),%XMM0    [1]

0x7cea CALL	1160 <expf@plt>

0x7cef VMOVAPS	0x40(%RSP),%XMM1    [1]

0x7cf5 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x7cfb VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x7d01 VPERMILPD	$0x1,0x180(%RSP),%XMM0    [1]

0x7d0c CALL	1160 <expf@plt>

0x7d11 VMOVAPS	0x40(%RSP),%XMM1    [1]

0x7d17 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x7d1d VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x7d23 VPERMILPS	$-0x1,0x180(%RSP),%XMM0    [1]

0x7d2e CALL	1160 <expf@plt>

0x7d33 VMOVAPS	0x40(%RSP),%XMM1    [1]

0x7d39 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x7d3f VINSERTF128	$0x1,0xc0(%RSP),%YMM0,%YMM0    [1]

0x7d4a VMOVAPS	%YMM0,0xc0(%RSP)    [1]

0x7d53 VMOVAPS	0x200(%RSP),%ZMM0    [1]

0x7d5b VEXTRACTF128	$0x1,%YMM0,%XMM0

0x7d61 VMOVAPS	%XMM0,0x180(%RSP)    [1]

0x7d6a VZEROUPPER

0x7d6d CALL	1160 <expf@plt>

0x7d72 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x7d78 VMOVSHDUP	0x180(%RSP),%XMM0    [1]

0x7d81 CALL	1160 <expf@plt>

0x7d86 VMOVAPS	0x40(%RSP),%XMM1    [1]

0x7d8c VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x7d92 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x7d98 VPERMILPD	$0x1,0x180(%RSP),%XMM0    [1]

0x7da3 CALL	1160 <expf@plt>

0x7da8 VMOVAPS	0x40(%RSP),%XMM1    [1]

0x7dae VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x7db4 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x7dba VPERMILPS	$-0x1,0x180(%RSP),%XMM0    [1]

0x7dc5 CALL	1160 <expf@plt>

0x7dca VMOVAPS	0x40(%RSP),%XMM1    [1]

0x7dd0 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x7dd6 VMOVAPS	%XMM0,0x180(%RSP)    [1]

0x7ddf VMOVAPS	0x200(%RSP),%ZMM0    [1]

0x7de7 VZEROUPPER

0x7dea CALL	1160 <expf@plt>

0x7def VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x7df5 VMOVSHDUP	0x200(%RSP),%XMM0    [1]

0x7dfe CALL	1160 <expf@plt>

0x7e03 VMOVAPS	0x40(%RSP),%XMM1    [1]

0x7e09 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x7e0f VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x7e15 VPERMILPD	$0x1,0x200(%RSP),%XMM0    [1]

0x7e20 CALL	1160 <expf@plt>

0x7e25 VMOVAPS	0x40(%RSP),%XMM1    [1]

0x7e2b VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x7e31 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x7e37 VPERMILPS	$-0x1,0x200(%RSP),%XMM0    [1]

0x7e42 CALL	1160 <expf@plt>

0x7e47 VMOVAPS	0x40(%RSP),%XMM1    [1]

0x7e4d VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x7e53 VINSERTF128	$0x1,0x180(%RSP),%YMM0,%YMM0    [1]

0x7e5e VINSERTF64X4	$0x1,0xc0(%RSP),%ZMM0,%ZMM0    [1]

0x7e67 VDIVPS	0x540(%RSP),%ZMM0,%ZMM0    [1]

0x7e6f VMOVUPS	%ZMM0,(%R14,%R13,4)    [3]

0x7e76 ADD	$0x10,%R13

0x7e7a CMP	%R13,0x500(%RSP)    [1]

0x7e82 JNE	7c0d

/home/eoseret/llm-attention/attention_v2.cpp: 55 - 56

--------------------------------------------------------------------------------

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.23
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	micro-operation queue, P6, P7, P8, P9,
Function	main
Source	attention_v2.cpp:55-56
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	13.50
CQA cycles if no scalar integer	13.50
CQA cycles if FP arith vectorized	13.50
CQA cycles if fully vectorized	6.05
Front-end cycles	13.50
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	13.50
P7 cycles	13.50
P8 cycles	13.50
P9 cycles	13.50
P10 cycles	7.00
P11 cycles	7.00
P12 cycles	7.00
P13 cycles	7.00
P14 cycles	11.00
P15 cycles	11.00
DIV/SQRT cycles	2.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	91.00
Nb uops	108.00
Nb loads	34.00
Nb stores	20.00
Nb stack references	7.00
FLOP/cycle	2.37
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	94.22
Bytes prefetched	0.00
Bytes loaded	840.00
Bytes stored	432.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	83.33
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	60.00
Vector-efficiency ratio all	30.21
Vector-efficiency ratio load	37.88
Vector-efficiency ratio store	33.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	18.33

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.23
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	micro-operation queue, P6, P7, P8, P9,
Function	main
Source	attention_v2.cpp:55-56
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	13.50
CQA cycles if no scalar integer	13.50
CQA cycles if FP arith vectorized	13.50
CQA cycles if fully vectorized	6.05
Front-end cycles	13.50
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	13.50
P7 cycles	13.50
P8 cycles	13.50
P9 cycles	13.50
P10 cycles	7.00
P11 cycles	7.00
P12 cycles	7.00
P13 cycles	7.00
P14 cycles	11.00
P15 cycles	11.00
DIV/SQRT cycles	2.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	91.00
Nb uops	108.00
Nb loads	34.00
Nb stores	20.00
Nb stack references	7.00
FLOP/cycle	2.37
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	94.22
Bytes prefetched	0.00
Bytes loaded	840.00
Bytes stored	432.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	83.33
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	60.00
Vector-efficiency ratio all	30.21
Vector-efficiency ratio load	37.88
Vector-efficiency ratio store	33.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	18.33

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:55-56
Module	attention-clang-znver5-512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:55-56.

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 30% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 13.50 to 6.05 cycles (2.23x speedup).

Details

83% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

60% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 13.50 to 11.00 cycles (1.23x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

expf@plt: 16 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVAPS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
VMOVUPS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56

Vector unaligned load/store instructions

Detected 6 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
VEXTRACTF32X4: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
VINSERTF128: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
VINSERTF64X4: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

16: addition or subtraction
16: divide

The binary loop is loading 840 bytes (210 single precision FP elements). The binary loop is storing 432 bytes (108 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	91
nb uops	108
loop length	635
used x86 registers	4
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	1
nb stack references	7

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.50 cycles
front end	13.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	13.50	13.50	13.50	13.50	7.00	7.00	7.00	7.00	11.00	11.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	13.50	13.50	13.50	13.50	7.00	7.00	7.00	7.00	11.00	11.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	2.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	13.50
Dispatch	13.50
DIV/SQRT	2.50
Data deps.	1.00
Overall L1	13.50

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	82%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	53%

INT+FP

all	83%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	60%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	30%
load	37%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	17%

INT+FP

all	30%
load	37%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.50 cycles. At this rate:

24% of peak load performance is reached (62.22 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (32.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.50 to 11.00 cycles (1.23x speedup).

ASM code

In the binary file, the address of the loop is: 7c0d

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPS (%R15,%R13,4),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPS 0x5c0(%RSP),%ZMM0,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVAPS %ZMM0,0x200(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VEXTRACTF32X4 $0x3,%ZMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (25.0%)
VMOVAPS %XMM0,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSHDUP 0x180(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPERMILPD $0x1,0x180(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPERMILPS $-0x1,0x180(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPS 0x200(%RSP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF32X4 $0x2,%ZMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (25.0%)
VMOVAPS %XMM0,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSHDUP 0x180(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPERMILPD $0x1,0x180(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPERMILPS $-0x1,0x180(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VINSERTF128 $0x1,0xc0(%RSP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VMOVAPS %YMM0,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVAPS 0x200(%RSP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (25.0%)
VMOVAPS %XMM0,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSHDUP 0x180(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPERMILPD $0x1,0x180(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPERMILPS $-0x1,0x180(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VMOVAPS %XMM0,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPS 0x200(%RSP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSHDUP 0x200(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPERMILPD $0x1,0x200(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPERMILPS $-0x1,0x200(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VINSERTF128 $0x1,0x180(%RSP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VINSERTF64X4 $0x1,0xc0(%RSP),%ZMM0,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	1-2	0.50	vect (50.0%)
VDIVPS 0x540(%RSP),%ZMM0,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	10	2.50	vect (100.0%)
VMOVUPS %ZMM0,(%R14,%R13,4)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
ADD $0x10,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,0x500(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JNE 7c0d <main+0x425d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:55-56
Module	attention-clang-znver5-512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:55-56.

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

83% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

60% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 13.50 to 11.00 cycles (1.23x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

CALL instructions

Detected function call instructions.

Details

expf@plt: 16 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVAPS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
VMOVUPS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56

Vector unaligned load/store instructions

Detected 6 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
VEXTRACTF32X4: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
VINSERTF128: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
VINSERTF64X4: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

16: addition or subtraction
16: divide

The binary loop is loading 840 bytes (210 single precision FP elements). The binary loop is storing 432 bytes (108 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	91
nb uops	108
loop length	635
used x86 registers	4
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	1
nb stack references	7

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.50 cycles
front end	13.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	13.50	13.50	13.50	13.50	7.00	7.00	7.00	7.00	11.00	11.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	13.50	13.50	13.50	13.50	7.00	7.00	7.00	7.00	11.00	11.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	2.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	13.50
Dispatch	13.50
DIV/SQRT	2.50
Data deps.	1.00
Overall L1	13.50

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	82%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	53%

INT+FP

all	83%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	60%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	30%
load	37%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	17%

INT+FP

all	30%
load	37%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.50 cycles. At this rate:

24% of peak load performance is reached (62.22 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (32.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 7c0d

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPS (%R15,%R13,4),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VSUBPS 0x5c0(%RSP),%ZMM0,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VMOVAPS %ZMM0,0x200(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VEXTRACTF32X4 $0x3,%ZMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (25.0%)
VMOVAPS %XMM0,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSHDUP 0x180(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPERMILPD $0x1,0x180(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPERMILPS $-0x1,0x180(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPS 0x200(%RSP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF32X4 $0x2,%ZMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (25.0%)
VMOVAPS %XMM0,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSHDUP 0x180(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPERMILPD $0x1,0x180(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPERMILPS $-0x1,0x180(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VINSERTF128 $0x1,0xc0(%RSP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VMOVAPS %YMM0,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVAPS 0x200(%RSP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (25.0%)
VMOVAPS %XMM0,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSHDUP 0x180(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPERMILPD $0x1,0x180(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPERMILPS $-0x1,0x180(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VMOVAPS %XMM0,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPS 0x200(%RSP),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVSHDUP 0x200(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPERMILPD $0x1,0x200(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPERMILPS $-0x1,0x200(%RSP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	scal (6.3%)
VINSERTF128 $0x1,0x180(%RSP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VINSERTF64X4 $0x1,0xc0(%RSP),%ZMM0,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	1-2	0.50	vect (50.0%)
VDIVPS 0x540(%RSP),%ZMM0,%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	10	2.50	vect (100.0%)
VMOVUPS %ZMM0,(%R14,%R13,4)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
ADD $0x10,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,0x500(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JNE 7c0d <main+0x425d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A

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CALL instructions

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Complex instructions

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Vector unaligned load/store instructions

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code