OV - attention-clang-znver5-512 - Loop 44 - attention-clang-znver5-512

	Loop Id: 44	Module: attention-clang-znver5-512	Source: attention_v2.cpp:30-31	Coverage: 5.67%

0x6150 LEA	(%RCX,%R9,1),%R11D

0x6154 VMOVSS	(%R14,%R11,4),%XMM1    [2]

0x615a MOV	%R10D,%R11D

0x615d VMOVSS	(%R13,%R11,4),%XMM2    [3]

0x6164 LEA	0x1(%RCX,%R9,1),%R11D

0x6169 VMOVSS	(%R14,%R11,4),%XMM3    [2]

0x616f LEA	(%RBX,%R10,1),%R11D

0x6173 LEA	0x6(%RCX,%R9,1),%EBX

0x6178 VMOVSS	(%R13,%R11,4),%XMM4    [3]

0x617f LEA	0x2(%RCX,%R9,1),%R11D

0x6184 VMOVSS	(%R14,%RBX,4),%XMM13    [2]

0x618a MOV	0x38(%RSP),%RBX    [1]

0x618f VMOVSS	(%R14,%R11,4),%XMM5    [2]

0x6195 LEA	(%RSI,%R10,1),%R11D

0x6199 VMOVSS	(%R13,%R11,4),%XMM6    [3]

0x61a0 LEA	0x3(%RCX,%R9,1),%R11D

0x61a5 VCVTSS2SD	%XMM1,%XMM1,%XMM1

0x61a9 VCVTSS2SD	%XMM2,%XMM2,%XMM2

0x61ad VMOVSS	(%R14,%R11,4),%XMM7    [2]

0x61b3 LEA	(%RDX,%R10,1),%R11D

0x61b7 VMOVSS	(%R13,%R11,4),%XMM8    [3]

0x61be LEA	0x4(%RCX,%R9,1),%R11D

0x61c3 VFMADD213SD	%XMM0,%XMM1,%XMM2

0x61c8 VCVTSS2SD	%XMM3,%XMM3,%XMM0

0x61cc VMOVSS	(%R14,%R11,4),%XMM9    [2]

0x61d2 LEA	(%R15,%R10,1),%R11D

0x61d6 VMOVSS	(%R13,%R11,4),%XMM10    [3]

0x61dd LEA	0x5(%RCX,%R9,1),%R11D

0x61e2 VCVTSS2SD	%XMM4,%XMM4,%XMM1

0x61e6 VMOVSS	(%R14,%R11,4),%XMM11    [2]

0x61ec LEA	(%R8,%R10,1),%R11D

0x61f0 VMOVSS	(%R13,%R11,4),%XMM12    [3]

0x61f7 LEA	(%R12,%R10,1),%R11D

0x61fb VMOVSS	(%R13,%R11,4),%XMM14    [3]

0x6202 LEA	0x7(%RCX,%R9,1),%R11D

0x6207 ADD	$0x8,%R9

0x620b VFMADD213SD	%XMM2,%XMM0,%XMM1

0x6210 VCVTSS2SD	%XMM5,%XMM5,%XMM0

0x6214 VMOVSS	(%R14,%R11,4),%XMM15    [2]

0x621a LEA	(%RDI,%R10,1),%R11D

0x621e ADD	%RAX,%R10

0x6221 VMOVSS	(%R13,%R11,4),%XMM16    [3]

0x6229 VCVTSS2SD	%XMM6,%XMM6,%XMM2

0x622d VFMADD213SD	%XMM1,%XMM0,%XMM2

0x6232 VCVTSS2SD	%XMM7,%XMM7,%XMM0

0x6236 VCVTSS2SD	%XMM8,%XMM8,%XMM1

0x623b VFMADD213SD	%XMM2,%XMM0,%XMM1

0x6240 VCVTSS2SD	%XMM9,%XMM9,%XMM0

0x6245 VCVTSS2SD	%XMM10,%XMM10,%XMM2

0x624a VFMADD213SD	%XMM1,%XMM0,%XMM2

0x624f VCVTSS2SD	%XMM11,%XMM11,%XMM0

0x6254 VCVTSS2SD	%XMM12,%XMM12,%XMM1

0x6259 VFMADD213SD	%XMM2,%XMM0,%XMM1

0x625e VCVTSS2SD	%XMM13,%XMM13,%XMM0

0x6263 VCVTSS2SD	%XMM14,%XMM14,%XMM2

0x6268 VFMADD213SD	%XMM1,%XMM0,%XMM2

0x626d VCVTSS2SD	%XMM15,%XMM15,%XMM1

0x6272 VCVTSS2SD	%XMM16,%XMM16,%XMM0

0x6278 VFMADD213SD	%XMM2,%XMM1,%XMM0

0x627d CMP	%R9,0x380(%RSP)    [1]

0x6285 JNE	6150

/home/eoseret/llm-attention/attention_v2.cpp: 30 - 31

--------------------------------------------------------------------------------

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.71
CQA speedup if fully vectorized	14.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.82
Bottlenecks
Function	main
Source	attention_v2.cpp:30-31
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.00
CQA cycles if no scalar integer	32.00
CQA cycles if FP arith vectorized	18.69
CQA cycles if fully vectorized	2.26
Front-end cycles	8.38
P0 cycles	2.83
P1 cycles	2.83
P2 cycles	3.50
P3 cycles	3.50
P4 cycles	2.67
P5 cycles	2.67
P6 cycles	6.25
P7 cycles	6.25
P8 cycles	6.25
P9 cycles	6.25
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	8.00
P13 cycles	8.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	32
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	61.00
Nb uops	67.00
Nb loads	18.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.50
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.50
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	1.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.50
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.71
CQA speedup if fully vectorized	14.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.82
Bottlenecks
Function	main
Source	attention_v2.cpp:30-31
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.00
CQA cycles if no scalar integer	32.00
CQA cycles if FP arith vectorized	18.69
CQA cycles if fully vectorized	2.26
Front-end cycles	8.38
P0 cycles	2.83
P1 cycles	2.83
P2 cycles	3.50
P3 cycles	3.50
P4 cycles	2.67
P5 cycles	2.67
P6 cycles	6.25
P7 cycles	6.25
P8 cycles	6.25
P9 cycles	6.25
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	8.00
P13 cycles	8.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	32
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	61.00
Nb uops	67.00
Nb loads	18.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.50
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.50
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	1.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.50
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:30-31
Module	attention-clang-znver5-512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:30-31.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 32.00 to 2.26 cycles (14.14x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 8 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 7 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSS2SD (FP32 to FP64, scalar): 16 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 80 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	61
nb uops	67
loop length	315
used x86 registers	15
used mmx registers	0
used xmm registers	17
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.38 cycles
front end	8.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.83	2.83	3.50	3.50	2.67	2.67	6.25	6.25	6.25	6.25	4.00	4.00	8.00	8.00	0.00	0.00
cycles	2.83	2.83	3.50	3.50	2.67	2.67	6.25	6.25	6.25	6.25	4.00	4.00	8.00	8.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	32.00

Cycles summary

Front-end	8.38
Dispatch	8.00
Data deps.	32.00
Overall L1	32.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.00 cycles. At this rate:

0% of peak load performance is reached (2.50 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 6150

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
LEA (%RCX,%R9,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R11,4),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
MOV %R10D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVSS (%R13,%R11,4),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x1(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VMOVSS (%R14,%R11,4),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RBX,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x6(%RCX,%R9,1),%EBX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VMOVSS (%R13,%R11,4),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x2(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VMOVSS (%R14,%RBX,4),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
MOV 0x38(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSS (%R14,%R11,4),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RSI,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R13,%R11,4),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x3(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VCVTSS2SD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R14,%R11,4),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RDX,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R13,%R11,4),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x4(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VFMADD213SD %XMM0,%XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM3,%XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R14,%R11,4),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%R15,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R13,%R11,4),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x5(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VCVTSS2SD %XMM4,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R14,%R11,4),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%R8,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R13,%R11,4),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%R12,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R13,%R11,4),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x7(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
ADD $0x8,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD %XMM2,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM5,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R14,%R11,4),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RDI,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RAX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R13,%R11,4),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
VCVTSS2SD %XMM6,%XMM6,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM7,%XMM7,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM8,%XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM2,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM9,%XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM10,%XMM10,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM11,%XMM11,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM12,%XMM12,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM2,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM13,%XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM14,%XMM14,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM15,%XMM15,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM16,%XMM16,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM2,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
CMP %R9,0x380(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JNE 6150 <main+0x27a0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:30-31
Module	attention-clang-znver5-512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:30-31.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 8 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 7 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSS2SD (FP32 to FP64, scalar): 16 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 80 bytes (10 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	61
nb uops	67
loop length	315
used x86 registers	15
used mmx registers	0
used xmm registers	17
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.38 cycles
front end	8.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.83	2.83	3.50	3.50	2.67	2.67	6.25	6.25	6.25	6.25	4.00	4.00	8.00	8.00	0.00	0.00
cycles	2.83	2.83	3.50	3.50	2.67	2.67	6.25	6.25	6.25	6.25	4.00	4.00	8.00	8.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	32.00

Cycles summary

Front-end	8.38
Dispatch	8.00
Data deps.	32.00
Overall L1	32.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.00 cycles. At this rate:

0% of peak load performance is reached (2.50 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 6150

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
LEA (%RCX,%R9,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R11,4),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
MOV %R10D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVSS (%R13,%R11,4),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x1(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VMOVSS (%R14,%R11,4),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RBX,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x6(%RCX,%R9,1),%EBX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VMOVSS (%R13,%R11,4),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x2(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VMOVSS (%R14,%RBX,4),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
MOV 0x38(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSS (%R14,%R11,4),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RSI,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R13,%R11,4),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x3(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VCVTSS2SD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R14,%R11,4),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RDX,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R13,%R11,4),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x4(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VFMADD213SD %XMM0,%XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM3,%XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R14,%R11,4),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%R15,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R13,%R11,4),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x5(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VCVTSS2SD %XMM4,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R14,%R11,4),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%R8,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R13,%R11,4),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%R12,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R13,%R11,4),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x7(%RCX,%R9,1),%R11D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
ADD $0x8,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VFMADD213SD %XMM2,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM5,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R14,%R11,4),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RDI,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RAX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R13,%R11,4),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
VCVTSS2SD %XMM6,%XMM6,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM7,%XMM7,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM8,%XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM2,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM9,%XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM10,%XMM10,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM11,%XMM11,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM12,%XMM12,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM2,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM13,%XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM14,%XMM14,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM15,%XMM15,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM16,%XMM16,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM2,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
CMP %R9,0x380(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
JNE 6150 <main+0x27a0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code