OV - attention-clang-znver5-512 - Loop 41 - attention-clang-znver5-512

	Loop Id: 41	Module: attention-clang-znver5-512	Source: random.tcc:330-336 [...]	Coverage: 0.11%

0x4480 MOV	%RCX,%RDX

0x4483 SHR	$0x1e,%RDX

0x4487 XOR	%RCX,%RDX

0x448a IMUL	$0x6c078965,%RDX,%RCX

0x4491 LEA	-0x6(%RAX,%RCX,1),%RCX

0x4496 MOV	%ECX,%EDX

0x4498 MOV	%RDX,0x608(%RSP,%RAX,8)    [1]

0x44a0 MOV	%ECX,%EDX

0x44a2 SHR	$0x1e,%EDX

0x44a5 XOR	%RCX,%RDX

0x44a8 IMUL	$0x6c078965,%RDX,%RCX

0x44af LEA	-0x5(%RAX,%RCX,1),%RCX

0x44b4 MOV	%ECX,%EDX

0x44b6 MOV	%RDX,0x610(%RSP,%RAX,8)    [1]

0x44be MOV	%ECX,%EDX

0x44c0 SHR	$0x1e,%EDX

0x44c3 XOR	%RCX,%RDX

0x44c6 IMUL	$0x6c078965,%RDX,%RCX

0x44cd LEA	-0x4(%RAX,%RCX,1),%RCX

0x44d2 MOV	%ECX,%EDX

0x44d4 MOV	%RDX,0x618(%RSP,%RAX,8)    [1]

0x44dc MOV	%ECX,%EDX

0x44de SHR	$0x1e,%EDX

0x44e1 XOR	%RCX,%RDX

0x44e4 IMUL	$0x6c078965,%RDX,%RCX

0x44eb LEA	-0x3(%RAX,%RCX,1),%RCX

0x44f0 MOV	%ECX,%EDX

0x44f2 MOV	%RDX,0x620(%RSP,%RAX,8)    [1]

0x44fa MOV	%ECX,%EDX

0x44fc SHR	$0x1e,%EDX

0x44ff XOR	%RCX,%RDX

0x4502 IMUL	$0x6c078965,%RDX,%RCX

0x4509 LEA	-0x2(%RAX,%RCX,1),%RCX

0x450e MOV	%ECX,%EDX

0x4510 MOV	%RDX,0x628(%RSP,%RAX,8)    [1]

0x4518 MOV	%ECX,%EDX

0x451a SHR	$0x1e,%EDX

0x451d XOR	%RCX,%RDX

0x4520 IMUL	$0x6c078965,%RDX,%RCX

0x4527 LEA	-0x1(%RAX,%RCX,1),%RCX

0x452c MOV	%ECX,%EDI

0x452e SHR	$0x1e,%EDI

0x4531 MOV	%ECX,%EDX

0x4533 MOV	%RDX,0x630(%RSP,%RAX,8)    [1]

0x453b XOR	%ECX,%EDI

0x453d IMUL	$0x6c078965,%EDI,%ECX

0x4543 ADD	%EAX,%ECX

0x4545 MOV	%RCX,0x638(%RSP,%RAX,8)    [1]

0x454d ADD	$0x7,%RAX

0x4551 CMP	$0x276,%RAX

0x4557 JNE	4480

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.h: 140 - 140

--------------------------------------------------------------------------------

140: 	    __res %= __m;

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 330 - 336

--------------------------------------------------------------------------------

330:       for (size_t __i = 1; __i < state_size; ++__i)

331: 	{

332: 	  _UIntType __x = _M_x[__i - 1];

333: 	  __x ^= __x >> (__w - 2);

334: 	  __x *= __f;

335: 	  __x += __detail::__mod<_UIntType, __n>(__i);

336: 	  _M_x[__i] = __detail::__mod<_UIntType,

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.83
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.40
Bottlenecks	micro-operation queue,
Function	main
Source	random.h:140-140,random.tcc:330-336
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	7.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	0.51
Front-end cycles	7.00
P0 cycles	5.00
P1 cycles	5.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	5.00
P5 cycles	5.00
P6 cycles	3.25
P7 cycles	3.25
P8 cycles	3.25
P9 cycles	3.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	56.00
Nb loads	0.00
Nb stores	7.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	56.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.01
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.10

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.83
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.40
Bottlenecks	micro-operation queue,
Function	main
Source	random.h:140-140,random.tcc:330-336
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	7.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	0.51
Front-end cycles	7.00
P0 cycles	5.00
P1 cycles	5.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	5.00
P5 cycles	5.00
P6 cycles	3.25
P7 cycles	3.25
P8 cycles	3.25
P9 cycles	3.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	56.00
Nb loads	0.00
Nb stores	7.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	56.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.01
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.10

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:330-336
Module	attention-clang-znver5-512

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.h:140
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:330-336

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 7.00 to 0.51 cycles (13.83x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 6 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.h:140
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.h:140
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.h:140
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.h:140
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.h:140
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.h:140

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 56 bytes.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	51
nb uops	56
loop length	221
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.00	5.00	5.00	5.00	5.00	5.00	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.00	5.00	5.00	5.00	5.00	5.00	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	7.00
Dispatch	5.00
Data deps.	0.00
Overall L1	7.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

6% of peak store performance is reached (8.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.00 to 5.00 cycles (1.40x speedup).

ASM code

In the binary file, the address of the loop is: 4480

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
SHR $0x1e,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
XOR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA -0x6(%RAX,%RCX,1),%RCX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
MOV %RDX,0x608(%RSP,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
SHR $0x1e,%EDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
XOR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA -0x5(%RAX,%RCX,1),%RCX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
MOV %RDX,0x610(%RSP,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
SHR $0x1e,%EDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
XOR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA -0x4(%RAX,%RCX,1),%RCX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
MOV %RDX,0x618(%RSP,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
SHR $0x1e,%EDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
XOR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA -0x3(%RAX,%RCX,1),%RCX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
MOV %RDX,0x620(%RSP,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
SHR $0x1e,%EDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
XOR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA -0x2(%RAX,%RCX,1),%RCX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
MOV %RDX,0x628(%RSP,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
SHR $0x1e,%EDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
XOR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA -0x1(%RAX,%RCX,1),%RCX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
MOV %ECX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
SHR $0x1e,%EDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
MOV %RDX,0x630(%RSP,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
XOR %ECX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
IMUL $0x6c078965,%EDI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RCX,0x638(%RSP,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
ADD $0x7,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP $0x276,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JNE 4480 <main+0xad0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-0.50	N/A

Function	main
Source file and lines	random.tcc:330-336
Module	attention-clang-znver5-512

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.h:140
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:330-336

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 6 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.h:140
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.h:140
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.h:140
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.h:140
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.h:140
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.h:140

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 56 bytes.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	51
nb uops	56
loop length	221
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.00	5.00	5.00	5.00	5.00	5.00	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.00	5.00	5.00	5.00	5.00	5.00	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	7.00
Dispatch	5.00
Data deps.	0.00
Overall L1	7.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

6% of peak store performance is reached (8.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4480

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
SHR $0x1e,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
XOR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA -0x6(%RAX,%RCX,1),%RCX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
MOV %RDX,0x608(%RSP,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
SHR $0x1e,%EDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
XOR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA -0x5(%RAX,%RCX,1),%RCX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
MOV %RDX,0x610(%RSP,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
SHR $0x1e,%EDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
XOR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA -0x4(%RAX,%RCX,1),%RCX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
MOV %RDX,0x618(%RSP,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
SHR $0x1e,%EDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
XOR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA -0x3(%RAX,%RCX,1),%RCX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
MOV %RDX,0x620(%RSP,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
SHR $0x1e,%EDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
XOR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA -0x2(%RAX,%RCX,1),%RCX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
MOV %RDX,0x628(%RSP,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
SHR $0x1e,%EDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
XOR %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA -0x1(%RAX,%RCX,1),%RCX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
MOV %ECX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
SHR $0x1e,%EDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (6.3%)
MOV %RDX,0x630(%RSP,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
XOR %ECX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
IMUL $0x6c078965,%EDI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EAX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RCX,0x638(%RSP,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
ADD $0x7,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP $0x276,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JNE 4480 <main+0xad0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0.33-0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code