OV - attention-clang-znver5-512 - Loop 106 - attention-clang-znver5-512

	Loop Id: 106	Module: attention-clang-znver5-512	Source: random.tcc:412-414	Coverage: 0.06%

0x48c0 VMOVDQU	0x5e8(%RSP,%RDX,8),%XMM3    [1]

0x48c9 VMOVDQU	0x5f8(%RSP,%RDX,8),%XMM4    [1]

0x48d2 VMOVDQU	0x608(%RSP,%RDX,8),%XMM5    [1]

0x48db VMOVDQU	0x618(%RSP,%RDX,8),%XMM6    [1]

0x48e4 VPALIGNR	$0x8,%XMM2,%XMM3,%XMM2

0x48ea VPAND	%XMM3,%XMM9,%XMM7

0x48ee VPTESTMQ	%XMM10,%XMM3,%K1

0x48f4 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM7

0x48fb VPSRLQ	$0x1,%XMM7,%XMM2

0x4900 VPXOR	-0x138(%RSP,%RDX,8),%XMM2,%XMM2    [1]

0x4909 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

0x490f VPTESTMQ	%XMM10,%XMM4,%K1

0x4915 VMOVDQU	%XMM2,0x5e0(%RSP,%RDX,8)    [1]

0x491e VPALIGNR	$0x8,%XMM3,%XMM4,%XMM2

0x4924 VPAND	%XMM4,%XMM9,%XMM3

0x4928 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

0x492f VPSRLQ	$0x1,%XMM3,%XMM2

0x4934 VPXOR	-0x128(%RSP,%RDX,8),%XMM2,%XMM2    [1]

0x493d VPAND	%XMM5,%XMM9,%XMM3

0x4941 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

0x4947 VPTESTMQ	%XMM10,%XMM5,%K1

0x494d VMOVDQU	%XMM2,0x5f0(%RSP,%RDX,8)    [1]

0x4956 VPALIGNR	$0x8,%XMM4,%XMM5,%XMM2

0x495c VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

0x4963 VPSRLQ	$0x1,%XMM3,%XMM2

0x4968 VPXOR	-0x118(%RSP,%RDX,8),%XMM2,%XMM2    [1]

0x4971 VPAND	%XMM6,%XMM9,%XMM3

0x4975 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

0x497b VPTESTMQ	%XMM10,%XMM6,%K1

0x4981 VMOVDQU	%XMM2,0x600(%RSP,%RDX,8)    [1]

0x498a VPALIGNR	$0x8,%XMM5,%XMM6,%XMM2

0x4990 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

0x4997 VPSRLQ	$0x1,%XMM3,%XMM2

0x499c VPXOR	-0x108(%RSP,%RDX,8),%XMM2,%XMM2    [1]

0x49a5 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

0x49ab VMOVDQU	%XMM2,0x610(%RSP,%RDX,8)    [1]

0x49b4 VMOVDQU	0x628(%RSP,%RDX,8),%XMM3    [1]

0x49bd VPALIGNR	$0x8,%XMM6,%XMM3,%XMM2

0x49c3 VPAND	%XMM3,%XMM9,%XMM4

0x49c7 VPTESTMQ	%XMM10,%XMM3,%K1

0x49cd VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM4

0x49d4 VPSRLQ	$0x1,%XMM4,%XMM2

0x49d9 VPXOR	-0xf8(%RSP,%RDX,8),%XMM2,%XMM2    [1]

0x49e2 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

0x49e8 VMOVDQU	%XMM2,0x620(%RSP,%RDX,8)    [1]

0x49f1 VMOVDQU	0x638(%RSP,%RDX,8),%XMM2    [1]

0x49fa VPALIGNR	$0x8,%XMM3,%XMM2,%XMM3

0x4a00 VPAND	%XMM2,%XMM9,%XMM4

0x4a04 VPTESTMQ	%XMM10,%XMM2,%K1

0x4a0a VPTERNLOGQ	$-0x8,%XMM8,%XMM3,%XMM4

0x4a11 VPSRLQ	$0x1,%XMM4,%XMM3

0x4a16 VPXOR	-0xe8(%RSP,%RDX,8),%XMM3,%XMM3    [1]

0x4a1f VPXORQ	%XMM11,%XMM3,%XMM3{%K1}

0x4a25 VMOVDQU	%XMM3,0x630(%RSP,%RDX,8)    [1]

0x4a2e ADD	$0xc,%RDX

0x4a32 CMP	$0x27a,%RDX

0x4a39 JNE	48c0

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 412 - 414

--------------------------------------------------------------------------------

412: 			   | (_M_x[__k + 1] & __lower_mask));

413: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

414: 		       ^ ((__y & 0x01) ? __a : 0));

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P10, P11, P12, P13,
Function	main
Source	random.tcc:412-414
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.50
CQA cycles if no scalar integer	10.50
CQA cycles if FP arith vectorized	10.50
CQA cycles if fully vectorized	2.25
Front-end cycles	7.00
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	4.50
P7 cycles	4.50
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	10.50
P11 cycles	10.50
P12 cycles	10.50
P13 cycles	10.50
P14 cycles	3.00
P15 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	57.00
Nb uops	56.00
Nb loads	12.00
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.43
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	96.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	88.89
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	85.71
Vector-efficiency ratio all	23.61
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.21

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P10, P11, P12, P13,
Function	main
Source	random.tcc:412-414
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.50
CQA cycles if no scalar integer	10.50
CQA cycles if FP arith vectorized	10.50
CQA cycles if fully vectorized	2.25
Front-end cycles	7.00
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	4.50
P7 cycles	4.50
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	10.50
P11 cycles	10.50
P12 cycles	10.50
P13 cycles	10.50
P14 cycles	3.00
P15 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	57.00
Nb uops	56.00
Nb loads	12.00
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.43
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	96.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	88.89
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	85.71
Vector-efficiency ratio all	23.61
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.21

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:412-414
Module	attention-clang-znver5-512

The loop is defined in /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:412-414.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 23% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 10.50 to 2.25 cycles (4.67x speedup).

Details

88% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

85% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 192 bytes. The binary loop is storing 96 bytes.

General properties

nb instructions	57
nb uops	56
loop length	383
used x86 registers	2
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	4.50	4.50	4.50	4.50	10.50	10.50	10.50	10.50	3.00	3.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	4.50	4.50	4.50	4.50	10.50	10.50	10.50	10.50	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.00
Dispatch	10.50
Data deps.	1.00
Overall L1	10.50

Vectorization ratios

all	88%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

Vector efficiency ratios

all	23%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.50 cycles. At this rate:

7% of peak load performance is reached (18.29 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.14 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 48c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVDQU 0x5e8(%RSP,%RDX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVDQU 0x5f8(%RSP,%RDX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVDQU 0x608(%RSP,%RDX,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVDQU 0x618(%RSP,%RDX,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPALIGNR $0x8,%XMM2,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
VPAND %XMM3,%XMM9,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPTESTMQ %XMM10,%XMM3,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM8,%XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPSRLQ $0x1,%XMM7,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1-2	0.50	vect (25.0%)
VPXOR -0x138(%RSP,%RDX,8),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
VPXORQ %XMM11,%XMM2,%XMM2{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPTESTMQ %XMM10,%XMM4,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVDQU %XMM2,0x5e0(%RSP,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPALIGNR $0x8,%XMM3,%XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
VPAND %XMM4,%XMM9,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM8,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPSRLQ $0x1,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1-2	0.50	vect (25.0%)
VPXOR -0x128(%RSP,%RDX,8),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
VPAND %XMM5,%XMM9,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPXORQ %XMM11,%XMM2,%XMM2{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPTESTMQ %XMM10,%XMM5,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVDQU %XMM2,0x5f0(%RSP,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPALIGNR $0x8,%XMM4,%XMM5,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
VPTERNLOGQ $-0x8,%XMM8,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPSRLQ $0x1,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1-2	0.50	vect (25.0%)
VPXOR -0x118(%RSP,%RDX,8),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
VPAND %XMM6,%XMM9,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPXORQ %XMM11,%XMM2,%XMM2{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPTESTMQ %XMM10,%XMM6,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVDQU %XMM2,0x600(%RSP,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPALIGNR $0x8,%XMM5,%XMM6,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
VPTERNLOGQ $-0x8,%XMM8,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPSRLQ $0x1,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1-2	0.50	vect (25.0%)
VPXOR -0x108(%RSP,%RDX,8),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
VPXORQ %XMM11,%XMM2,%XMM2{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VMOVDQU %XMM2,0x610(%RSP,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVDQU 0x628(%RSP,%RDX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPALIGNR $0x8,%XMM6,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
VPAND %XMM3,%XMM9,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPTESTMQ %XMM10,%XMM3,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM8,%XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPSRLQ $0x1,%XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1-2	0.50	vect (25.0%)
VPXOR -0xf8(%RSP,%RDX,8),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
VPXORQ %XMM11,%XMM2,%XMM2{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VMOVDQU %XMM2,0x620(%RSP,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVDQU 0x638(%RSP,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPALIGNR $0x8,%XMM3,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
VPAND %XMM2,%XMM9,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPTESTMQ %XMM10,%XMM2,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM8,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPSRLQ $0x1,%XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1-2	0.50	vect (25.0%)
VPXOR -0xe8(%RSP,%RDX,8),%XMM3,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
VPXORQ %XMM11,%XMM3,%XMM3{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VMOVDQU %XMM3,0x630(%RSP,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
ADD $0xc,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x27a,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 48c0 <main+0xf10>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A

Function	main
Source file and lines	random.tcc:412-414
Module	attention-clang-znver5-512

The loop is defined in /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:412-414.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Details

88% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

85% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 192 bytes. The binary loop is storing 96 bytes.

General properties

nb instructions	57
nb uops	56
loop length	383
used x86 registers	2
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	4.50	4.50	4.50	4.50	10.50	10.50	10.50	10.50	3.00	3.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	4.50	4.50	4.50	4.50	10.50	10.50	10.50	10.50	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.00
Dispatch	10.50
Data deps.	1.00
Overall L1	10.50

Vectorization ratios

all	88%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

Vector efficiency ratios

all	23%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.50 cycles. At this rate:

7% of peak load performance is reached (18.29 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.14 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 48c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVDQU 0x5e8(%RSP,%RDX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVDQU 0x5f8(%RSP,%RDX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVDQU 0x608(%RSP,%RDX,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVDQU 0x618(%RSP,%RDX,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPALIGNR $0x8,%XMM2,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
VPAND %XMM3,%XMM9,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPTESTMQ %XMM10,%XMM3,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM8,%XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPSRLQ $0x1,%XMM7,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1-2	0.50	vect (25.0%)
VPXOR -0x138(%RSP,%RDX,8),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
VPXORQ %XMM11,%XMM2,%XMM2{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPTESTMQ %XMM10,%XMM4,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVDQU %XMM2,0x5e0(%RSP,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPALIGNR $0x8,%XMM3,%XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
VPAND %XMM4,%XMM9,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM8,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPSRLQ $0x1,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1-2	0.50	vect (25.0%)
VPXOR -0x128(%RSP,%RDX,8),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
VPAND %XMM5,%XMM9,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPXORQ %XMM11,%XMM2,%XMM2{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPTESTMQ %XMM10,%XMM5,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVDQU %XMM2,0x5f0(%RSP,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPALIGNR $0x8,%XMM4,%XMM5,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
VPTERNLOGQ $-0x8,%XMM8,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPSRLQ $0x1,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1-2	0.50	vect (25.0%)
VPXOR -0x118(%RSP,%RDX,8),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
VPAND %XMM6,%XMM9,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPXORQ %XMM11,%XMM2,%XMM2{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPTESTMQ %XMM10,%XMM6,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVDQU %XMM2,0x600(%RSP,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPALIGNR $0x8,%XMM5,%XMM6,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
VPTERNLOGQ $-0x8,%XMM8,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPSRLQ $0x1,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1-2	0.50	vect (25.0%)
VPXOR -0x108(%RSP,%RDX,8),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
VPXORQ %XMM11,%XMM2,%XMM2{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VMOVDQU %XMM2,0x610(%RSP,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVDQU 0x628(%RSP,%RDX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPALIGNR $0x8,%XMM6,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
VPAND %XMM3,%XMM9,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPTESTMQ %XMM10,%XMM3,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM8,%XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPSRLQ $0x1,%XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1-2	0.50	vect (25.0%)
VPXOR -0xf8(%RSP,%RDX,8),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
VPXORQ %XMM11,%XMM2,%XMM2{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VMOVDQU %XMM2,0x620(%RSP,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVDQU 0x638(%RSP,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPALIGNR $0x8,%XMM3,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	scal (12.5%)
VPAND %XMM2,%XMM9,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPTESTMQ %XMM10,%XMM2,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM8,%XMM3,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VPSRLQ $0x1,%XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1-2	0.50	vect (25.0%)
VPXOR -0xe8(%RSP,%RDX,8),%XMM3,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1-2	0.50	vect (25.0%)
VPXORQ %XMM11,%XMM3,%XMM3{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VMOVDQU %XMM3,0x630(%RSP,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
ADD $0xc,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x27a,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 48c0 <main+0xf10>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code