| Loop Id: 103 | Module: attention-clang-znver5-512 | Source: attention_v2.cpp:163-164 [...] | Coverage: 0.11% |
|---|
| Loop Id: 103 | Module: attention-clang-znver5-512 | Source: attention_v2.cpp:163-164 [...] | Coverage: 0.11% |
|---|
0x45f0 VMOVSS 0x4a1c(%RIP),%XMM1 |
0x45f8 VXORPS %XMM0,%XMM0,%XMM0 |
0x45fc MOV %RAX,%RCX |
0x45ff JMP 4675 |
(104) 0x4610 MOV %R13,%RDX |
(104) 0x4613 INC %R13 |
(104) 0x4616 MOV $0x200b,%ESI |
(104) 0x461b MOV %R13,0x19b8(%RSP) |
(104) 0x4623 MOV 0x638(%RSP,%RDX,8),%RDX |
(104) 0x462b BEXTR %RSI,%RDX,%RSI |
(104) 0x4630 XOR %RDX,%RSI |
(104) 0x4633 MOV %ESI,%EDX |
(104) 0x4635 SAL $0x7,%EDX |
(104) 0x4638 AND $-0x62d3a980,%EDX |
(104) 0x463e XOR %RSI,%RDX |
(104) 0x4641 MOV %EDX,%ESI |
(104) 0x4643 SAL $0xf,%ESI |
(104) 0x4646 AND $-0x103a0000,%ESI |
(104) 0x464c XOR %RDX,%RSI |
(104) 0x464f MOV %RSI,%RDX |
(104) 0x4652 SHR $0x12,%RDX |
(104) 0x4656 XOR %RSI,%RDX |
(104) 0x4659 DEC %RCX |
(104) 0x465c VCVTUSI2SS %RDX,%XMM15,%XMM2 |
(104) 0x4662 VFMADD231SS %XMM2,%XMM1,%XMM0 |
(104) 0x4667 VMULSS 0x4999(%RIP),%XMM1,%XMM1 |
(104) 0x466f JE 4a90 |
(104) 0x4675 CMP $0x270,%R13 |
(104) 0x467c JB 4610 |
(104) 0x467e VPBROADCASTQ 0x49b8(%RIP),%ZMM14 |
(104) 0x4688 VPBROADCASTQ 0x49b6(%RIP),%ZMM15 |
(104) 0x4692 VPBROADCASTQ 0x49b4(%RIP),%ZMM16 |
(104) 0x469c VPBROADCASTQ 0x49b2(%RIP),%ZMM17 |
(104) 0x46a6 VPBROADCASTQ %RBX,%ZMM2 |
(104) 0x46ac XOR %EDX,%EDX |
(104) 0x46ae XCHG %AX,%AX |
(105) 0x46b0 VMOVDQU64 0x640(%RSP,%RDX,8),%ZMM3 |
(105) 0x46b8 VMOVDQU64 0x680(%RSP,%RDX,8),%ZMM4 |
(105) 0x46c0 VMOVDQU64 0x6c0(%RSP,%RDX,8),%ZMM5 |
(105) 0x46c8 VALIGNQ $0x7,%ZMM2,%ZMM3,%ZMM6 |
(105) 0x46cf VMOVDQU64 0x700(%RSP,%RDX,8),%ZMM2 |
(105) 0x46d7 VALIGNQ $0x7,%ZMM3,%ZMM4,%ZMM7 |
(105) 0x46de VALIGNQ $0x7,%ZMM4,%ZMM5,%ZMM8 |
(105) 0x46e5 VPANDQ %ZMM15,%ZMM3,%ZMM10 |
(105) 0x46eb VPANDQ %ZMM15,%ZMM4,%ZMM11 |
(105) 0x46f1 VPANDQ %ZMM15,%ZMM5,%ZMM12 |
(105) 0x46f7 VPTESTMQ %ZMM16,%ZMM3,%K1 |
(105) 0x46fd VPTESTMQ %ZMM16,%ZMM4,%K2 |
(105) 0x4703 VPTESTMQ %ZMM16,%ZMM5,%K3 |
(105) 0x4709 VPTERNLOGQ $-0x8,%ZMM14,%ZMM6,%ZMM10 |
(105) 0x4710 VPTERNLOGQ $-0x8,%ZMM14,%ZMM7,%ZMM11 |
(105) 0x4717 VPTERNLOGQ $-0x8,%ZMM14,%ZMM8,%ZMM12 |
(105) 0x471e VPSRLQ $0x1,%ZMM10,%ZMM6 |
(105) 0x4725 VPSRLQ $0x1,%ZMM11,%ZMM7 |
(105) 0x472c VPSRLQ $0x1,%ZMM12,%ZMM8 |
(105) 0x4733 VPXORQ 0x12a0(%RSP,%RDX,8),%ZMM6,%ZMM6 |
(105) 0x473e VPXORQ 0x12e0(%RSP,%RDX,8),%ZMM7,%ZMM7 |
(105) 0x4749 VPXORQ 0x1320(%RSP,%RDX,8),%ZMM8,%ZMM8 |
(105) 0x4754 VALIGNQ $0x7,%ZMM5,%ZMM2,%ZMM9 |
(105) 0x475b VPANDQ %ZMM15,%ZMM2,%ZMM13 |
(105) 0x4761 VPTESTMQ %ZMM16,%ZMM2,%K4 |
(105) 0x4767 VPTERNLOGQ $-0x8,%ZMM14,%ZMM9,%ZMM13 |
(105) 0x476e VPSRLQ $0x1,%ZMM13,%ZMM9 |
(105) 0x4775 VPXORQ 0x1360(%RSP,%RDX,8),%ZMM9,%ZMM9 |
(105) 0x4780 VPXORQ %ZMM17,%ZMM6,%ZMM6{%K1} |
(105) 0x4786 VPXORQ %ZMM17,%ZMM7,%ZMM7{%K2} |
(105) 0x478c VPXORQ %ZMM17,%ZMM8,%ZMM8{%K3} |
(105) 0x4792 VMOVDQU64 %ZMM6,0x638(%RSP,%RDX,8) |
(105) 0x479d VMOVDQU64 %ZMM7,0x678(%RSP,%RDX,8) |
(105) 0x47a8 VMOVDQU64 %ZMM8,0x6b8(%RSP,%RDX,8) |
(105) 0x47b3 VPXORQ %ZMM17,%ZMM9,%ZMM9{%K4} |
(105) 0x47b9 VMOVDQU64 %ZMM9,0x6f8(%RSP,%RDX,8) |
(105) 0x47c4 ADD $0x20,%RDX |
(105) 0x47c8 CMP $0xe0,%RDX |
(105) 0x47cf JNE 46b0 |
(104) 0x47d5 MOV 0xd40(%RSP),%RSI |
(104) 0x47dd VEXTRACTI32X4 $0x3,%ZMM2,%XMM2 |
(104) 0x47e4 MOV 0xd48(%RSP),%RDX |
(104) 0x47ec VPBROADCASTQ 0x484b(%RIP),%XMM8 |
(104) 0x47f5 VPBROADCASTQ 0x484a(%RIP),%XMM9 |
(104) 0x47fe VPBROADCASTQ 0x4849(%RIP),%XMM10 |
(104) 0x4807 VPBROADCASTQ 0x4848(%RIP),%XMM11 |
(104) 0x4810 VPEXTRQ $0x1,%XMM2,%RDI |
(104) 0x4816 AND $-0x80000000,%RDI |
(104) 0x481d MOV %ESI,%R8D |
(104) 0x4820 AND $0x7ffffffe,%R8D |
(104) 0x4827 OR %RDI,%R8 |
(104) 0x482a MOV %ESI,%EDI |
(104) 0x482c AND $0x1,%EDI |
(104) 0x482f AND $-0x80000000,%RSI |
(104) 0x4836 SHR $0x1,%R8 |
(104) 0x4839 XOR 0x19a0(%RSP),%R8 |
(104) 0x4841 NEG %EDI |
(104) 0x4843 AND %R12D,%EDI |
(104) 0x4846 XOR %R8,%RDI |
(104) 0x4849 MOV %RDI,0xd38(%RSP) |
(104) 0x4851 MOV %EDX,%EDI |
(104) 0x4853 AND $0x7ffffffe,%EDI |
(104) 0x4859 OR %RSI,%RDI |
(104) 0x485c MOV %EDX,%ESI |
(104) 0x485e AND $0x1,%ESI |
(104) 0x4861 AND $-0x80000000,%RDX |
(104) 0x4868 SHR $0x1,%RDI |
(104) 0x486b XOR 0x19a8(%RSP),%RDI |
(104) 0x4873 NEG %ESI |
(104) 0x4875 AND %R12D,%ESI |
(104) 0x4878 XOR %RDI,%RSI |
(104) 0x487b MOV %RSI,0xd40(%RSP) |
(104) 0x4883 MOV 0xd50(%RSP),%RSI |
(104) 0x488b MOV %ESI,%EDI |
(104) 0x488d VPBROADCASTQ %RSI,%XMM2 |
(104) 0x4893 AND $0x7ffffffe,%ESI |
(104) 0x4899 AND $0x1,%EDI |
(104) 0x489c OR %RDX,%RSI |
(104) 0x489f NEG %EDI |
(104) 0x48a1 MOV $0xee,%EDX |
(104) 0x48a6 SHR $0x1,%RSI |
(104) 0x48a9 XOR 0x19b0(%RSP),%RSI |
(104) 0x48b1 AND %R12D,%EDI |
(104) 0x48b4 XOR %RSI,%RDI |
(104) 0x48b7 MOV %RDI,0xd48(%RSP) |
(104) 0x48bf NOP |
(106) 0x48c0 VMOVDQU 0x5e8(%RSP,%RDX,8),%XMM3 |
(106) 0x48c9 VMOVDQU 0x5f8(%RSP,%RDX,8),%XMM4 |
(106) 0x48d2 VMOVDQU 0x608(%RSP,%RDX,8),%XMM5 |
(106) 0x48db VMOVDQU 0x618(%RSP,%RDX,8),%XMM6 |
(106) 0x48e4 VPALIGNR $0x8,%XMM2,%XMM3,%XMM2 |
(106) 0x48ea VPAND %XMM3,%XMM9,%XMM7 |
(106) 0x48ee VPTESTMQ %XMM10,%XMM3,%K1 |
(106) 0x48f4 VPTERNLOGQ $-0x8,%XMM8,%XMM2,%XMM7 |
(106) 0x48fb VPSRLQ $0x1,%XMM7,%XMM2 |
(106) 0x4900 VPXOR -0x138(%RSP,%RDX,8),%XMM2,%XMM2 |
(106) 0x4909 VPXORQ %XMM11,%XMM2,%XMM2{%K1} |
(106) 0x490f VPTESTMQ %XMM10,%XMM4,%K1 |
(106) 0x4915 VMOVDQU %XMM2,0x5e0(%RSP,%RDX,8) |
(106) 0x491e VPALIGNR $0x8,%XMM3,%XMM4,%XMM2 |
(106) 0x4924 VPAND %XMM4,%XMM9,%XMM3 |
(106) 0x4928 VPTERNLOGQ $-0x8,%XMM8,%XMM2,%XMM3 |
(106) 0x492f VPSRLQ $0x1,%XMM3,%XMM2 |
(106) 0x4934 VPXOR -0x128(%RSP,%RDX,8),%XMM2,%XMM2 |
(106) 0x493d VPAND %XMM5,%XMM9,%XMM3 |
(106) 0x4941 VPXORQ %XMM11,%XMM2,%XMM2{%K1} |
(106) 0x4947 VPTESTMQ %XMM10,%XMM5,%K1 |
(106) 0x494d VMOVDQU %XMM2,0x5f0(%RSP,%RDX,8) |
(106) 0x4956 VPALIGNR $0x8,%XMM4,%XMM5,%XMM2 |
(106) 0x495c VPTERNLOGQ $-0x8,%XMM8,%XMM2,%XMM3 |
(106) 0x4963 VPSRLQ $0x1,%XMM3,%XMM2 |
(106) 0x4968 VPXOR -0x118(%RSP,%RDX,8),%XMM2,%XMM2 |
(106) 0x4971 VPAND %XMM6,%XMM9,%XMM3 |
(106) 0x4975 VPXORQ %XMM11,%XMM2,%XMM2{%K1} |
(106) 0x497b VPTESTMQ %XMM10,%XMM6,%K1 |
(106) 0x4981 VMOVDQU %XMM2,0x600(%RSP,%RDX,8) |
(106) 0x498a VPALIGNR $0x8,%XMM5,%XMM6,%XMM2 |
(106) 0x4990 VPTERNLOGQ $-0x8,%XMM8,%XMM2,%XMM3 |
(106) 0x4997 VPSRLQ $0x1,%XMM3,%XMM2 |
(106) 0x499c VPXOR -0x108(%RSP,%RDX,8),%XMM2,%XMM2 |
(106) 0x49a5 VPXORQ %XMM11,%XMM2,%XMM2{%K1} |
(106) 0x49ab VMOVDQU %XMM2,0x610(%RSP,%RDX,8) |
(106) 0x49b4 VMOVDQU 0x628(%RSP,%RDX,8),%XMM3 |
(106) 0x49bd VPALIGNR $0x8,%XMM6,%XMM3,%XMM2 |
(106) 0x49c3 VPAND %XMM3,%XMM9,%XMM4 |
(106) 0x49c7 VPTESTMQ %XMM10,%XMM3,%K1 |
(106) 0x49cd VPTERNLOGQ $-0x8,%XMM8,%XMM2,%XMM4 |
(106) 0x49d4 VPSRLQ $0x1,%XMM4,%XMM2 |
(106) 0x49d9 VPXOR -0xf8(%RSP,%RDX,8),%XMM2,%XMM2 |
(106) 0x49e2 VPXORQ %XMM11,%XMM2,%XMM2{%K1} |
(106) 0x49e8 VMOVDQU %XMM2,0x620(%RSP,%RDX,8) |
(106) 0x49f1 VMOVDQU 0x638(%RSP,%RDX,8),%XMM2 |
(106) 0x49fa VPALIGNR $0x8,%XMM3,%XMM2,%XMM3 |
(106) 0x4a00 VPAND %XMM2,%XMM9,%XMM4 |
(106) 0x4a04 VPTESTMQ %XMM10,%XMM2,%K1 |
(106) 0x4a0a VPTERNLOGQ $-0x8,%XMM8,%XMM3,%XMM4 |
(106) 0x4a11 VPSRLQ $0x1,%XMM4,%XMM3 |
(106) 0x4a16 VPXOR -0xe8(%RSP,%RDX,8),%XMM3,%XMM3 |
(106) 0x4a1f VPXORQ %XMM11,%XMM3,%XMM3{%K1} |
(106) 0x4a25 VMOVDQU %XMM3,0x630(%RSP,%RDX,8) |
(106) 0x4a2e ADD $0xc,%RDX |
(106) 0x4a32 CMP $0x27a,%RDX |
(106) 0x4a39 JNE 48c0 |
(104) 0x4a3f MOV 0x19b0(%RSP),%RDX |
(104) 0x4a47 MOV 0x638(%RSP),%RBX |
(104) 0x4a4f XOR %R13D,%R13D |
(104) 0x4a52 MOV %EBX,%ESI |
(104) 0x4a54 AND %R14,%RDX |
(104) 0x4a57 AND $0x7ffffffe,%ESI |
(104) 0x4a5d OR %RDX,%RSI |
(104) 0x4a60 MOV %EBX,%EDX |
(104) 0x4a62 AND $0x1,%EDX |
(104) 0x4a65 SHR $0x1,%RSI |
(104) 0x4a68 XOR 0x1298(%RSP),%RSI |
(104) 0x4a70 NEG %EDX |
(104) 0x4a72 AND %R12D,%EDX |
(104) 0x4a75 XOR %RSI,%RDX |
(104) 0x4a78 MOV %RDX,0x19b0(%RSP) |
(104) 0x4a80 JMP 4610 |
0x4a90 VDIVSS %XMM1,%XMM0,%XMM0 |
0x4a94 VUCOMISS 0x4578(%RIP),%XMM0 |
0x4a9c JAE 4abf |
0x4a9e MOV 0x70(%RSP),%RCX |
0x4aa3 VMOVSS %XMM0,(%RCX,%R9,4) |
0x4aa9 INC %R9 |
0x4aac CMP 0xb0(%RSP),%R9 |
0x4ab4 JNE 45f0 |
0x4abf VMOVSS 0x454d(%RIP),%XMM0 |
0x4ac7 VXORPS %XMM1,%XMM1,%XMM1 |
0x4acb MOV %RAX,0x2c0(%RSP) |
0x4ad3 MOV %R9,0x200(%RSP) |
0x4adb VZEROUPPER |
0x4ade CALL 10a0 <nextafterf@plt> |
0x4ae3 MOV 0x200(%RSP),%R9 |
0x4aeb MOV 0x2c0(%RSP),%RAX |
0x4af3 JMP 4a9e |
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath: 1661 - 1661 |
-------------------------------------------------------------------------------- |
1661: { return __builtin_nextafterf(__x, __y); } |
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 401 - 3370 |
-------------------------------------------------------------------------------- |
401: for (size_t __k = 0; __k < (__n - __m); ++__k) |
402: { |
403: _UIntType __y = ((_M_x[__k] & __upper_mask) |
404: | (_M_x[__k + 1] & __lower_mask)); |
405: _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1) |
406: ^ ((__y & 0x01) ? __a : 0)); |
407: } |
408: |
409: for (size_t __k = (__n - __m); __k < (__n - 1); ++__k) |
410: { |
411: _UIntType __y = ((_M_x[__k] & __upper_mask) |
412: | (_M_x[__k + 1] & __lower_mask)); |
413: _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1) |
414: ^ ((__y & 0x01) ? __a : 0)); |
415: } |
416: |
417: _UIntType __y = ((_M_x[__n - 1] & __upper_mask) |
418: | (_M_x[0] & __lower_mask)); |
419: _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1) |
420: ^ ((__y & 0x01) ? __a : 0)); |
[...] |
455: if (_M_p >= state_size) |
456: _M_gen_rand(); |
457: |
458: // Calculate o(x(i)). |
459: result_type __z = _M_x[_M_p++]; |
460: __z ^= (__z >> __u) & __d; |
461: __z ^= (__z << __s) & __b; |
462: __z ^= (__z << __t) & __c; |
463: __z ^= (__z >> __l); |
[...] |
3364: for (size_t __k = __m; __k != 0; --__k) |
3365: { |
3366: __sum += _RealType(__urng() - __urng.min()) * __tmp; |
3367: __tmp *= __r; |
3368: } |
3369: __ret = __sum / __tmp; |
3370: if (__builtin_expect(__ret >= _RealType(1), 0)) |
/home/eoseret/llm-attention/attention_v2.cpp: 163 - 164 |
-------------------------------------------------------------------------------- |
163: for (size_t i = 0; i < elemsX; ++i) h_X[i] = dist(rng); |
164: for (size_t i = 0; i < elemsW; ++i) { |
| Coverage (%) | Name | Source Location | Module |
|---|
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.07 |
| CQA speedup if FP arith vectorized | 1.92 |
| CQA speedup if fully vectorized | 13.88 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.34 |
| Bottlenecks | |
| Function | main |
| Source | cmath:1661-1661,random.tcc:3369-3370,attention_v2.cpp:163-164 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 2.69 |
| CQA cycles if no scalar integer | 2.50 |
| CQA cycles if FP arith vectorized | 1.40 |
| CQA cycles if fully vectorized | 0.19 |
| Front-end cycles | 2.19 |
| P0 cycles | 0.50 |
| P1 cycles | 0.50 |
| P2 cycles | 0.50 |
| P3 cycles | 1.17 |
| P4 cycles | 1.17 |
| P5 cycles | 1.17 |
| P6 cycles | 1.88 |
| P7 cycles | 1.88 |
| P8 cycles | 1.88 |
| P9 cycles | 1.88 |
| P10 cycles | 0.50 |
| P11 cycles | 0.50 |
| P12 cycles | 0.50 |
| P13 cycles | 0.50 |
| P14 cycles | 1.00 |
| P15 cycles | 1.00 |
| DIV/SQRT cycles | 2.50 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 16.50 |
| Nb uops | 17.50 |
| Nb loads | 5.50 |
| Nb stores | 2.00 |
| Nb stack references | 3.00 |
| FLOP/cycle | 0.37 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 1.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 16.73 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 34.00 |
| Bytes stored | 12.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 2.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 23.64 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 62.50 |
| Vector-efficiency ratio all | 11.53 |
| Vector-efficiency ratio load | 7.03 |
| Vector-efficiency ratio store | 8.33 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | 6.25 |
| Vector-efficiency ratio other | 17.97 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 2.50 |
| CQA speedup if fully vectorized | 16.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.67 |
| Bottlenecks | P10, P11, |
| Function | main |
| Source | cmath:1661-1661,random.tcc:3369-3370,attention_v2.cpp:163-164 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 2.50 |
| CQA cycles if no scalar integer | 2.50 |
| CQA cycles if FP arith vectorized | 1.00 |
| CQA cycles if fully vectorized | 0.16 |
| Front-end cycles | 1.50 |
| P0 cycles | 0.33 |
| P1 cycles | 0.33 |
| P2 cycles | 0.33 |
| P3 cycles | 1.00 |
| P4 cycles | 1.00 |
| P5 cycles | 1.00 |
| P6 cycles | 1.25 |
| P7 cycles | 1.25 |
| P8 cycles | 1.25 |
| P9 cycles | 1.25 |
| P10 cycles | 0.50 |
| P11 cycles | 0.50 |
| P12 cycles | 0.50 |
| P13 cycles | 0.50 |
| P14 cycles | 1.00 |
| P15 cycles | 1.00 |
| DIV/SQRT cycles | 2.50 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 12.00 |
| Nb uops | 12.00 |
| Nb loads | 4.00 |
| Nb stores | 1.00 |
| Nb stack references | 2.00 |
| FLOP/cycle | 0.40 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 1.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 11.20 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 24.00 |
| Bytes stored | 4.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 2.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 20.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 50.00 |
| Vector-efficiency ratio all | 10.00 |
| Vector-efficiency ratio load | 6.25 |
| Vector-efficiency ratio store | 6.25 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | 6.25 |
| Vector-efficiency ratio other | 15.63 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.15 |
| CQA speedup if FP arith vectorized | 1.60 |
| CQA speedup if fully vectorized | 12.44 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.15 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | cmath:1661-1661,random.tcc:3369-3370,attention_v2.cpp:163-164 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 2.88 |
| CQA cycles if no scalar integer | 2.50 |
| CQA cycles if FP arith vectorized | 1.80 |
| CQA cycles if fully vectorized | 0.23 |
| Front-end cycles | 2.88 |
| P0 cycles | 0.67 |
| P1 cycles | 0.67 |
| P2 cycles | 0.67 |
| P3 cycles | 1.33 |
| P4 cycles | 1.33 |
| P5 cycles | 1.33 |
| P6 cycles | 2.50 |
| P7 cycles | 2.50 |
| P8 cycles | 2.50 |
| P9 cycles | 2.50 |
| P10 cycles | 0.50 |
| P11 cycles | 0.50 |
| P12 cycles | 0.50 |
| P13 cycles | 0.50 |
| P14 cycles | 1.00 |
| P15 cycles | 1.00 |
| DIV/SQRT cycles | 2.50 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 21.00 |
| Nb uops | 23.00 |
| Nb loads | 7.00 |
| Nb stores | 3.00 |
| Nb stack references | 4.00 |
| FLOP/cycle | 0.35 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 1.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 22.26 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 44.00 |
| Bytes stored | 20.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 2.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 27.27 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 75.00 |
| Vector-efficiency ratio all | 13.07 |
| Vector-efficiency ratio load | 7.81 |
| Vector-efficiency ratio store | 10.42 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | 6.25 |
| Vector-efficiency ratio other | 20.31 |
| Path / |
| Function | main |
| Source file and lines | attention_v2.cpp:163-164 |
| Module | attention-clang-znver5-512 |
| nb instructions | 16.50 |
| nb uops | 17.50 |
| loop length | 86 |
| used x86 registers | 4 |
| used mmx registers | 0 |
| used xmm registers | 2 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 3 |
| micro-operation queue | 2.19 cycles |
| front end | 2.19 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 0.50 | 0.50 | 1.17 | 1.17 | 1.17 | 1.88 | 1.88 | 1.88 | 1.88 | 0.50 | 0.50 | 0.50 | 0.50 | 1.00 | 1.00 |
| cycles | 0.50 | 0.50 | 0.50 | 1.17 | 1.17 | 1.17 | 1.88 | 1.88 | 1.88 | 1.88 | 0.50 | 0.50 | 0.50 | 0.50 | 1.00 | 1.00 |
| Cycles executing div or sqrt instructions | 2.50 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 2.19 |
| Dispatch | 1.88 |
| DIV/SQRT | 2.50 |
| Data deps. | 1.00 |
| Overall L1 | 2.69 |
| all | 25% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 100% |
| all | 24% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 58% |
| all | 23% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 62% |
| all | 15% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 25% |
| all | 10% |
| load | 6% |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 6% |
| other | 17% |
| all | 11% |
| load | 7% |
| store | 8% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 6% |
| other | 17% |
| Function | main |
| Source file and lines | attention_v2.cpp:163-164 |
| Module | attention-clang-znver5-512 |
| nb instructions | 12 |
| nb uops | 12 |
| loop length | 59 |
| used x86 registers | 4 |
| used mmx registers | 0 |
| used xmm registers | 2 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 2 |
| micro-operation queue | 1.50 cycles |
| front end | 1.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.33 | 0.33 | 0.33 | 1.00 | 1.00 | 1.00 | 1.25 | 1.25 | 1.25 | 1.25 | 0.50 | 0.50 | 0.50 | 0.50 | 1.00 | 1.00 |
| cycles | 0.33 | 0.33 | 0.33 | 1.00 | 1.00 | 1.00 | 1.25 | 1.25 | 1.25 | 1.25 | 0.50 | 0.50 | 0.50 | 0.50 | 1.00 | 1.00 |
| Cycles executing div or sqrt instructions | 2.50 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 1.50 |
| Dispatch | 1.25 |
| DIV/SQRT | 2.50 |
| Data deps. | 1.00 |
| Overall L1 | 2.50 |
| all | 20% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 50% |
| all | 10% |
| load | 6% |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 6% |
| other | 15% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVSS 0x4a1c(%RIP),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VXORPS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| MOV %RAX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.13 | N/A |
| JMP 4675 <main+0xcc5> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| VDIVSS %XMM1,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 10 | 2.50 | scal (6.3%) |
| VUCOMISS 0x4578(%RIP),%XMM0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0.50 | 7 | 0.50 | scal (6.3%) |
| JAE 4abf <main+0x110f> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33-0.50 | N/A |
| MOV 0x70(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| VMOVSS %XMM0,(%RCX,%R9,4) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (6.3%) |
| INC %R9 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP 0xb0(%RSP),%R9 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| JNE 45f0 <main+0xc40> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33-0.50 | N/A |
| Function | main |
| Source file and lines | attention_v2.cpp:163-164 |
| Module | attention-clang-znver5-512 |
| nb instructions | 21 |
| nb uops | 23 |
| loop length | 113 |
| used x86 registers | 4 |
| used mmx registers | 0 |
| used xmm registers | 2 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 4 |
| micro-operation queue | 2.88 cycles |
| front end | 2.88 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.67 | 0.67 | 0.67 | 1.33 | 1.33 | 1.33 | 2.50 | 2.50 | 2.50 | 2.50 | 0.50 | 0.50 | 0.50 | 0.50 | 1.00 | 1.00 |
| cycles | 0.67 | 0.67 | 0.67 | 1.33 | 1.33 | 1.33 | 2.50 | 2.50 | 2.50 | 2.50 | 0.50 | 0.50 | 0.50 | 0.50 | 1.00 | 1.00 |
| Cycles executing div or sqrt instructions | 2.50 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 2.88 |
| Dispatch | 2.50 |
| DIV/SQRT | 2.50 |
| Data deps. | 1.00 |
| Overall L1 | 2.88 |
| all | 25% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 100% |
| all | 28% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 66% |
| all | 27% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 75% |
| all | 15% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 25% |
| all | 11% |
| load | 6% |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 6% |
| other | 18% |
| all | 13% |
| load | 7% |
| store | 10% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 6% |
| other | 20% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVSS 0x4a1c(%RIP),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VXORPS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| MOV %RAX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.13 | N/A |
| JMP 4675 <main+0xcc5> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| VDIVSS %XMM1,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 10 | 2.50 | scal (6.3%) |
| VUCOMISS 0x4578(%RIP),%XMM0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0.50 | 7 | 0.50 | scal (6.3%) |
| JAE 4abf <main+0x110f> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33-0.50 | N/A |
| MOV 0x70(%RSP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| VMOVSS %XMM0,(%RCX,%R9,4) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 0.50 | scal (6.3%) |
| INC %R9 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP 0xb0(%RSP),%R9 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| JNE 45f0 <main+0xc40> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33-0.50 | N/A |
| VMOVSS 0x454d(%RIP),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VXORPS %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| MOV %RAX,0x2c0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| MOV %R9,0x200(%RSP) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VZEROUPPER | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | vect (25.0%) |
| CALL 10a0 <nextafterf@plt> | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | N/A |
| MOV 0x200(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| MOV 0x2c0(%RSP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | scal (12.5%) |
| JMP 4a9e <main+0x10ee> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
