OV - attention-clang-znver5-256 - Loop 98 - attention-clang-znver5-256

	Loop Id: 98	Module: attention-clang-znver5-256	Source: attention_v2.cpp:163-164 [...]	Coverage: 0.06%

0x39f0 VMOVSS	0x461c(%RIP),%XMM1

0x39f8 VPXOR	%XMM0,%XMM0,%XMM0

0x39fc MOV	%RAX,%RCX

0x39ff JMP	3a75

  (99) 0x3a10 MOV	%R13,%RDX

  (99) 0x3a13 INC	%R13

  (99) 0x3a16 MOV	$0x200b,%ESI

  (99) 0x3a1b MOV	%R13,0x1818(%RSP)

  (99) 0x3a23 MOV	0x498(%RSP,%RDX,8),%RDX

  (99) 0x3a2b BEXTR	%RSI,%RDX,%RSI

  (99) 0x3a30 XOR	%RDX,%RSI

  (99) 0x3a33 MOV	%ESI,%EDX

  (99) 0x3a35 SAL	$0x7,%EDX

  (99) 0x3a38 AND	$-0x62d3a980,%EDX

  (99) 0x3a3e XOR	%RSI,%RDX

  (99) 0x3a41 MOV	%EDX,%ESI

  (99) 0x3a43 SAL	$0xf,%ESI

  (99) 0x3a46 AND	$-0x103a0000,%ESI

  (99) 0x3a4c XOR	%RDX,%RSI

  (99) 0x3a4f MOV	%RSI,%RDX

  (99) 0x3a52 SHR	$0x12,%RDX

  (99) 0x3a56 XOR	%RSI,%RDX

  (99) 0x3a59 DEC	%RCX

  (99) 0x3a5c VCVTUSI2SS	%RDX,%XMM15,%XMM2

  (99) 0x3a62 VFMADD231SS	%XMM2,%XMM1,%XMM0

  (99) 0x3a67 VMULSS	0x4599(%RIP),%XMM1,%XMM1

  (99) 0x3a6f JE	3e80

  (99) 0x3a75 CMP	$0x270,%R13

  (99) 0x3a7c JB	3a10

  (99) 0x3a7e VPBROADCASTQ	0x45b9(%RIP),%YMM14

  (99) 0x3a87 VPBROADCASTQ	0x45b8(%RIP),%YMM15

  (99) 0x3a90 VPBROADCASTQ	0x45b6(%RIP),%YMM16

  (99) 0x3a9a VPBROADCASTQ	0x45b4(%RIP),%YMM17

  (99) 0x3aa4 VPBROADCASTQ	%RBX,%YMM2

  (99) 0x3aaa XOR	%EDX,%EDX

  (99) 0x3aac NOPL	(%RAX)

    (100) 0x3ab0 VMOVDQU	0x4a0(%RSP,%RDX,8),%YMM3

    (100) 0x3ab9 VMOVDQU	0x4c0(%RSP,%RDX,8),%YMM4

    (100) 0x3ac2 VMOVDQU	0x4e0(%RSP,%RDX,8),%YMM5

    (100) 0x3acb VALIGNQ	$0x3,%YMM2,%YMM3,%YMM6

    (100) 0x3ad2 VMOVDQU	0x500(%RSP,%RDX,8),%YMM2

    (100) 0x3adb VALIGNQ	$0x3,%YMM3,%YMM4,%YMM7

    (100) 0x3ae2 VALIGNQ	$0x3,%YMM4,%YMM5,%YMM8

    (100) 0x3ae9 VPAND	%YMM3,%YMM15,%YMM10

    (100) 0x3aed VPAND	%YMM4,%YMM15,%YMM11

    (100) 0x3af1 VPAND	%YMM5,%YMM15,%YMM12

    (100) 0x3af5 VPTESTMQ	%YMM16,%YMM3,%K1

    (100) 0x3afb VPTESTMQ	%YMM16,%YMM4,%K2

    (100) 0x3b01 VPTESTMQ	%YMM16,%YMM5,%K3

    (100) 0x3b07 VPTERNLOGQ	$-0x8,%YMM14,%YMM6,%YMM10

    (100) 0x3b0e VPTERNLOGQ	$-0x8,%YMM14,%YMM7,%YMM11

    (100) 0x3b15 VPTERNLOGQ	$-0x8,%YMM14,%YMM8,%YMM12

    (100) 0x3b1c VPSRLQ	$0x1,%YMM10,%YMM6

    (100) 0x3b22 VPSRLQ	$0x1,%YMM11,%YMM7

    (100) 0x3b28 VPSRLQ	$0x1,%YMM12,%YMM8

    (100) 0x3b2e VPXOR	0x1100(%RSP,%RDX,8),%YMM6,%YMM6

    (100) 0x3b37 VPXOR	0x1120(%RSP,%RDX,8),%YMM7,%YMM7

    (100) 0x3b40 VPXOR	0x1140(%RSP,%RDX,8),%YMM8,%YMM8

    (100) 0x3b49 VALIGNQ	$0x3,%YMM5,%YMM2,%YMM9

    (100) 0x3b50 VPAND	%YMM2,%YMM15,%YMM13

    (100) 0x3b54 VPTESTMQ	%YMM16,%YMM2,%K4

    (100) 0x3b5a VPTERNLOGQ	$-0x8,%YMM14,%YMM9,%YMM13

    (100) 0x3b61 VPSRLQ	$0x1,%YMM13,%YMM9

    (100) 0x3b67 VPXOR	0x1160(%RSP,%RDX,8),%YMM9,%YMM9

    (100) 0x3b70 VPXORQ	%YMM17,%YMM6,%YMM6{%K1}

    (100) 0x3b76 VPXORQ	%YMM17,%YMM7,%YMM7{%K2}

    (100) 0x3b7c VPXORQ	%YMM17,%YMM8,%YMM8{%K3}

    (100) 0x3b82 VMOVDQU	%YMM6,0x498(%RSP,%RDX,8)

    (100) 0x3b8b VMOVDQU	%YMM7,0x4b8(%RSP,%RDX,8)

    (100) 0x3b94 VMOVDQU	%YMM8,0x4d8(%RSP,%RDX,8)

    (100) 0x3b9d VPXORQ	%YMM17,%YMM9,%YMM9{%K4}

    (100) 0x3ba3 VMOVDQU	%YMM9,0x4f8(%RSP,%RDX,8)

    (100) 0x3bac ADD	$0x10,%RDX

    (100) 0x3bb0 CMP	$0xe0,%RDX

    (100) 0x3bb7 JNE	3ab0

  (99) 0x3bbd MOV	0xba0(%RSP),%RSI

  (99) 0x3bc5 VEXTRACTI128	$0x1,%YMM2,%XMM2

  (99) 0x3bcb MOV	0xba8(%RSP),%RDX

  (99) 0x3bd3 VPBROADCASTQ	0x4464(%RIP),%XMM8

  (99) 0x3bdc VPBROADCASTQ	0x4463(%RIP),%XMM9

  (99) 0x3be5 VPBROADCASTQ	0x4462(%RIP),%XMM10

  (99) 0x3bee VPBROADCASTQ	0x4461(%RIP),%XMM11

  (99) 0x3bf7 VPEXTRQ	$0x1,%XMM2,%RDI

  (99) 0x3bfd AND	$-0x80000000,%RDI

  (99) 0x3c04 MOV	%ESI,%R8D

  (99) 0x3c07 AND	$0x7ffffffe,%R8D

  (99) 0x3c0e OR	%RDI,%R8

  (99) 0x3c11 MOV	%ESI,%EDI

  (99) 0x3c13 AND	$0x1,%EDI

  (99) 0x3c16 AND	$-0x80000000,%RSI

  (99) 0x3c1d SHR	$0x1,%R8

  (99) 0x3c20 XOR	0x1800(%RSP),%R8

  (99) 0x3c28 NEG	%EDI

  (99) 0x3c2a AND	%R12D,%EDI

  (99) 0x3c2d XOR	%R8,%RDI

  (99) 0x3c30 MOV	%RDI,0xb98(%RSP)

  (99) 0x3c38 MOV	%EDX,%EDI

  (99) 0x3c3a AND	$0x7ffffffe,%EDI

  (99) 0x3c40 OR	%RSI,%RDI

  (99) 0x3c43 MOV	%EDX,%ESI

  (99) 0x3c45 AND	$0x1,%ESI

  (99) 0x3c48 AND	$-0x80000000,%RDX

  (99) 0x3c4f SHR	$0x1,%RDI

  (99) 0x3c52 XOR	0x1808(%RSP),%RDI

  (99) 0x3c5a NEG	%ESI

  (99) 0x3c5c AND	%R12D,%ESI

  (99) 0x3c5f XOR	%RDI,%RSI

  (99) 0x3c62 MOV	%RSI,0xba0(%RSP)

  (99) 0x3c6a MOV	0xbb0(%RSP),%RSI

  (99) 0x3c72 MOV	%ESI,%EDI

  (99) 0x3c74 VPBROADCASTQ	%RSI,%XMM2

  (99) 0x3c7a AND	$0x7ffffffe,%ESI

  (99) 0x3c80 AND	$0x1,%EDI

  (99) 0x3c83 OR	%RDX,%RSI

  (99) 0x3c86 NEG	%EDI

  (99) 0x3c88 MOV	$0xee,%EDX

  (99) 0x3c8d SHR	$0x1,%RSI

  (99) 0x3c90 XOR	0x1810(%RSP),%RSI

  (99) 0x3c98 AND	%R12D,%EDI

  (99) 0x3c9b XOR	%RSI,%RDI

  (99) 0x3c9e MOV	%RDI,0xba8(%RSP)

  (99) 0x3ca6 NOPW	%CS:(%RAX,%RAX,1)

    (101) 0x3cb0 VMOVDQU	0x448(%RSP,%RDX,8),%XMM3

    (101) 0x3cb9 VMOVDQU	0x458(%RSP,%RDX,8),%XMM4

    (101) 0x3cc2 VMOVDQU	0x468(%RSP,%RDX,8),%XMM5

    (101) 0x3ccb VMOVDQU	0x478(%RSP,%RDX,8),%XMM6

    (101) 0x3cd4 VPALIGNR	$0x8,%XMM2,%XMM3,%XMM2

    (101) 0x3cda VPAND	%XMM3,%XMM9,%XMM7

    (101) 0x3cde VPTESTMQ	%XMM10,%XMM3,%K1

    (101) 0x3ce4 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM7

    (101) 0x3ceb VPSRLQ	$0x1,%XMM7,%XMM2

    (101) 0x3cf0 VPXOR	-0x2d8(%RSP,%RDX,8),%XMM2,%XMM2

    (101) 0x3cf9 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (101) 0x3cff VPTESTMQ	%XMM10,%XMM4,%K1

    (101) 0x3d05 VMOVDQU	%XMM2,0x440(%RSP,%RDX,8)

    (101) 0x3d0e VPALIGNR	$0x8,%XMM3,%XMM4,%XMM2

    (101) 0x3d14 VPAND	%XMM4,%XMM9,%XMM3

    (101) 0x3d18 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

    (101) 0x3d1f VPSRLQ	$0x1,%XMM3,%XMM2

    (101) 0x3d24 VPXOR	-0x2c8(%RSP,%RDX,8),%XMM2,%XMM2

    (101) 0x3d2d VPAND	%XMM5,%XMM9,%XMM3

    (101) 0x3d31 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (101) 0x3d37 VPTESTMQ	%XMM10,%XMM5,%K1

    (101) 0x3d3d VMOVDQU	%XMM2,0x450(%RSP,%RDX,8)

    (101) 0x3d46 VPALIGNR	$0x8,%XMM4,%XMM5,%XMM2

    (101) 0x3d4c VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

    (101) 0x3d53 VPSRLQ	$0x1,%XMM3,%XMM2

    (101) 0x3d58 VPXOR	-0x2b8(%RSP,%RDX,8),%XMM2,%XMM2

    (101) 0x3d61 VPAND	%XMM6,%XMM9,%XMM3

    (101) 0x3d65 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (101) 0x3d6b VPTESTMQ	%XMM10,%XMM6,%K1

    (101) 0x3d71 VMOVDQU	%XMM2,0x460(%RSP,%RDX,8)

    (101) 0x3d7a VPALIGNR	$0x8,%XMM5,%XMM6,%XMM2

    (101) 0x3d80 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

    (101) 0x3d87 VPSRLQ	$0x1,%XMM3,%XMM2

    (101) 0x3d8c VPXOR	-0x2a8(%RSP,%RDX,8),%XMM2,%XMM2

    (101) 0x3d95 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (101) 0x3d9b VMOVDQU	%XMM2,0x470(%RSP,%RDX,8)

    (101) 0x3da4 VMOVDQU	0x488(%RSP,%RDX,8),%XMM3

    (101) 0x3dad VPALIGNR	$0x8,%XMM6,%XMM3,%XMM2

    (101) 0x3db3 VPAND	%XMM3,%XMM9,%XMM4

    (101) 0x3db7 VPTESTMQ	%XMM10,%XMM3,%K1

    (101) 0x3dbd VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM4

    (101) 0x3dc4 VPSRLQ	$0x1,%XMM4,%XMM2

    (101) 0x3dc9 VPXOR	-0x298(%RSP,%RDX,8),%XMM2,%XMM2

    (101) 0x3dd2 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (101) 0x3dd8 VMOVDQU	%XMM2,0x480(%RSP,%RDX,8)

    (101) 0x3de1 VMOVDQU	0x498(%RSP,%RDX,8),%XMM2

    (101) 0x3dea VPALIGNR	$0x8,%XMM3,%XMM2,%XMM3

    (101) 0x3df0 VPAND	%XMM2,%XMM9,%XMM4

    (101) 0x3df4 VPTESTMQ	%XMM10,%XMM2,%K1

    (101) 0x3dfa VPTERNLOGQ	$-0x8,%XMM8,%XMM3,%XMM4

    (101) 0x3e01 VPSRLQ	$0x1,%XMM4,%XMM3

    (101) 0x3e06 VPXOR	-0x288(%RSP,%RDX,8),%XMM3,%XMM3

    (101) 0x3e0f VPXORQ	%XMM11,%XMM3,%XMM3{%K1}

    (101) 0x3e15 VMOVDQU	%XMM3,0x490(%RSP,%RDX,8)

    (101) 0x3e1e ADD	$0xc,%RDX

    (101) 0x3e22 CMP	$0x27a,%RDX

    (101) 0x3e29 JNE	3cb0

  (99) 0x3e2f MOV	0x1810(%RSP),%RDX

  (99) 0x3e37 MOV	0x498(%RSP),%RBX

  (99) 0x3e3f XOR	%R13D,%R13D

  (99) 0x3e42 MOV	%EBX,%ESI

  (99) 0x3e44 AND	%R14,%RDX

  (99) 0x3e47 AND	$0x7ffffffe,%ESI

  (99) 0x3e4d OR	%RDX,%RSI

  (99) 0x3e50 MOV	%EBX,%EDX

  (99) 0x3e52 AND	$0x1,%EDX

  (99) 0x3e55 SHR	$0x1,%RSI

  (99) 0x3e58 XOR	0x10f8(%RSP),%RSI

  (99) 0x3e60 NEG	%EDX

  (99) 0x3e62 AND	%R12D,%EDX

  (99) 0x3e65 XOR	%RSI,%RDX

  (99) 0x3e68 MOV	%RDX,0x1810(%RSP)

  (99) 0x3e70 JMP	3a10

0x3e80 VDIVSS	%XMM1,%XMM0,%XMM0

0x3e84 VUCOMISS	0x4188(%RIP),%XMM0

0x3e8c JAE	3eaf

0x3e8e MOV	0x48(%RSP),%RCX

0x3e93 VMOVSS	%XMM0,(%RCX,%R9,4)

0x3e99 INC	%R9

0x3e9c CMP	0x90(%RSP),%R9

0x3ea4 JNE	39f0

0x3eaf VMOVSS	0x415d(%RIP),%XMM0

0x3eb7 VXORPS	%XMM1,%XMM1,%XMM1

0x3ebb MOV	%RAX,0x140(%RSP)

0x3ec3 MOV	%R9,0x120(%RSP)

0x3ecb VZEROUPPER

0x3ece CALL	10a0 <nextafterf@plt>

0x3ed3 MOV	0x120(%RSP),%R9

0x3edb MOV	0x140(%RSP),%RAX

0x3ee3 JMP	3e8e

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath: 1661 - 1661

--------------------------------------------------------------------------------

1661:   { return __builtin_nextafterf(__x, __y); }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 401 - 3370

--------------------------------------------------------------------------------

401:       for (size_t __k = 0; __k < (__n - __m); ++__k)

402:         {

403: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

404: 			   | (_M_x[__k + 1] & __lower_mask));

405: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

406: 		       ^ ((__y & 0x01) ? __a : 0));

407:         }

408:

409:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

410: 	{

411: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

412: 			   | (_M_x[__k + 1] & __lower_mask));

413: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

414: 		       ^ ((__y & 0x01) ? __a : 0));

415: 	}

416:

417:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

418: 		       | (_M_x[0] & __lower_mask));

419:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

420: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

455:       if (_M_p >= state_size)

456: 	_M_gen_rand();

457:

458:       // Calculate o(x(i)).

459:       result_type __z = _M_x[_M_p++];

460:       __z ^= (__z >> __u) & __d;

461:       __z ^= (__z << __s) & __b;

462:       __z ^= (__z << __t) & __c;

463:       __z ^= (__z >> __l);

[...]

3364:       for (size_t __k = __m; __k != 0; --__k)

3365: 	{

3366: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3367: 	  __tmp *= __r;

3368: 	}

3369:       __ret = __sum / __tmp;

3370:       if (__builtin_expect(__ret >= _RealType(1), 0))

/home/eoseret/llm-attention/attention_v2.cpp: 163 - 164

--------------------------------------------------------------------------------

163:       for (size_t i = 0; i < elemsX; ++i) h_X[i] = dist(rng);

164:       for (size_t i = 0; i < elemsW; ++i) {

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.07
CQA speedup if FP arith vectorized	1.92
CQA speedup if fully vectorized	13.88
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.34
Bottlenecks
Function	main
Source	cmath:1661-1661,random.tcc:3369-3370,attention_v2.cpp:163-164
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.69
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	1.40
CQA cycles if fully vectorized	0.19
Front-end cycles	2.19
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	1.17
P4 cycles	1.17
P5 cycles	1.17
P6 cycles	1.88
P7 cycles	1.88
P8 cycles	1.88
P9 cycles	1.88
P10 cycles	0.50
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	2.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.50
Nb uops	17.50
Nb loads	5.50
Nb stores	2.00
Nb stack references	3.00
FLOP/cycle	0.37
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.73
Bytes prefetched	0.00
Bytes loaded	34.00
Bytes stored	12.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	23.64
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	62.50
Vector-efficiency ratio all	11.53
Vector-efficiency ratio load	7.03
Vector-efficiency ratio store	8.33
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	17.97

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.50
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.67
Bottlenecks	P10, P11,
Function	main
Source	cmath:1661-1661,random.tcc:3369-3370,attention_v2.cpp:163-164
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	1.00
CQA cycles if fully vectorized	0.16
Front-end cycles	1.50
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	1.25
P7 cycles	1.25
P8 cycles	1.25
P9 cycles	1.25
P10 cycles	0.50
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	2.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	12.00
Nb uops	12.00
Nb loads	4.00
Nb stores	1.00
Nb stack references	2.00
FLOP/cycle	0.40
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.20
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	20.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	10.00
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	15.63

Metric	Value
CQA speedup if no scalar integer	1.15
CQA speedup if FP arith vectorized	1.60
CQA speedup if fully vectorized	12.44
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	micro-operation queue,
Function	main
Source	cmath:1661-1661,random.tcc:3369-3370,attention_v2.cpp:163-164
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.88
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	1.80
CQA cycles if fully vectorized	0.23
Front-end cycles	2.88
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	1.33
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	2.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	0.50
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	2.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	23.00
Nb loads	7.00
Nb stores	3.00
Nb stack references	4.00
FLOP/cycle	0.35
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.26
Bytes prefetched	0.00
Bytes loaded	44.00
Bytes stored	20.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	27.27
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	75.00
Vector-efficiency ratio all	13.07
Vector-efficiency ratio load	7.81
Vector-efficiency ratio store	10.42
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	20.31

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:163-164
Module	attention-clang-znver5-256

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3364-3370
/home/eoseret/llm-attention/attention_v2.cpp:163-164

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.69 to 0.19 cycles (13.88x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 2.69 to 2.19 cycles (1.23x speedup).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISS: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: divide

The binary loop is loading 34 bytes (8 single precision FP elements). The binary loop is storing 12 bytes (3 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	16.50
nb uops	17.50
loop length	86
used x86 registers	4
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	2.19 cycles
front end	2.19 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	0.50	1.17	1.17	1.17	1.88	1.88	1.88	1.88	0.50	0.50	0.50	0.50	1.00	1.00
cycles	0.50	0.50	0.50	1.17	1.17	1.17	1.88	1.88	1.88	1.88	0.50	0.50	0.50	0.50	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	2.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.19
Dispatch	1.88
DIV/SQRT	2.50
Data deps.	1.00
Overall L1	2.69

Vectorization ratios

INT

all	70%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	8%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	25%

INT+FP

all	23%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	62%

Vector efficiency ratios

INT

all	21%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	7%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

INT+FP

all	11%
load	7%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.69 cycles. At this rate:

4% of peak load performance is reached (12.45 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.28 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention_v2.cpp:163-164
Module	attention-clang-znver5-256

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3364-3370
/home/eoseret/llm-attention/attention_v2.cpp:163-164

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.50 to 0.16 cycles (16.00x speedup).

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.50 to 1.50 cycles (1.67x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 2.50 to 1.50 cycles (1.67x speedup).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISS: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: divide

The binary loop is loading 24 bytes (6 single precision FP elements). The binary loop is storing 4 bytes (1 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	12
nb uops	12
loop length	59
used x86 registers	4
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.50 cycles
front end	1.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	1.00	1.00	1.00	1.25	1.25	1.25	1.25	0.50	0.50	0.50	0.50	1.00	1.00
cycles	0.33	0.33	0.33	1.00	1.00	1.00	1.25	1.25	1.25	1.25	0.50	0.50	0.50	0.50	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	2.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.50
Dispatch	1.25
DIV/SQRT	2.50
Data deps.	1.00
Overall L1	2.50

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	20%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	50%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	6%

INT+FP

all	10%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

3% of peak load performance is reached (9.60 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.60 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 39f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVSS 0x461c(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 3a75 <main+0xca5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
VUCOMISS 0x4188(%RIP),%XMM0	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	7	0.50	scal (6.3%)
JAE 3eaf <main+0x10df>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x48(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSS %XMM0,(%RCX,%R9,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x90(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JNE 39f0 <main+0xc20>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:163-164
Module	attention-clang-znver5-256

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3364-3370
/home/eoseret/llm-attention/attention_v2.cpp:163-164

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.88 to 2.50 cycles (1.15x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.88 to 0.23 cycles (12.44x speedup).

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

nextafterf@plt: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISS: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: divide

The binary loop is loading 44 bytes (11 single precision FP elements). The binary loop is storing 20 bytes (5 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	21
nb uops	23
loop length	113
used x86 registers	4
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.88 cycles
front end	2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	1.33	1.33	1.33	2.50	2.50	2.50	2.50	0.50	0.50	0.50	0.50	1.00	1.00
cycles	0.67	0.67	0.67	1.33	1.33	1.33	2.50	2.50	2.50	2.50	0.50	0.50	0.50	0.50	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	2.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.88
Dispatch	2.50
DIV/SQRT	2.50
Data deps.	1.00
Overall L1	2.88

Vectorization ratios

INT

all	40%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	16%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	50%

INT+FP

all	27%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	75%

Vector efficiency ratios

INT

all	17%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	9%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	15%

INT+FP

all	13%
load	7%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.88 cycles. At this rate:

5% of peak load performance is reached (15.30 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.96 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.88 to 2.50 cycles (1.15x speedup).

ASM code

In the binary file, the address of the loop is: 39f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVSS 0x461c(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 3a75 <main+0xca5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
VUCOMISS 0x4188(%RIP),%XMM0	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	7	0.50	scal (6.3%)
JAE 3eaf <main+0x10df>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x48(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSS %XMM0,(%RCX,%R9,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x90(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JNE 39f0 <main+0xc20>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VMOVSS 0x415d(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RAX,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 10a0 <nextafterf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV 0x120(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x140(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JMP 3e8e <main+0x10be>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A

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Vectorization

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Expensive FP math instructions/calls

Complex instructions

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Slow data structures access

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Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code