OV - attention-clang-znver5-256 - Loop 88 - attention-clang-znver5-256

	Loop Id: 88	Module: attention-clang-znver5-256	Source: attention_v2.cpp:164-167 [...]	Coverage: 0.06%

0x3f00 VMOVSS	0x410c(%RIP),%XMM1

0x3f08 VXORPS	%XMM0,%XMM0,%XMM0

0x3f0c MOV	%R8,%RAX

0x3f0f JMP	3f85

  (95) 0x3f20 MOV	%R13,%RCX

  (95) 0x3f23 INC	%R13

  (95) 0x3f26 MOV	$0x200b,%EDX

  (95) 0x3f2b MOV	%R13,0x1818(%RSP)

  (95) 0x3f33 MOV	0x498(%RSP,%RCX,8),%RCX

  (95) 0x3f3b BEXTR	%RDX,%RCX,%RDX

  (95) 0x3f40 XOR	%RCX,%RDX

  (95) 0x3f43 MOV	%EDX,%ECX

  (95) 0x3f45 SAL	$0x7,%ECX

  (95) 0x3f48 AND	$-0x62d3a980,%ECX

  (95) 0x3f4e XOR	%RDX,%RCX

  (95) 0x3f51 MOV	%ECX,%EDX

  (95) 0x3f53 SAL	$0xf,%EDX

  (95) 0x3f56 AND	$-0x103a0000,%EDX

  (95) 0x3f5c XOR	%RCX,%RDX

  (95) 0x3f5f MOV	%RDX,%RCX

  (95) 0x3f62 SHR	$0x12,%RCX

  (95) 0x3f66 XOR	%RDX,%RCX

  (95) 0x3f69 DEC	%RAX

  (95) 0x3f6c VCVTUSI2SS	%RCX,%XMM15,%XMM2

  (95) 0x3f72 VFMADD231SS	%XMM2,%XMM1,%XMM0

  (95) 0x3f77 VMULSS	0x4089(%RIP),%XMM1,%XMM1

  (95) 0x3f7f JE	4390

  (95) 0x3f85 CMP	$0x270,%R13

  (95) 0x3f8c JB	3f20

  (95) 0x3f8e VPBROADCASTQ	0x40a9(%RIP),%YMM14

  (95) 0x3f97 VPBROADCASTQ	0x40a8(%RIP),%YMM15

  (95) 0x3fa0 VPBROADCASTQ	0x40a6(%RIP),%YMM16

  (95) 0x3faa VPBROADCASTQ	0x40a4(%RIP),%YMM17

  (95) 0x3fb4 VPBROADCASTQ	%RBX,%YMM2

  (95) 0x3fba XOR	%ECX,%ECX

  (95) 0x3fbc NOPL	(%RAX)

    (96) 0x3fc0 VMOVDQU	0x4a0(%RSP,%RCX,8),%YMM3

    (96) 0x3fc9 VMOVDQU	0x4c0(%RSP,%RCX,8),%YMM4

    (96) 0x3fd2 VMOVDQU	0x4e0(%RSP,%RCX,8),%YMM5

    (96) 0x3fdb VALIGNQ	$0x3,%YMM2,%YMM3,%YMM6

    (96) 0x3fe2 VMOVDQU	0x500(%RSP,%RCX,8),%YMM2

    (96) 0x3feb VALIGNQ	$0x3,%YMM3,%YMM4,%YMM7

    (96) 0x3ff2 VALIGNQ	$0x3,%YMM4,%YMM5,%YMM8

    (96) 0x3ff9 VPAND	%YMM3,%YMM15,%YMM10

    (96) 0x3ffd VPAND	%YMM4,%YMM15,%YMM11

    (96) 0x4001 VPAND	%YMM5,%YMM15,%YMM12

    (96) 0x4005 VPTESTMQ	%YMM16,%YMM3,%K1

    (96) 0x400b VPTESTMQ	%YMM16,%YMM4,%K2

    (96) 0x4011 VPTESTMQ	%YMM16,%YMM5,%K3

    (96) 0x4017 VPTERNLOGQ	$-0x8,%YMM14,%YMM6,%YMM10

    (96) 0x401e VPTERNLOGQ	$-0x8,%YMM14,%YMM7,%YMM11

    (96) 0x4025 VPTERNLOGQ	$-0x8,%YMM14,%YMM8,%YMM12

    (96) 0x402c VPSRLQ	$0x1,%YMM10,%YMM6

    (96) 0x4032 VPSRLQ	$0x1,%YMM11,%YMM7

    (96) 0x4038 VPSRLQ	$0x1,%YMM12,%YMM8

    (96) 0x403e VPXOR	0x1100(%RSP,%RCX,8),%YMM6,%YMM6

    (96) 0x4047 VPXOR	0x1120(%RSP,%RCX,8),%YMM7,%YMM7

    (96) 0x4050 VPXOR	0x1140(%RSP,%RCX,8),%YMM8,%YMM8

    (96) 0x4059 VALIGNQ	$0x3,%YMM5,%YMM2,%YMM9

    (96) 0x4060 VPAND	%YMM2,%YMM15,%YMM13

    (96) 0x4064 VPTESTMQ	%YMM16,%YMM2,%K4

    (96) 0x406a VPTERNLOGQ	$-0x8,%YMM14,%YMM9,%YMM13

    (96) 0x4071 VPSRLQ	$0x1,%YMM13,%YMM9

    (96) 0x4077 VPXOR	0x1160(%RSP,%RCX,8),%YMM9,%YMM9

    (96) 0x4080 VPXORQ	%YMM17,%YMM6,%YMM6{%K1}

    (96) 0x4086 VPXORQ	%YMM17,%YMM7,%YMM7{%K2}

    (96) 0x408c VPXORQ	%YMM17,%YMM8,%YMM8{%K3}

    (96) 0x4092 VMOVDQU	%YMM6,0x498(%RSP,%RCX,8)

    (96) 0x409b VMOVDQU	%YMM7,0x4b8(%RSP,%RCX,8)

    (96) 0x40a4 VMOVDQU	%YMM8,0x4d8(%RSP,%RCX,8)

    (96) 0x40ad VPXORQ	%YMM17,%YMM9,%YMM9{%K4}

    (96) 0x40b3 VMOVDQU	%YMM9,0x4f8(%RSP,%RCX,8)

    (96) 0x40bc ADD	$0x10,%RCX

    (96) 0x40c0 CMP	$0xe0,%RCX

    (96) 0x40c7 JNE	3fc0

  (95) 0x40cd MOV	0xba0(%RSP),%RDX

  (95) 0x40d5 VEXTRACTI128	$0x1,%YMM2,%XMM2

  (95) 0x40db MOV	0xba8(%RSP),%RCX

  (95) 0x40e3 VPBROADCASTQ	0x3f54(%RIP),%XMM8

  (95) 0x40ec VPBROADCASTQ	0x3f53(%RIP),%XMM9

  (95) 0x40f5 VPBROADCASTQ	0x3f52(%RIP),%XMM10

  (95) 0x40fe VPBROADCASTQ	0x3f51(%RIP),%XMM11

  (95) 0x4107 VPEXTRQ	$0x1,%XMM2,%RSI

  (95) 0x410d AND	$-0x80000000,%RSI

  (95) 0x4114 MOV	%EDX,%EDI

  (95) 0x4116 AND	$0x7ffffffe,%EDI

  (95) 0x411c OR	%RSI,%RDI

  (95) 0x411f MOV	%EDX,%ESI

  (95) 0x4121 AND	$0x1,%ESI

  (95) 0x4124 AND	$-0x80000000,%RDX

  (95) 0x412b SHR	$0x1,%RDI

  (95) 0x412e XOR	0x1800(%RSP),%RDI

  (95) 0x4136 NEG	%ESI

  (95) 0x4138 AND	%R12D,%ESI

  (95) 0x413b XOR	%RDI,%RSI

  (95) 0x413e MOV	%RSI,0xb98(%RSP)

  (95) 0x4146 MOV	%ECX,%ESI

  (95) 0x4148 AND	$0x7ffffffe,%ESI

  (95) 0x414e OR	%RDX,%RSI

  (95) 0x4151 MOV	%ECX,%EDX

  (95) 0x4153 AND	$0x1,%EDX

  (95) 0x4156 AND	$-0x80000000,%RCX

  (95) 0x415d SHR	$0x1,%RSI

  (95) 0x4160 XOR	0x1808(%RSP),%RSI

  (95) 0x4168 NEG	%EDX

  (95) 0x416a AND	%R12D,%EDX

  (95) 0x416d XOR	%RSI,%RDX

  (95) 0x4170 MOV	%RDX,0xba0(%RSP)

  (95) 0x4178 MOV	0xbb0(%RSP),%RDX

  (95) 0x4180 MOV	%EDX,%ESI

  (95) 0x4182 VPBROADCASTQ	%RDX,%XMM2

  (95) 0x4188 AND	$0x7ffffffe,%EDX

  (95) 0x418e AND	$0x1,%ESI

  (95) 0x4191 OR	%RCX,%RDX

  (95) 0x4194 NEG	%ESI

  (95) 0x4196 MOV	$0xee,%ECX

  (95) 0x419b SHR	$0x1,%RDX

  (95) 0x419e XOR	0x1810(%RSP),%RDX

  (95) 0x41a6 AND	%R12D,%ESI

  (95) 0x41a9 XOR	%RDX,%RSI

  (95) 0x41ac MOV	%RSI,0xba8(%RSP)

  (95) 0x41b4 NOPW	%CS:(%RAX,%RAX,1)

    (97) 0x41c0 VMOVDQU	0x448(%RSP,%RCX,8),%XMM3

    (97) 0x41c9 VMOVDQU	0x458(%RSP,%RCX,8),%XMM4

    (97) 0x41d2 VMOVDQU	0x468(%RSP,%RCX,8),%XMM5

    (97) 0x41db VMOVDQU	0x478(%RSP,%RCX,8),%XMM6

    (97) 0x41e4 VPALIGNR	$0x8,%XMM2,%XMM3,%XMM2

    (97) 0x41ea VPAND	%XMM3,%XMM9,%XMM7

    (97) 0x41ee VPTESTMQ	%XMM10,%XMM3,%K1

    (97) 0x41f4 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM7

    (97) 0x41fb VPSRLQ	$0x1,%XMM7,%XMM2

    (97) 0x4200 VPXOR	-0x2d8(%RSP,%RCX,8),%XMM2,%XMM2

    (97) 0x4209 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (97) 0x420f VPTESTMQ	%XMM10,%XMM4,%K1

    (97) 0x4215 VMOVDQU	%XMM2,0x440(%RSP,%RCX,8)

    (97) 0x421e VPALIGNR	$0x8,%XMM3,%XMM4,%XMM2

    (97) 0x4224 VPAND	%XMM4,%XMM9,%XMM3

    (97) 0x4228 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

    (97) 0x422f VPSRLQ	$0x1,%XMM3,%XMM2

    (97) 0x4234 VPXOR	-0x2c8(%RSP,%RCX,8),%XMM2,%XMM2

    (97) 0x423d VPAND	%XMM5,%XMM9,%XMM3

    (97) 0x4241 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (97) 0x4247 VPTESTMQ	%XMM10,%XMM5,%K1

    (97) 0x424d VMOVDQU	%XMM2,0x450(%RSP,%RCX,8)

    (97) 0x4256 VPALIGNR	$0x8,%XMM4,%XMM5,%XMM2

    (97) 0x425c VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

    (97) 0x4263 VPSRLQ	$0x1,%XMM3,%XMM2

    (97) 0x4268 VPXOR	-0x2b8(%RSP,%RCX,8),%XMM2,%XMM2

    (97) 0x4271 VPAND	%XMM6,%XMM9,%XMM3

    (97) 0x4275 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (97) 0x427b VPTESTMQ	%XMM10,%XMM6,%K1

    (97) 0x4281 VMOVDQU	%XMM2,0x460(%RSP,%RCX,8)

    (97) 0x428a VPALIGNR	$0x8,%XMM5,%XMM6,%XMM2

    (97) 0x4290 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

    (97) 0x4297 VPSRLQ	$0x1,%XMM3,%XMM2

    (97) 0x429c VPXOR	-0x2a8(%RSP,%RCX,8),%XMM2,%XMM2

    (97) 0x42a5 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (97) 0x42ab VMOVDQU	%XMM2,0x470(%RSP,%RCX,8)

    (97) 0x42b4 VMOVDQU	0x488(%RSP,%RCX,8),%XMM3

    (97) 0x42bd VPALIGNR	$0x8,%XMM6,%XMM3,%XMM2

    (97) 0x42c3 VPAND	%XMM3,%XMM9,%XMM4

    (97) 0x42c7 VPTESTMQ	%XMM10,%XMM3,%K1

    (97) 0x42cd VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM4

    (97) 0x42d4 VPSRLQ	$0x1,%XMM4,%XMM2

    (97) 0x42d9 VPXOR	-0x298(%RSP,%RCX,8),%XMM2,%XMM2

    (97) 0x42e2 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (97) 0x42e8 VMOVDQU	%XMM2,0x480(%RSP,%RCX,8)

    (97) 0x42f1 VMOVDQU	0x498(%RSP,%RCX,8),%XMM2

    (97) 0x42fa VPALIGNR	$0x8,%XMM3,%XMM2,%XMM3

    (97) 0x4300 VPAND	%XMM2,%XMM9,%XMM4

    (97) 0x4304 VPTESTMQ	%XMM10,%XMM2,%K1

    (97) 0x430a VPTERNLOGQ	$-0x8,%XMM8,%XMM3,%XMM4

    (97) 0x4311 VPSRLQ	$0x1,%XMM4,%XMM3

    (97) 0x4316 VPXOR	-0x288(%RSP,%RCX,8),%XMM3,%XMM3

    (97) 0x431f VPXORQ	%XMM11,%XMM3,%XMM3{%K1}

    (97) 0x4325 VMOVDQU	%XMM3,0x490(%RSP,%RCX,8)

    (97) 0x432e ADD	$0xc,%RCX

    (97) 0x4332 CMP	$0x27a,%RCX

    (97) 0x4339 JNE	41c0

  (95) 0x433f MOV	0x1810(%RSP),%RCX

  (95) 0x4347 MOV	0x498(%RSP),%RBX

  (95) 0x434f XOR	%R13D,%R13D

  (95) 0x4352 MOV	%EBX,%EDX

  (95) 0x4354 AND	%R14,%RCX

  (95) 0x4357 AND	$0x7ffffffe,%EDX

  (95) 0x435d OR	%RCX,%RDX

  (95) 0x4360 MOV	%EBX,%ECX

  (95) 0x4362 AND	$0x1,%ECX

  (95) 0x4365 SHR	$0x1,%RDX

  (95) 0x4368 XOR	0x10f8(%RSP),%RDX

  (95) 0x4370 NEG	%ECX

  (95) 0x4372 AND	%R12D,%ECX

  (95) 0x4375 XOR	%RDX,%RCX

  (95) 0x4378 MOV	%RCX,0x1810(%RSP)

  (95) 0x4380 JMP	3f20

0x4390 VDIVSS	%XMM1,%XMM0,%XMM0

0x4394 VMOVSS	0x3c78(%RIP),%XMM2

0x439c VUCOMISS	%XMM2,%XMM0

0x43a0 JAE	4d16

0x43a6 VMOVSS	%XMM0,(%R15,%R9,4)

0x43ac VXORPS	%XMM0,%XMM0,%XMM0

0x43b0 MOV	%R8,%RAX

0x43b3 VMOVAPS	%XMM2,%XMM1

0x43b7 JMP	4425

  (92) 0x43c0 MOV	%R13,%RCX

  (92) 0x43c3 INC	%R13

  (92) 0x43c6 MOV	$0x200b,%EDX

  (92) 0x43cb MOV	%R13,0x1818(%RSP)

  (92) 0x43d3 MOV	0x498(%RSP,%RCX,8),%RCX

  (92) 0x43db BEXTR	%RDX,%RCX,%RDX

  (92) 0x43e0 XOR	%RCX,%RDX

  (92) 0x43e3 MOV	%EDX,%ECX

  (92) 0x43e5 SAL	$0x7,%ECX

  (92) 0x43e8 AND	$-0x62d3a980,%ECX

  (92) 0x43ee XOR	%RDX,%RCX

  (92) 0x43f1 MOV	%ECX,%EDX

  (92) 0x43f3 SAL	$0xf,%EDX

  (92) 0x43f6 AND	$-0x103a0000,%EDX

  (92) 0x43fc XOR	%RCX,%RDX

  (92) 0x43ff MOV	%RDX,%RCX

  (92) 0x4402 SHR	$0x12,%RCX

  (92) 0x4406 XOR	%RDX,%RCX

  (92) 0x4409 DEC	%RAX

  (92) 0x440c VCVTUSI2SS	%RCX,%XMM15,%XMM2

  (92) 0x4412 VFMADD231SS	%XMM2,%XMM1,%XMM0

  (92) 0x4417 VMULSS	0x3be9(%RIP),%XMM1,%XMM1

  (92) 0x441f JE	4830

  (92) 0x4425 CMP	$0x270,%R13

  (92) 0x442c JB	43c0

  (92) 0x442e VPBROADCASTQ	0x3c09(%RIP),%YMM14

  (92) 0x4437 VPBROADCASTQ	0x3c08(%RIP),%YMM15

  (92) 0x4440 VPBROADCASTQ	0x3c06(%RIP),%YMM16

  (92) 0x444a VPBROADCASTQ	0x3c04(%RIP),%YMM17

  (92) 0x4454 VPBROADCASTQ	%RBX,%YMM2

  (92) 0x445a XOR	%ECX,%ECX

  (92) 0x445c NOPL	(%RAX)

    (93) 0x4460 VMOVDQU	0x4a0(%RSP,%RCX,8),%YMM3

    (93) 0x4469 VMOVDQU	0x4c0(%RSP,%RCX,8),%YMM4

    (93) 0x4472 VMOVDQU	0x4e0(%RSP,%RCX,8),%YMM5

    (93) 0x447b VALIGNQ	$0x3,%YMM2,%YMM3,%YMM6

    (93) 0x4482 VMOVDQU	0x500(%RSP,%RCX,8),%YMM2

    (93) 0x448b VALIGNQ	$0x3,%YMM3,%YMM4,%YMM7

    (93) 0x4492 VALIGNQ	$0x3,%YMM4,%YMM5,%YMM8

    (93) 0x4499 VPAND	%YMM3,%YMM15,%YMM10

    (93) 0x449d VPAND	%YMM4,%YMM15,%YMM11

    (93) 0x44a1 VPAND	%YMM5,%YMM15,%YMM12

    (93) 0x44a5 VPTESTMQ	%YMM16,%YMM3,%K1

    (93) 0x44ab VPTESTMQ	%YMM16,%YMM4,%K2

    (93) 0x44b1 VPTESTMQ	%YMM16,%YMM5,%K3

    (93) 0x44b7 VPTERNLOGQ	$-0x8,%YMM14,%YMM6,%YMM10

    (93) 0x44be VPTERNLOGQ	$-0x8,%YMM14,%YMM7,%YMM11

    (93) 0x44c5 VPTERNLOGQ	$-0x8,%YMM14,%YMM8,%YMM12

    (93) 0x44cc VPSRLQ	$0x1,%YMM10,%YMM6

    (93) 0x44d2 VPSRLQ	$0x1,%YMM11,%YMM7

    (93) 0x44d8 VPSRLQ	$0x1,%YMM12,%YMM8

    (93) 0x44de VPXOR	0x1100(%RSP,%RCX,8),%YMM6,%YMM6

    (93) 0x44e7 VPXOR	0x1120(%RSP,%RCX,8),%YMM7,%YMM7

    (93) 0x44f0 VPXOR	0x1140(%RSP,%RCX,8),%YMM8,%YMM8

    (93) 0x44f9 VALIGNQ	$0x3,%YMM5,%YMM2,%YMM9

    (93) 0x4500 VPAND	%YMM2,%YMM15,%YMM13

    (93) 0x4504 VPTESTMQ	%YMM16,%YMM2,%K4

    (93) 0x450a VPTERNLOGQ	$-0x8,%YMM14,%YMM9,%YMM13

    (93) 0x4511 VPSRLQ	$0x1,%YMM13,%YMM9

    (93) 0x4517 VPXOR	0x1160(%RSP,%RCX,8),%YMM9,%YMM9

    (93) 0x4520 VPXORQ	%YMM17,%YMM6,%YMM6{%K1}

    (93) 0x4526 VPXORQ	%YMM17,%YMM7,%YMM7{%K2}

    (93) 0x452c VPXORQ	%YMM17,%YMM8,%YMM8{%K3}

    (93) 0x4532 VMOVDQU	%YMM6,0x498(%RSP,%RCX,8)

    (93) 0x453b VMOVDQU	%YMM7,0x4b8(%RSP,%RCX,8)

    (93) 0x4544 VMOVDQU	%YMM8,0x4d8(%RSP,%RCX,8)

    (93) 0x454d VPXORQ	%YMM17,%YMM9,%YMM9{%K4}

    (93) 0x4553 VMOVDQU	%YMM9,0x4f8(%RSP,%RCX,8)

    (93) 0x455c ADD	$0x10,%RCX

    (93) 0x4560 CMP	$0xe0,%RCX

    (93) 0x4567 JNE	4460

  (92) 0x456d MOV	0xba0(%RSP),%RDX

  (92) 0x4575 VEXTRACTI128	$0x1,%YMM2,%XMM2

  (92) 0x457b MOV	0xba8(%RSP),%RCX

  (92) 0x4583 VPBROADCASTQ	0x3ab4(%RIP),%XMM8

  (92) 0x458c VPBROADCASTQ	0x3ab3(%RIP),%XMM9

  (92) 0x4595 VPBROADCASTQ	0x3ab2(%RIP),%XMM10

  (92) 0x459e VPBROADCASTQ	0x3ab1(%RIP),%XMM11

  (92) 0x45a7 VPEXTRQ	$0x1,%XMM2,%RSI

  (92) 0x45ad AND	$-0x80000000,%RSI

  (92) 0x45b4 MOV	%EDX,%EDI

  (92) 0x45b6 AND	$0x7ffffffe,%EDI

  (92) 0x45bc OR	%RSI,%RDI

  (92) 0x45bf MOV	%EDX,%ESI

  (92) 0x45c1 AND	$0x1,%ESI

  (92) 0x45c4 AND	$-0x80000000,%RDX

  (92) 0x45cb SHR	$0x1,%RDI

  (92) 0x45ce XOR	0x1800(%RSP),%RDI

  (92) 0x45d6 NEG	%ESI

  (92) 0x45d8 AND	%R12D,%ESI

  (92) 0x45db XOR	%RDI,%RSI

  (92) 0x45de MOV	%RSI,0xb98(%RSP)

  (92) 0x45e6 MOV	%ECX,%ESI

  (92) 0x45e8 AND	$0x7ffffffe,%ESI

  (92) 0x45ee OR	%RDX,%RSI

  (92) 0x45f1 MOV	%ECX,%EDX

  (92) 0x45f3 AND	$0x1,%EDX

  (92) 0x45f6 AND	$-0x80000000,%RCX

  (92) 0x45fd SHR	$0x1,%RSI

  (92) 0x4600 XOR	0x1808(%RSP),%RSI

  (92) 0x4608 NEG	%EDX

  (92) 0x460a AND	%R12D,%EDX

  (92) 0x460d XOR	%RSI,%RDX

  (92) 0x4610 MOV	%RDX,0xba0(%RSP)

  (92) 0x4618 MOV	0xbb0(%RSP),%RDX

  (92) 0x4620 MOV	%EDX,%ESI

  (92) 0x4622 VPBROADCASTQ	%RDX,%XMM2

  (92) 0x4628 AND	$0x7ffffffe,%EDX

  (92) 0x462e AND	$0x1,%ESI

  (92) 0x4631 OR	%RCX,%RDX

  (92) 0x4634 NEG	%ESI

  (92) 0x4636 MOV	$0xee,%ECX

  (92) 0x463b SHR	$0x1,%RDX

  (92) 0x463e XOR	0x1810(%RSP),%RDX

  (92) 0x4646 AND	%R12D,%ESI

  (92) 0x4649 XOR	%RDX,%RSI

  (92) 0x464c MOV	%RSI,0xba8(%RSP)

  (92) 0x4654 NOPW	%CS:(%RAX,%RAX,1)

    (94) 0x4660 VMOVDQU	0x448(%RSP,%RCX,8),%XMM3

    (94) 0x4669 VMOVDQU	0x458(%RSP,%RCX,8),%XMM4

    (94) 0x4672 VMOVDQU	0x468(%RSP,%RCX,8),%XMM5

    (94) 0x467b VMOVDQU	0x478(%RSP,%RCX,8),%XMM6

    (94) 0x4684 VPALIGNR	$0x8,%XMM2,%XMM3,%XMM2

    (94) 0x468a VPAND	%XMM3,%XMM9,%XMM7

    (94) 0x468e VPTESTMQ	%XMM10,%XMM3,%K1

    (94) 0x4694 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM7

    (94) 0x469b VPSRLQ	$0x1,%XMM7,%XMM2

    (94) 0x46a0 VPXOR	-0x2d8(%RSP,%RCX,8),%XMM2,%XMM2

    (94) 0x46a9 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (94) 0x46af VPTESTMQ	%XMM10,%XMM4,%K1

    (94) 0x46b5 VMOVDQU	%XMM2,0x440(%RSP,%RCX,8)

    (94) 0x46be VPALIGNR	$0x8,%XMM3,%XMM4,%XMM2

    (94) 0x46c4 VPAND	%XMM4,%XMM9,%XMM3

    (94) 0x46c8 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

    (94) 0x46cf VPSRLQ	$0x1,%XMM3,%XMM2

    (94) 0x46d4 VPXOR	-0x2c8(%RSP,%RCX,8),%XMM2,%XMM2

    (94) 0x46dd VPAND	%XMM5,%XMM9,%XMM3

    (94) 0x46e1 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (94) 0x46e7 VPTESTMQ	%XMM10,%XMM5,%K1

    (94) 0x46ed VMOVDQU	%XMM2,0x450(%RSP,%RCX,8)

    (94) 0x46f6 VPALIGNR	$0x8,%XMM4,%XMM5,%XMM2

    (94) 0x46fc VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

    (94) 0x4703 VPSRLQ	$0x1,%XMM3,%XMM2

    (94) 0x4708 VPXOR	-0x2b8(%RSP,%RCX,8),%XMM2,%XMM2

    (94) 0x4711 VPAND	%XMM6,%XMM9,%XMM3

    (94) 0x4715 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (94) 0x471b VPTESTMQ	%XMM10,%XMM6,%K1

    (94) 0x4721 VMOVDQU	%XMM2,0x460(%RSP,%RCX,8)

    (94) 0x472a VPALIGNR	$0x8,%XMM5,%XMM6,%XMM2

    (94) 0x4730 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

    (94) 0x4737 VPSRLQ	$0x1,%XMM3,%XMM2

    (94) 0x473c VPXOR	-0x2a8(%RSP,%RCX,8),%XMM2,%XMM2

    (94) 0x4745 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (94) 0x474b VMOVDQU	%XMM2,0x470(%RSP,%RCX,8)

    (94) 0x4754 VMOVDQU	0x488(%RSP,%RCX,8),%XMM3

    (94) 0x475d VPALIGNR	$0x8,%XMM6,%XMM3,%XMM2

    (94) 0x4763 VPAND	%XMM3,%XMM9,%XMM4

    (94) 0x4767 VPTESTMQ	%XMM10,%XMM3,%K1

    (94) 0x476d VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM4

    (94) 0x4774 VPSRLQ	$0x1,%XMM4,%XMM2

    (94) 0x4779 VPXOR	-0x298(%RSP,%RCX,8),%XMM2,%XMM2

    (94) 0x4782 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (94) 0x4788 VMOVDQU	%XMM2,0x480(%RSP,%RCX,8)

    (94) 0x4791 VMOVDQU	0x498(%RSP,%RCX,8),%XMM2

    (94) 0x479a VPALIGNR	$0x8,%XMM3,%XMM2,%XMM3

    (94) 0x47a0 VPAND	%XMM2,%XMM9,%XMM4

    (94) 0x47a4 VPTESTMQ	%XMM10,%XMM2,%K1

    (94) 0x47aa VPTERNLOGQ	$-0x8,%XMM8,%XMM3,%XMM4

    (94) 0x47b1 VPSRLQ	$0x1,%XMM4,%XMM3

    (94) 0x47b6 VPXOR	-0x288(%RSP,%RCX,8),%XMM3,%XMM3

    (94) 0x47bf VPXORQ	%XMM11,%XMM3,%XMM3{%K1}

    (94) 0x47c5 VMOVDQU	%XMM3,0x490(%RSP,%RCX,8)

    (94) 0x47ce ADD	$0xc,%RCX

    (94) 0x47d2 CMP	$0x27a,%RCX

    (94) 0x47d9 JNE	4660

  (92) 0x47df MOV	0x1810(%RSP),%RCX

  (92) 0x47e7 MOV	0x498(%RSP),%RBX

  (92) 0x47ef XOR	%R13D,%R13D

  (92) 0x47f2 MOV	%EBX,%EDX

  (92) 0x47f4 AND	%R14,%RCX

  (92) 0x47f7 AND	$0x7ffffffe,%EDX

  (92) 0x47fd OR	%RCX,%RDX

  (92) 0x4800 MOV	%EBX,%ECX

  (92) 0x4802 AND	$0x1,%ECX

  (92) 0x4805 SHR	$0x1,%RDX

  (92) 0x4808 XOR	0x10f8(%RSP),%RDX

  (92) 0x4810 NEG	%ECX

  (92) 0x4812 AND	%R12D,%ECX

  (92) 0x4815 XOR	%RDX,%RCX

  (92) 0x4818 MOV	%RCX,0x1810(%RSP)

  (92) 0x4820 JMP	43c0

0x4830 VDIVSS	%XMM1,%XMM0,%XMM0

0x4834 VMOVSS	0x37d8(%RIP),%XMM2

0x483c VUCOMISS	%XMM2,%XMM0

0x4840 JAE	4d53

0x4846 MOV	0x168(%RSP),%RAX

0x484e VMOVAPS	%XMM2,%XMM1

0x4852 VMOVSS	%XMM0,(%RAX,%R9,4)

0x4858 VXORPS	%XMM0,%XMM0,%XMM0

0x485c MOV	%R8,%RAX

0x485f JMP	48d5

  (89) 0x4870 MOV	%R13,%RCX

  (89) 0x4873 INC	%R13

  (89) 0x4876 MOV	$0x200b,%EDX

  (89) 0x487b MOV	%R13,0x1818(%RSP)

  (89) 0x4883 MOV	0x498(%RSP,%RCX,8),%RCX

  (89) 0x488b BEXTR	%RDX,%RCX,%RDX

  (89) 0x4890 XOR	%RCX,%RDX

  (89) 0x4893 MOV	%EDX,%ECX

  (89) 0x4895 SAL	$0x7,%ECX

  (89) 0x4898 AND	$-0x62d3a980,%ECX

  (89) 0x489e XOR	%RDX,%RCX

  (89) 0x48a1 MOV	%ECX,%EDX

  (89) 0x48a3 SAL	$0xf,%EDX

  (89) 0x48a6 AND	$-0x103a0000,%EDX

  (89) 0x48ac XOR	%RCX,%RDX

  (89) 0x48af MOV	%RDX,%RCX

  (89) 0x48b2 SHR	$0x12,%RCX

  (89) 0x48b6 XOR	%RDX,%RCX

  (89) 0x48b9 DEC	%RAX

  (89) 0x48bc VCVTUSI2SS	%RCX,%XMM15,%XMM2

  (89) 0x48c2 VFMADD231SS	%XMM2,%XMM1,%XMM0

  (89) 0x48c7 VMULSS	0x3739(%RIP),%XMM1,%XMM1

  (89) 0x48cf JE	4ce0

  (89) 0x48d5 CMP	$0x270,%R13

  (89) 0x48dc JB	4870

  (89) 0x48de VPBROADCASTQ	0x3759(%RIP),%YMM14

  (89) 0x48e7 VPBROADCASTQ	0x3758(%RIP),%YMM15

  (89) 0x48f0 VPBROADCASTQ	0x3756(%RIP),%YMM16

  (89) 0x48fa VPBROADCASTQ	0x3754(%RIP),%YMM17

  (89) 0x4904 VPBROADCASTQ	%RBX,%YMM2

  (89) 0x490a XOR	%ECX,%ECX

  (89) 0x490c NOPL	(%RAX)

    (90) 0x4910 VMOVDQU	0x4a0(%RSP,%RCX,8),%YMM3

    (90) 0x4919 VMOVDQU	0x4c0(%RSP,%RCX,8),%YMM4

    (90) 0x4922 VMOVDQU	0x4e0(%RSP,%RCX,8),%YMM5

    (90) 0x492b VALIGNQ	$0x3,%YMM2,%YMM3,%YMM6

    (90) 0x4932 VMOVDQU	0x500(%RSP,%RCX,8),%YMM2

    (90) 0x493b VALIGNQ	$0x3,%YMM3,%YMM4,%YMM7

    (90) 0x4942 VALIGNQ	$0x3,%YMM4,%YMM5,%YMM8

    (90) 0x4949 VPAND	%YMM3,%YMM15,%YMM10

    (90) 0x494d VPAND	%YMM4,%YMM15,%YMM11

    (90) 0x4951 VPAND	%YMM5,%YMM15,%YMM12

    (90) 0x4955 VPTESTMQ	%YMM16,%YMM3,%K1

    (90) 0x495b VPTESTMQ	%YMM16,%YMM4,%K2

    (90) 0x4961 VPTESTMQ	%YMM16,%YMM5,%K3

    (90) 0x4967 VPTERNLOGQ	$-0x8,%YMM14,%YMM6,%YMM10

    (90) 0x496e VPTERNLOGQ	$-0x8,%YMM14,%YMM7,%YMM11

    (90) 0x4975 VPTERNLOGQ	$-0x8,%YMM14,%YMM8,%YMM12

    (90) 0x497c VPSRLQ	$0x1,%YMM10,%YMM6

    (90) 0x4982 VPSRLQ	$0x1,%YMM11,%YMM7

    (90) 0x4988 VPSRLQ	$0x1,%YMM12,%YMM8

    (90) 0x498e VPXOR	0x1100(%RSP,%RCX,8),%YMM6,%YMM6

    (90) 0x4997 VPXOR	0x1120(%RSP,%RCX,8),%YMM7,%YMM7

    (90) 0x49a0 VPXOR	0x1140(%RSP,%RCX,8),%YMM8,%YMM8

    (90) 0x49a9 VALIGNQ	$0x3,%YMM5,%YMM2,%YMM9

    (90) 0x49b0 VPAND	%YMM2,%YMM15,%YMM13

    (90) 0x49b4 VPTESTMQ	%YMM16,%YMM2,%K4

    (90) 0x49ba VPTERNLOGQ	$-0x8,%YMM14,%YMM9,%YMM13

    (90) 0x49c1 VPSRLQ	$0x1,%YMM13,%YMM9

    (90) 0x49c7 VPXOR	0x1160(%RSP,%RCX,8),%YMM9,%YMM9

    (90) 0x49d0 VPXORQ	%YMM17,%YMM6,%YMM6{%K1}

    (90) 0x49d6 VPXORQ	%YMM17,%YMM7,%YMM7{%K2}

    (90) 0x49dc VPXORQ	%YMM17,%YMM8,%YMM8{%K3}

    (90) 0x49e2 VMOVDQU	%YMM6,0x498(%RSP,%RCX,8)

    (90) 0x49eb VMOVDQU	%YMM7,0x4b8(%RSP,%RCX,8)

    (90) 0x49f4 VMOVDQU	%YMM8,0x4d8(%RSP,%RCX,8)

    (90) 0x49fd VPXORQ	%YMM17,%YMM9,%YMM9{%K4}

    (90) 0x4a03 VMOVDQU	%YMM9,0x4f8(%RSP,%RCX,8)

    (90) 0x4a0c ADD	$0x10,%RCX

    (90) 0x4a10 CMP	$0xe0,%RCX

    (90) 0x4a17 JNE	4910

  (89) 0x4a1d MOV	0xba0(%RSP),%RDX

  (89) 0x4a25 VEXTRACTI128	$0x1,%YMM2,%XMM2

  (89) 0x4a2b MOV	0xba8(%RSP),%RCX

  (89) 0x4a33 VPBROADCASTQ	0x3604(%RIP),%XMM8

  (89) 0x4a3c VPBROADCASTQ	0x3603(%RIP),%XMM9

  (89) 0x4a45 VPBROADCASTQ	0x3602(%RIP),%XMM10

  (89) 0x4a4e VPBROADCASTQ	0x3601(%RIP),%XMM11

  (89) 0x4a57 VPEXTRQ	$0x1,%XMM2,%RSI

  (89) 0x4a5d AND	$-0x80000000,%RSI

  (89) 0x4a64 MOV	%EDX,%EDI

  (89) 0x4a66 AND	$0x7ffffffe,%EDI

  (89) 0x4a6c OR	%RSI,%RDI

  (89) 0x4a6f MOV	%EDX,%ESI

  (89) 0x4a71 AND	$0x1,%ESI

  (89) 0x4a74 AND	$-0x80000000,%RDX

  (89) 0x4a7b SHR	$0x1,%RDI

  (89) 0x4a7e XOR	0x1800(%RSP),%RDI

  (89) 0x4a86 NEG	%ESI

  (89) 0x4a88 AND	%R12D,%ESI

  (89) 0x4a8b XOR	%RDI,%RSI

  (89) 0x4a8e MOV	%RSI,0xb98(%RSP)

  (89) 0x4a96 MOV	%ECX,%ESI

  (89) 0x4a98 AND	$0x7ffffffe,%ESI

  (89) 0x4a9e OR	%RDX,%RSI

  (89) 0x4aa1 MOV	%ECX,%EDX

  (89) 0x4aa3 AND	$0x1,%EDX

  (89) 0x4aa6 AND	$-0x80000000,%RCX

  (89) 0x4aad SHR	$0x1,%RSI

  (89) 0x4ab0 XOR	0x1808(%RSP),%RSI

  (89) 0x4ab8 NEG	%EDX

  (89) 0x4aba AND	%R12D,%EDX

  (89) 0x4abd XOR	%RSI,%RDX

  (89) 0x4ac0 MOV	%RDX,0xba0(%RSP)

  (89) 0x4ac8 MOV	0xbb0(%RSP),%RDX

  (89) 0x4ad0 MOV	%EDX,%ESI

  (89) 0x4ad2 VPBROADCASTQ	%RDX,%XMM2

  (89) 0x4ad8 AND	$0x7ffffffe,%EDX

  (89) 0x4ade AND	$0x1,%ESI

  (89) 0x4ae1 OR	%RCX,%RDX

  (89) 0x4ae4 NEG	%ESI

  (89) 0x4ae6 MOV	$0xee,%ECX

  (89) 0x4aeb SHR	$0x1,%RDX

  (89) 0x4aee XOR	0x1810(%RSP),%RDX

  (89) 0x4af6 AND	%R12D,%ESI

  (89) 0x4af9 XOR	%RDX,%RSI

  (89) 0x4afc MOV	%RSI,0xba8(%RSP)

  (89) 0x4b04 NOPW	%CS:(%RAX,%RAX,1)

    (91) 0x4b10 VMOVDQU	0x448(%RSP,%RCX,8),%XMM3

    (91) 0x4b19 VMOVDQU	0x458(%RSP,%RCX,8),%XMM4

    (91) 0x4b22 VMOVDQU	0x468(%RSP,%RCX,8),%XMM5

    (91) 0x4b2b VMOVDQU	0x478(%RSP,%RCX,8),%XMM6

    (91) 0x4b34 VPALIGNR	$0x8,%XMM2,%XMM3,%XMM2

    (91) 0x4b3a VPAND	%XMM3,%XMM9,%XMM7

    (91) 0x4b3e VPTESTMQ	%XMM10,%XMM3,%K1

    (91) 0x4b44 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM7

    (91) 0x4b4b VPSRLQ	$0x1,%XMM7,%XMM2

    (91) 0x4b50 VPXOR	-0x2d8(%RSP,%RCX,8),%XMM2,%XMM2

    (91) 0x4b59 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (91) 0x4b5f VPTESTMQ	%XMM10,%XMM4,%K1

    (91) 0x4b65 VMOVDQU	%XMM2,0x440(%RSP,%RCX,8)

    (91) 0x4b6e VPALIGNR	$0x8,%XMM3,%XMM4,%XMM2

    (91) 0x4b74 VPAND	%XMM4,%XMM9,%XMM3

    (91) 0x4b78 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

    (91) 0x4b7f VPSRLQ	$0x1,%XMM3,%XMM2

    (91) 0x4b84 VPXOR	-0x2c8(%RSP,%RCX,8),%XMM2,%XMM2

    (91) 0x4b8d VPAND	%XMM5,%XMM9,%XMM3

    (91) 0x4b91 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (91) 0x4b97 VPTESTMQ	%XMM10,%XMM5,%K1

    (91) 0x4b9d VMOVDQU	%XMM2,0x450(%RSP,%RCX,8)

    (91) 0x4ba6 VPALIGNR	$0x8,%XMM4,%XMM5,%XMM2

    (91) 0x4bac VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

    (91) 0x4bb3 VPSRLQ	$0x1,%XMM3,%XMM2

    (91) 0x4bb8 VPXOR	-0x2b8(%RSP,%RCX,8),%XMM2,%XMM2

    (91) 0x4bc1 VPAND	%XMM6,%XMM9,%XMM3

    (91) 0x4bc5 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (91) 0x4bcb VPTESTMQ	%XMM10,%XMM6,%K1

    (91) 0x4bd1 VMOVDQU	%XMM2,0x460(%RSP,%RCX,8)

    (91) 0x4bda VPALIGNR	$0x8,%XMM5,%XMM6,%XMM2

    (91) 0x4be0 VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM3

    (91) 0x4be7 VPSRLQ	$0x1,%XMM3,%XMM2

    (91) 0x4bec VPXOR	-0x2a8(%RSP,%RCX,8),%XMM2,%XMM2

    (91) 0x4bf5 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (91) 0x4bfb VMOVDQU	%XMM2,0x470(%RSP,%RCX,8)

    (91) 0x4c04 VMOVDQU	0x488(%RSP,%RCX,8),%XMM3

    (91) 0x4c0d VPALIGNR	$0x8,%XMM6,%XMM3,%XMM2

    (91) 0x4c13 VPAND	%XMM3,%XMM9,%XMM4

    (91) 0x4c17 VPTESTMQ	%XMM10,%XMM3,%K1

    (91) 0x4c1d VPTERNLOGQ	$-0x8,%XMM8,%XMM2,%XMM4

    (91) 0x4c24 VPSRLQ	$0x1,%XMM4,%XMM2

    (91) 0x4c29 VPXOR	-0x298(%RSP,%RCX,8),%XMM2,%XMM2

    (91) 0x4c32 VPXORQ	%XMM11,%XMM2,%XMM2{%K1}

    (91) 0x4c38 VMOVDQU	%XMM2,0x480(%RSP,%RCX,8)

    (91) 0x4c41 VMOVDQU	0x498(%RSP,%RCX,8),%XMM2

    (91) 0x4c4a VPALIGNR	$0x8,%XMM3,%XMM2,%XMM3

    (91) 0x4c50 VPAND	%XMM2,%XMM9,%XMM4

    (91) 0x4c54 VPTESTMQ	%XMM10,%XMM2,%K1

    (91) 0x4c5a VPTERNLOGQ	$-0x8,%XMM8,%XMM3,%XMM4

    (91) 0x4c61 VPSRLQ	$0x1,%XMM4,%XMM3

    (91) 0x4c66 VPXOR	-0x288(%RSP,%RCX,8),%XMM3,%XMM3

    (91) 0x4c6f VPXORQ	%XMM11,%XMM3,%XMM3{%K1}

    (91) 0x4c75 VMOVDQU	%XMM3,0x490(%RSP,%RCX,8)

    (91) 0x4c7e ADD	$0xc,%RCX

    (91) 0x4c82 CMP	$0x27a,%RCX

    (91) 0x4c89 JNE	4b10

  (89) 0x4c8f MOV	0x1810(%RSP),%RCX

  (89) 0x4c97 MOV	0x498(%RSP),%RBX

  (89) 0x4c9f XOR	%R13D,%R13D

  (89) 0x4ca2 MOV	%EBX,%EDX

  (89) 0x4ca4 AND	%R14,%RCX

  (89) 0x4ca7 AND	$0x7ffffffe,%EDX

  (89) 0x4cad OR	%RCX,%RDX

  (89) 0x4cb0 MOV	%EBX,%ECX

  (89) 0x4cb2 AND	$0x1,%ECX

  (89) 0x4cb5 SHR	$0x1,%RDX

  (89) 0x4cb8 XOR	0x10f8(%RSP),%RDX

  (89) 0x4cc0 NEG	%ECX

  (89) 0x4cc2 AND	%R12D,%ECX

  (89) 0x4cc5 XOR	%RDX,%RCX

  (89) 0x4cc8 MOV	%RCX,0x1810(%RSP)

  (89) 0x4cd0 JMP	4870

0x4ce0 VDIVSS	%XMM1,%XMM0,%XMM0

0x4ce4 VUCOMISS	0x3328(%RIP),%XMM0

0x4cec JAE	4d90

0x4cf2 MOV	0x198(%RSP),%RAX

0x4cfa VMOVSS	%XMM0,(%RAX,%R9,4)

0x4d00 INC	%R9

0x4d03 CMP	0x3d0(%RSP),%R9

0x4d0b JNE	3f00

0x4d16 VXORPS	%XMM1,%XMM1,%XMM1

0x4d1a VMOVAPS	%XMM2,%XMM0

0x4d1e MOV	%R8,0x140(%RSP)

0x4d26 MOV	%R9,0x120(%RSP)

0x4d2e VZEROUPPER

0x4d31 CALL	10a0 <nextafterf@plt>

0x4d36 VMOVSS	0x32d6(%RIP),%XMM2

0x4d3e MOV	0x120(%RSP),%R9

0x4d46 MOV	0x140(%RSP),%R8

0x4d4e JMP	43a6

0x4d53 VXORPS	%XMM1,%XMM1,%XMM1

0x4d57 VMOVAPS	%XMM2,%XMM0

0x4d5b MOV	%R8,0x140(%RSP)

0x4d63 MOV	%R9,0x120(%RSP)

0x4d6b VZEROUPPER

0x4d6e CALL	10a0 <nextafterf@plt>

0x4d73 VMOVSS	0x3299(%RIP),%XMM2

0x4d7b MOV	0x120(%RSP),%R9

0x4d83 MOV	0x140(%RSP),%R8

0x4d8b JMP	4846

0x4d90 VMOVSS	0x327c(%RIP),%XMM0

0x4d98 VXORPS	%XMM1,%XMM1,%XMM1

0x4d9c MOV	%R8,0x140(%RSP)

0x4da4 MOV	%R9,0x120(%RSP)

0x4dac VZEROUPPER

0x4daf CALL	10a0 <nextafterf@plt>

0x4db4 MOV	0x120(%RSP),%R9

0x4dbc MOV	0x140(%RSP),%R8

0x4dc4 JMP	4cf2

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath: 1661 - 1661

--------------------------------------------------------------------------------

1661:   { return __builtin_nextafterf(__x, __y); }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 401 - 3370

--------------------------------------------------------------------------------

401:       for (size_t __k = 0; __k < (__n - __m); ++__k)

402:         {

403: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

404: 			   | (_M_x[__k + 1] & __lower_mask));

405: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

406: 		       ^ ((__y & 0x01) ? __a : 0));

407:         }

408:

409:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

410: 	{

411: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

412: 			   | (_M_x[__k + 1] & __lower_mask));

413: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

414: 		       ^ ((__y & 0x01) ? __a : 0));

415: 	}

416:

417:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

418: 		       | (_M_x[0] & __lower_mask));

419:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

420: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

455:       if (_M_p >= state_size)

456: 	_M_gen_rand();

457:

458:       // Calculate o(x(i)).

459:       result_type __z = _M_x[_M_p++];

460:       __z ^= (__z >> __u) & __d;

461:       __z ^= (__z << __s) & __b;

462:       __z ^= (__z << __t) & __c;

463:       __z ^= (__z >> __l);

[...]

3364:       for (size_t __k = __m; __k != 0; --__k)

3365: 	{

3366: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3367: 	  __tmp *= __r;

3368: 	}

3369:       __ret = __sum / __tmp;

3370:       if (__builtin_expect(__ret >= _RealType(1), 0))

/home/eoseret/llm-attention/attention_v2.cpp: 164 - 167

--------------------------------------------------------------------------------

164:       for (size_t i = 0; i < elemsW; ++i) {

165:          h_WQ[i] = dist(rng);

166:          h_WK[i] = dist(rng);

167:          h_WV[i] = dist(rng);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.10
CQA speedup if FP arith vectorized	1.70
CQA speedup if fully vectorized	12.31
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	micro-operation queue,
Function	main
Source	cmath:1661-1661,random.tcc:3369-3370,attention_v2.cpp:164-167
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.25
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	4.84
CQA cycles if fully vectorized	0.67
Front-end cycles	8.25
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	3.33
P4 cycles	3.33
P5 cycles	3.33
P6 cycles	6.25
P7 cycles	6.25
P8 cycles	6.25
P9 cycles	6.25
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	3.00
P15 cycles	3.00
DIV/SQRT cycles	7.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	66.00
Nb loads	16.00
Nb stores	9.00
Nb stack references	5.00
FLOP/cycle	0.36
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.39
Bytes prefetched	0.00
Bytes loaded	100.00
Bytes stored	60.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	35.14
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	81.25
Vector-efficiency ratio all	14.36
Vector-efficiency ratio load	8.13
Vector-efficiency ratio store	10.42
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	21.48

Metric	Value
CQA speedup if no scalar integer	1.10
CQA speedup if FP arith vectorized	1.70
CQA speedup if fully vectorized	12.31
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	micro-operation queue,
Function	main
Source	cmath:1661-1661,random.tcc:3369-3370,attention_v2.cpp:164-167
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.25
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	4.84
CQA cycles if fully vectorized	0.67
Front-end cycles	8.25
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	3.33
P4 cycles	3.33
P5 cycles	3.33
P6 cycles	6.25
P7 cycles	6.25
P8 cycles	6.25
P9 cycles	6.25
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	3.00
P15 cycles	3.00
DIV/SQRT cycles	7.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	66.00
Nb loads	16.00
Nb stores	9.00
Nb stack references	5.00
FLOP/cycle	0.36
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.39
Bytes prefetched	0.00
Bytes loaded	100.00
Bytes stored	60.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	35.14
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	81.25
Vector-efficiency ratio all	14.36
Vector-efficiency ratio load	8.13
Vector-efficiency ratio store	10.42
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	21.48

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:164-167
Module	attention-clang-znver5-256

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3364-3370
/home/eoseret/llm-attention/attention_v2.cpp:164-167

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 64 paths individually, rerun with max-paths=64
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 64 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.25 to 7.50 cycles (1.10x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 8.25 to 0.67 cycles (12.31x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

nextafterf@plt: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISS: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: divide

The binary loop is loading 100 bytes (25 single precision FP elements). The binary loop is storing 60 bytes (15 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	60
nb uops	66
loop length	335
used x86 registers	5
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.25 cycles
front end	8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	3.33	3.33	3.33	6.25	6.25	6.25	6.25	1.50	1.50	1.50	1.50	3.00	3.00
cycles	0.67	0.67	0.67	3.33	3.33	3.33	6.25	6.25	6.25	6.25	1.50	1.50	1.50	1.50	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

7.50

Cycles summary

Front-end	8.25
Dispatch	6.25
DIV/SQRT	7.50
Overall L1	8.25

Vectorization ratios

INT

all	25%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	40%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	76%

INT+FP

all	35%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	81%

Vector efficiency ratios

INT

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	13%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	20%

INT+FP

all	14%
load	8%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.25 cycles. At this rate:

4% of peak load performance is reached (12.12 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 3f00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVSS 0x410c(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 3f85 <main+0x11b5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
VMOVSS 0x3c78(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VUCOMISS %XMM2,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	0.50	scal (6.3%)
JAE 4d16 <main+0x1f46>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VMOVSS %XMM0,(%R15,%R9,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVAPS %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 4425 <main+0x1655>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
VMOVSS 0x37d8(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VUCOMISS %XMM2,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	0.50	scal (6.3%)
JAE 4d53 <main+0x1f83>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x168(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVAPS %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 48d5 <main+0x1b05>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
VUCOMISS 0x3328(%RIP),%XMM0	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	7	0.50	scal (6.3%)
JAE 4d90 <main+0x1fc0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x198(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x3d0(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JNE 3f00 <main+0x1130>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 10a0 <nextafterf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVSS 0x32d6(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV 0x120(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x140(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JMP 43a6 <main+0x15d6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 10a0 <nextafterf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVSS 0x3299(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV 0x120(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x140(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JMP 4846 <main+0x1a76>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VMOVSS 0x327c(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 10a0 <nextafterf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV 0x120(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x140(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JMP 4cf2 <main+0x1f22>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:164-167
Module	attention-clang-znver5-256

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3364-3370
/home/eoseret/llm-attention/attention_v2.cpp:164-167

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 64 paths individually, rerun with max-paths=64
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.25 to 7.50 cycles (1.10x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

nextafterf@plt: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISS: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: divide

The binary loop is loading 100 bytes (25 single precision FP elements). The binary loop is storing 60 bytes (15 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	60
nb uops	66
loop length	335
used x86 registers	5
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.25 cycles
front end	8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	3.33	3.33	3.33	6.25	6.25	6.25	6.25	1.50	1.50	1.50	1.50	3.00	3.00
cycles	0.67	0.67	0.67	3.33	3.33	3.33	6.25	6.25	6.25	6.25	1.50	1.50	1.50	1.50	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

7.50

Cycles summary

Front-end	8.25
Dispatch	6.25
DIV/SQRT	7.50
Overall L1	8.25

Vectorization ratios

INT

all	25%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	40%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	76%

INT+FP

all	35%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	81%

Vector efficiency ratios

INT

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	13%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	20%

INT+FP

all	14%
load	8%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.25 cycles. At this rate:

4% of peak load performance is reached (12.12 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 3f00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VMOVSS 0x410c(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 3f85 <main+0x11b5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
VMOVSS 0x3c78(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VUCOMISS %XMM2,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	0.50	scal (6.3%)
JAE 4d16 <main+0x1f46>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VMOVSS %XMM0,(%R15,%R9,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VMOVAPS %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 4425 <main+0x1655>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
VMOVSS 0x37d8(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VUCOMISS %XMM2,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	0.50	scal (6.3%)
JAE 4d53 <main+0x1f83>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x168(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVAPS %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 48d5 <main+0x1b05>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
VUCOMISS 0x3328(%RIP),%XMM0	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	7	0.50	scal (6.3%)
JAE 4d90 <main+0x1fc0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x198(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x3d0(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JNE 3f00 <main+0x1130>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 10a0 <nextafterf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVSS 0x32d6(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV 0x120(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x140(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JMP 43a6 <main+0x15d6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 10a0 <nextafterf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVSS 0x3299(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
MOV 0x120(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x140(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JMP 4846 <main+0x1a76>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
VMOVSS 0x327c(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (6.3%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 10a0 <nextafterf@plt>	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV 0x120(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x140(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JMP 4cf2 <main+0x1f22>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code