| Loop Id: 64 | Module: attention-clang-znver5-256 | Source: attention_v2.cpp:30-31 | Coverage: 21.08% |
|---|
| Loop Id: 64 | Module: attention-clang-znver5-256 | Source: attention_v2.cpp:30-31 | Coverage: 21.08% |
|---|
0x5b90 LEA (%RAX,%R8,1),%R9D |
0x5b94 LEA 0x6(%RAX,%R8,1),%R10D |
0x5b99 VMOVSS (%R11,%R9,4),%XMM1 [3] |
0x5b9f LEA (%RSI,%RDI,1),%R9D |
0x5ba3 VMOVSS (%R15,%R9,4),%XMM2 [2] |
0x5ba9 LEA 0x1(%RAX,%R8,1),%R9D |
0x5bae VMOVSS (%R11,%R10,4),%XMM13 [3] |
0x5bb4 VMOVSS (%R11,%R9,4),%XMM3 [3] |
0x5bba LEA (%RDX,%RDI,1),%R9D |
0x5bbe VMOVSS (%R15,%R9,4),%XMM4 [2] |
0x5bc4 LEA 0x2(%RAX,%R8,1),%R9D |
0x5bc9 VMOVSS (%R11,%R9,4),%XMM5 [3] |
0x5bcf LEA (%RCX,%RDI,1),%R9D |
0x5bd3 VMOVSS (%R15,%R9,4),%XMM6 [2] |
0x5bd9 LEA 0x3(%RAX,%R8,1),%R9D |
0x5bde VCVTSS2SD %XMM1,%XMM1,%XMM1 |
0x5be2 VCVTSS2SD %XMM2,%XMM2,%XMM2 |
0x5be6 VMOVSS (%R11,%R9,4),%XMM7 [3] |
0x5bec LEA (%R13,%RDI,1),%R9D |
0x5bf1 VMOVSS (%R15,%R9,4),%XMM8 [2] |
0x5bf7 LEA 0x4(%RAX,%R8,1),%R9D |
0x5bfc VFMADD213SD %XMM0,%XMM1,%XMM2 |
0x5c01 VCVTSS2SD %XMM3,%XMM3,%XMM0 |
0x5c05 VMOVSS (%R11,%R9,4),%XMM9 [3] |
0x5c0b LEA (%R12,%RDI,1),%R9D |
0x5c0f VMOVSS (%R15,%R9,4),%XMM10 [2] |
0x5c15 LEA 0x5(%RAX,%R8,1),%R9D |
0x5c1a VCVTSS2SD %XMM4,%XMM4,%XMM1 |
0x5c1e VMOVSS (%R11,%R9,4),%XMM11 [3] |
0x5c24 MOV 0xa0(%RSP),%R9 [1] |
0x5c2c VFMADD213SD %XMM2,%XMM0,%XMM1 |
0x5c31 VCVTSS2SD %XMM5,%XMM5,%XMM0 |
0x5c35 LEA (%R9,%RDI,1),%R9D |
0x5c39 VCVTSS2SD %XMM6,%XMM6,%XMM2 |
0x5c3d VMOVSS (%R15,%R9,4),%XMM12 [2] |
0x5c43 MOV 0x120(%RSP),%R9 [1] |
0x5c4b VFMADD213SD %XMM1,%XMM0,%XMM2 |
0x5c50 VCVTSS2SD %XMM7,%XMM7,%XMM0 |
0x5c54 ADD %EDI,%R9D |
0x5c57 VCVTSS2SD %XMM8,%XMM8,%XMM1 |
0x5c5c VMOVSS (%R15,%R9,4),%XMM14 [2] |
0x5c62 LEA 0x7(%RAX,%R8,1),%R9D |
0x5c67 ADD $0x8,%R8 |
0x5c6b VMOVSS (%R11,%R9,4),%XMM15 [3] |
0x5c71 MOV 0x140(%RSP),%R9 [1] |
0x5c79 VFMADD213SD %XMM2,%XMM0,%XMM1 |
0x5c7e VCVTSS2SD %XMM9,%XMM9,%XMM0 |
0x5c83 VCVTSS2SD %XMM10,%XMM10,%XMM2 |
0x5c88 ADD %EDI,%R9D |
0x5c8b ADD %RBX,%RDI |
0x5c8e VMOVSS (%R15,%R9,4),%XMM16 [2] |
0x5c95 VFMADD213SD %XMM1,%XMM0,%XMM2 |
0x5c9a VCVTSS2SD %XMM11,%XMM11,%XMM0 |
0x5c9f VCVTSS2SD %XMM12,%XMM12,%XMM1 |
0x5ca4 VFMADD213SD %XMM2,%XMM0,%XMM1 |
0x5ca9 VCVTSS2SD %XMM13,%XMM13,%XMM0 |
0x5cae VCVTSS2SD %XMM14,%XMM14,%XMM2 |
0x5cb3 VFMADD213SD %XMM1,%XMM0,%XMM2 |
0x5cb8 VCVTSS2SD %XMM15,%XMM15,%XMM1 |
0x5cbd VCVTSS2SD %XMM16,%XMM16,%XMM0 |
0x5cc3 VFMADD213SD %XMM2,%XMM1,%XMM0 |
0x5cc8 CMP %R8,%R14 |
0x5ccb JNE 5b90 |
/home/eoseret/llm-attention/attention_v2.cpp: 30 - 31 |
-------------------------------------------------------------------------------- |
30: for (unsigned int k = 0; k < K; ++k) { //vectorized |
31: sum += (double)A[i * K + k] * (double)B[k * N + j]; |
| Coverage (%) | Name | Source Location | Module |
|---|
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.76 |
| CQA speedup if fully vectorized | 14.20 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 3.71 |
| Bottlenecks | |
| Function | main |
| Source | attention_v2.cpp:30-31 |
| Source loop unroll info | multi-versionned |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 32.00 |
| CQA cycles if no scalar integer | 32.00 |
| CQA cycles if FP arith vectorized | 18.22 |
| CQA cycles if fully vectorized | 2.25 |
| Front-end cycles | 8.63 |
| P0 cycles | 3.00 |
| P1 cycles | 3.00 |
| P2 cycles | 3.50 |
| P3 cycles | 3.50 |
| P4 cycles | 3.00 |
| P5 cycles | 3.00 |
| P6 cycles | 6.50 |
| P7 cycles | 6.50 |
| P8 cycles | 6.50 |
| P9 cycles | 6.50 |
| P10 cycles | 4.00 |
| P11 cycles | 4.00 |
| P12 cycles | 8.00 |
| P13 cycles | 8.00 |
| P14 cycles | 0.00 |
| P15 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 32 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 63.00 |
| Nb uops | 69.00 |
| Nb loads | 19.00 |
| Nb stores | 0.00 |
| Nb stack references | 3.00 |
| FLOP/cycle | 0.50 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 8.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 2.75 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 88.00 |
| Bytes stored | 0.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 1.00 |
| Stride unknown | 1.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 7.50 |
| Vector-efficiency ratio load | 6.25 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 6.25 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.76 |
| CQA speedup if fully vectorized | 14.20 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 3.71 |
| Bottlenecks | |
| Function | main |
| Source | attention_v2.cpp:30-31 |
| Source loop unroll info | multi-versionned |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 32.00 |
| CQA cycles if no scalar integer | 32.00 |
| CQA cycles if FP arith vectorized | 18.22 |
| CQA cycles if fully vectorized | 2.25 |
| Front-end cycles | 8.63 |
| P0 cycles | 3.00 |
| P1 cycles | 3.00 |
| P2 cycles | 3.50 |
| P3 cycles | 3.50 |
| P4 cycles | 3.00 |
| P5 cycles | 3.00 |
| P6 cycles | 6.50 |
| P7 cycles | 6.50 |
| P8 cycles | 6.50 |
| P9 cycles | 6.50 |
| P10 cycles | 4.00 |
| P11 cycles | 4.00 |
| P12 cycles | 8.00 |
| P13 cycles | 8.00 |
| P14 cycles | 0.00 |
| P15 cycles | 0.00 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 32 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 63.00 |
| Nb uops | 69.00 |
| Nb loads | 19.00 |
| Nb stores | 0.00 |
| Nb stack references | 3.00 |
| FLOP/cycle | 0.50 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 8.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 2.75 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 88.00 |
| Bytes stored | 0.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 1.00 |
| Stride unknown | 1.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 7.50 |
| Vector-efficiency ratio load | 6.25 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 6.25 |
| Path / |
| Function | main |
| Source file and lines | attention_v2.cpp:30-31 |
| Module | attention-clang-znver5-256 |
| nb instructions | 63 |
| nb uops | 69 |
| loop length | 321 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 17 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 3 |
| micro-operation queue | 8.63 cycles |
| front end | 8.63 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 3.00 | 3.00 | 3.50 | 3.50 | 3.00 | 3.00 | 6.50 | 6.50 | 6.50 | 6.50 | 4.00 | 4.00 | 8.00 | 8.00 | 0.00 | 0.00 |
| cycles | 3.00 | 3.00 | 3.50 | 3.50 | 3.00 | 3.00 | 6.50 | 6.50 | 6.50 | 6.50 | 4.00 | 4.00 | 8.00 | 8.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 32.00 |
| Front-end | 8.63 |
| Dispatch | 8.00 |
| Data deps. | 32.00 |
| Overall L1 | 32.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 7% |
| load | 6% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 12% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 6% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LEA (%RAX,%R8,1),%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| LEA 0x6(%RAX,%R8,1),%R10D | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| VMOVSS (%R11,%R9,4),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA (%RSI,%RDI,1),%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSS (%R15,%R9,4),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA 0x1(%RAX,%R8,1),%R9D | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| VMOVSS (%R11,%R10,4),%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VMOVSS (%R11,%R9,4),%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA (%RDX,%RDI,1),%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSS (%R15,%R9,4),%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA 0x2(%RAX,%R8,1),%R9D | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| VMOVSS (%R11,%R9,4),%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA (%RCX,%RDI,1),%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSS (%R15,%R9,4),%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA 0x3(%RAX,%R8,1),%R9D | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| VCVTSS2SD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VCVTSS2SD %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VMOVSS (%R11,%R9,4),%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA (%R13,%RDI,1),%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSS (%R15,%R9,4),%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA 0x4(%RAX,%R8,1),%R9D | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| VFMADD213SD %XMM0,%XMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSS2SD %XMM3,%XMM3,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VMOVSS (%R11,%R9,4),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA (%R12,%RDI,1),%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSS (%R15,%R9,4),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA 0x5(%RAX,%R8,1),%R9D | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| VCVTSS2SD %XMM4,%XMM4,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VMOVSS (%R11,%R9,4),%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| MOV 0xa0(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| VFMADD213SD %XMM2,%XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSS2SD %XMM5,%XMM5,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| LEA (%R9,%RDI,1),%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VCVTSS2SD %XMM6,%XMM6,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VMOVSS (%R15,%R9,4),%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| MOV 0x120(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| VFMADD213SD %XMM1,%XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSS2SD %XMM7,%XMM7,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| ADD %EDI,%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VCVTSS2SD %XMM8,%XMM8,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VMOVSS (%R15,%R9,4),%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA 0x7(%RAX,%R8,1),%R9D | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| ADD $0x8,%R8 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSS (%R11,%R9,4),%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| MOV 0x140(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| VFMADD213SD %XMM2,%XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSS2SD %XMM9,%XMM9,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VCVTSS2SD %XMM10,%XMM10,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| ADD %EDI,%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD %RBX,%RDI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSS (%R15,%R9,4),%XMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VFMADD213SD %XMM1,%XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSS2SD %XMM11,%XMM11,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VCVTSS2SD %XMM12,%XMM12,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VFMADD213SD %XMM2,%XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSS2SD %XMM13,%XMM13,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VCVTSS2SD %XMM14,%XMM14,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VFMADD213SD %XMM1,%XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSS2SD %XMM15,%XMM15,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VCVTSS2SD %XMM16,%XMM16,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VFMADD213SD %XMM2,%XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| CMP %R8,%R14 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| JNE 5b90 <main+0x2dc0> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33-0.50 | N/A |
| Function | main |
| Source file and lines | attention_v2.cpp:30-31 |
| Module | attention-clang-znver5-256 |
| nb instructions | 63 |
| nb uops | 69 |
| loop length | 321 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 17 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 3 |
| micro-operation queue | 8.63 cycles |
| front end | 8.63 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 3.00 | 3.00 | 3.50 | 3.50 | 3.00 | 3.00 | 6.50 | 6.50 | 6.50 | 6.50 | 4.00 | 4.00 | 8.00 | 8.00 | 0.00 | 0.00 |
| cycles | 3.00 | 3.00 | 3.50 | 3.50 | 3.00 | 3.00 | 6.50 | 6.50 | 6.50 | 6.50 | 4.00 | 4.00 | 8.00 | 8.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 32.00 |
| Front-end | 8.63 |
| Dispatch | 8.00 |
| Data deps. | 32.00 |
| Overall L1 | 32.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 7% |
| load | 6% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 12% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 6% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | P15 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LEA (%RAX,%R8,1),%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| LEA 0x6(%RAX,%R8,1),%R10D | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| VMOVSS (%R11,%R9,4),%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA (%RSI,%RDI,1),%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSS (%R15,%R9,4),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA 0x1(%RAX,%R8,1),%R9D | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| VMOVSS (%R11,%R10,4),%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VMOVSS (%R11,%R9,4),%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA (%RDX,%RDI,1),%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSS (%R15,%R9,4),%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA 0x2(%RAX,%R8,1),%R9D | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| VMOVSS (%R11,%R9,4),%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA (%RCX,%RDI,1),%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSS (%R15,%R9,4),%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA 0x3(%RAX,%R8,1),%R9D | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| VCVTSS2SD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VCVTSS2SD %XMM2,%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VMOVSS (%R11,%R9,4),%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA (%R13,%RDI,1),%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSS (%R15,%R9,4),%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA 0x4(%RAX,%R8,1),%R9D | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| VFMADD213SD %XMM0,%XMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSS2SD %XMM3,%XMM3,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VMOVSS (%R11,%R9,4),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA (%R12,%RDI,1),%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSS (%R15,%R9,4),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA 0x5(%RAX,%R8,1),%R9D | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| VCVTSS2SD %XMM4,%XMM4,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VMOVSS (%R11,%R9,4),%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| MOV 0xa0(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| VFMADD213SD %XMM2,%XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSS2SD %XMM5,%XMM5,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| LEA (%R9,%RDI,1),%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VCVTSS2SD %XMM6,%XMM6,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VMOVSS (%R15,%R9,4),%XMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| MOV 0x120(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| VFMADD213SD %XMM1,%XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSS2SD %XMM7,%XMM7,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| ADD %EDI,%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VCVTSS2SD %XMM8,%XMM8,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VMOVSS (%R15,%R9,4),%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA 0x7(%RAX,%R8,1),%R9D | 2 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | N/A |
| ADD $0x8,%R8 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSS (%R11,%R9,4),%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| MOV 0x140(%RSP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 | N/A |
| VFMADD213SD %XMM2,%XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSS2SD %XMM9,%XMM9,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VCVTSS2SD %XMM10,%XMM10,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| ADD %EDI,%R9D | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD %RBX,%RDI | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| VMOVSS (%R15,%R9,4),%XMM16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| VFMADD213SD %XMM1,%XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSS2SD %XMM11,%XMM11,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VCVTSS2SD %XMM12,%XMM12,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VFMADD213SD %XMM2,%XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSS2SD %XMM13,%XMM13,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VCVTSS2SD %XMM14,%XMM14,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VFMADD213SD %XMM1,%XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| VCVTSS2SD %XMM15,%XMM15,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VCVTSS2SD %XMM16,%XMM16,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 | scal (6.3%) |
| VFMADD213SD %XMM2,%XMM1,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (12.5%) |
| CMP %R8,%R14 | 1 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0.17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| JNE 5b90 <main+0x2dc0> | 1 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33-0.50 | N/A |
