OV - attention-clang-znver5-256 - Loop 63 - attention-clang-znver5-256

	Loop Id: 63	Module: attention-clang-znver5-256	Source: attention_v2.cpp:27-33	Coverage: 8.47%

0x5a43 VCVTSD2SS	%XMM0,%XMM0,%XMM0

0x5a47 VDIVSS	0x2d4(%RSP),%XMM0,%XMM0

0x5a50 MOV	0x30(%RSP),%R12

0x5a55 MOV	0x170(%RSP),%RCX

0x5a5d MOV	0x118(%RSP),%RDX

0x5a65 MOV	0x40(%RSP),%R13

0x5a6a ADD	%R12D,%ECX

0x5a6d INC	%R12

0x5a70 VMOVSS	%XMM0,(%RDX,%RCX,4)

0x5a75 MOV	0x58(%RSP),%RDX

0x5a7a CMP	%R13,%R12

0x5a7d JE	59f7

0x5a83 CMPL	$0x4,0x28(%RSP)

0x5a88 VPXOR	%XMM0,%XMM0,%XMM0

0x5a8c MOV	%R12,0x30(%RSP)

0x5a91 JB	5aad

0x5a93 MOV	%R12D,%ECX

0x5a96 ADD	0x98(%RSP),%ECX

0x5a9d SETB	%CL

0x5aa0 OR	0xe0(%RSP),%CL

0x5aa7 JE	5cd6

0x5aad XOR	%ECX,%ECX

0x5aaf MOV	0x38(%RSP),%RDX

0x5ab4 SUB	%ECX,%EDX

0x5ab6 AND	$0x7,%EDX

0x5ab9 JE	5b0c

0x5abb MOV	0x58(%RSP),%R9

0x5ac0 MOV	0x68(%RSP),%R11

0x5ac5 MOV	%RCX,%R8

0x5ac8 MOV	%R9,%RSI

0x5acb IMUL	%RCX,%RSI

0x5acf ADD	0x30(%RSP),%RSI

0x5ad4 NOPW	%CS:(%RAX,%RAX,1)

  (65) 0x5ae0 LEA	(%RAX,%R8,1),%EDI

  (65) 0x5ae4 INC	%R8

  (65) 0x5ae7 VMOVSS	(%R11,%RDI,4),%XMM1

  (65) 0x5aed MOV	%ESI,%EDI

  (65) 0x5aef VMOVSS	(%R15,%RDI,4),%XMM2

  (65) 0x5af5 ADD	%R9,%RSI

  (65) 0x5af8 DEC	%RDX

  (65) 0x5afb VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (65) 0x5aff VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (65) 0x5b03 VFMADD231SD	%XMM2,%XMM1,%XMM0

  (65) 0x5b08 JNE	5ae0

0x5b0a JMP	5b14

0x5b0c MOV	0x68(%RSP),%R11

0x5b11 MOV	%RCX,%R8

0x5b14 MOV	0x28(%RSP),%R14

0x5b19 MOV	0x3c0(%RSP),%RBX

0x5b21 SUB	%R14,%RCX

0x5b24 CMP	$-0x8,%RCX

0x5b28 JA	5a43

0x5b2e MOV	0x58(%RSP),%RDI

0x5b33 LEA	0x7(%R8),%RCX

0x5b37 LEA	0x4(%R8),%R12

0x5b3b LEA	0x3(%R8),%R13

0x5b3f LEA	0x1(%R8),%RDX

0x5b43 IMUL	%RDI,%RCX

0x5b47 MOV	%RDI,%RSI

0x5b4a IMUL	%RDI,%R12

0x5b4e IMUL	%RDI,%R13

0x5b52 IMUL	%RDI,%RDX

0x5b56 IMUL	%R8,%RSI

0x5b5a MOV	%RCX,0x140(%RSP)

0x5b62 LEA	0x6(%R8),%RCX

0x5b66 IMUL	%RDI,%RCX

0x5b6a MOV	%RCX,0x120(%RSP)

0x5b72 LEA	0x5(%R8),%RCX

0x5b76 IMUL	%RDI,%RCX

0x5b7a MOV	%RCX,0xa0(%RSP)

0x5b82 LEA	0x2(%R8),%RCX

0x5b86 IMUL	%RDI,%RCX

0x5b8a MOV	0x30(%RSP),%RDI

0x5b8f NOP

  (64) 0x5b90 LEA	(%RAX,%R8,1),%R9D

  (64) 0x5b94 LEA	0x6(%RAX,%R8,1),%R10D

  (64) 0x5b99 VMOVSS	(%R11,%R9,4),%XMM1

  (64) 0x5b9f LEA	(%RSI,%RDI,1),%R9D

  (64) 0x5ba3 VMOVSS	(%R15,%R9,4),%XMM2

  (64) 0x5ba9 LEA	0x1(%RAX,%R8,1),%R9D

  (64) 0x5bae VMOVSS	(%R11,%R10,4),%XMM13

  (64) 0x5bb4 VMOVSS	(%R11,%R9,4),%XMM3

  (64) 0x5bba LEA	(%RDX,%RDI,1),%R9D

  (64) 0x5bbe VMOVSS	(%R15,%R9,4),%XMM4

  (64) 0x5bc4 LEA	0x2(%RAX,%R8,1),%R9D

  (64) 0x5bc9 VMOVSS	(%R11,%R9,4),%XMM5

  (64) 0x5bcf LEA	(%RCX,%RDI,1),%R9D

  (64) 0x5bd3 VMOVSS	(%R15,%R9,4),%XMM6

  (64) 0x5bd9 LEA	0x3(%RAX,%R8,1),%R9D

  (64) 0x5bde VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (64) 0x5be2 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (64) 0x5be6 VMOVSS	(%R11,%R9,4),%XMM7

  (64) 0x5bec LEA	(%R13,%RDI,1),%R9D

  (64) 0x5bf1 VMOVSS	(%R15,%R9,4),%XMM8

  (64) 0x5bf7 LEA	0x4(%RAX,%R8,1),%R9D

  (64) 0x5bfc VFMADD213SD	%XMM0,%XMM1,%XMM2

  (64) 0x5c01 VCVTSS2SD	%XMM3,%XMM3,%XMM0

  (64) 0x5c05 VMOVSS	(%R11,%R9,4),%XMM9

  (64) 0x5c0b LEA	(%R12,%RDI,1),%R9D

  (64) 0x5c0f VMOVSS	(%R15,%R9,4),%XMM10

  (64) 0x5c15 LEA	0x5(%RAX,%R8,1),%R9D

  (64) 0x5c1a VCVTSS2SD	%XMM4,%XMM4,%XMM1

  (64) 0x5c1e VMOVSS	(%R11,%R9,4),%XMM11

  (64) 0x5c24 MOV	0xa0(%RSP),%R9

  (64) 0x5c2c VFMADD213SD	%XMM2,%XMM0,%XMM1

  (64) 0x5c31 VCVTSS2SD	%XMM5,%XMM5,%XMM0

  (64) 0x5c35 LEA	(%R9,%RDI,1),%R9D

  (64) 0x5c39 VCVTSS2SD	%XMM6,%XMM6,%XMM2

  (64) 0x5c3d VMOVSS	(%R15,%R9,4),%XMM12

  (64) 0x5c43 MOV	0x120(%RSP),%R9

  (64) 0x5c4b VFMADD213SD	%XMM1,%XMM0,%XMM2

  (64) 0x5c50 VCVTSS2SD	%XMM7,%XMM7,%XMM0

  (64) 0x5c54 ADD	%EDI,%R9D

  (64) 0x5c57 VCVTSS2SD	%XMM8,%XMM8,%XMM1

  (64) 0x5c5c VMOVSS	(%R15,%R9,4),%XMM14

  (64) 0x5c62 LEA	0x7(%RAX,%R8,1),%R9D

  (64) 0x5c67 ADD	$0x8,%R8

  (64) 0x5c6b VMOVSS	(%R11,%R9,4),%XMM15

  (64) 0x5c71 MOV	0x140(%RSP),%R9

  (64) 0x5c79 VFMADD213SD	%XMM2,%XMM0,%XMM1

  (64) 0x5c7e VCVTSS2SD	%XMM9,%XMM9,%XMM0

  (64) 0x5c83 VCVTSS2SD	%XMM10,%XMM10,%XMM2

  (64) 0x5c88 ADD	%EDI,%R9D

  (64) 0x5c8b ADD	%RBX,%RDI

  (64) 0x5c8e VMOVSS	(%R15,%R9,4),%XMM16

  (64) 0x5c95 VFMADD213SD	%XMM1,%XMM0,%XMM2

  (64) 0x5c9a VCVTSS2SD	%XMM11,%XMM11,%XMM0

  (64) 0x5c9f VCVTSS2SD	%XMM12,%XMM12,%XMM1

  (64) 0x5ca4 VFMADD213SD	%XMM2,%XMM0,%XMM1

  (64) 0x5ca9 VCVTSS2SD	%XMM13,%XMM13,%XMM0

  (64) 0x5cae VCVTSS2SD	%XMM14,%XMM14,%XMM2

  (64) 0x5cb3 VFMADD213SD	%XMM1,%XMM0,%XMM2

  (64) 0x5cb8 VCVTSS2SD	%XMM15,%XMM15,%XMM1

  (64) 0x5cbd VCVTSS2SD	%XMM16,%XMM16,%XMM0

  (64) 0x5cc3 VFMADD213SD	%XMM2,%XMM1,%XMM0

  (64) 0x5cc8 CMP	%R8,%R14

  (64) 0x5ccb JNE	5b90

0x5cd1 JMP	5a43

0x5cd6 CMPL	$0x10,0x28(%RSP)

0x5cdb JAE	5ce9

0x5cdd MOV	0x68(%RSP),%RSI

0x5ce2 XOR	%EDX,%EDX

0x5ce4 JMP	5d9d

0x5ce9 MOV	0x68(%RSP),%RSI

0x5cee MOV	0x3a8(%RSP),%RDI

0x5cf6 VPXOR	%XMM0,%XMM0,%XMM0

0x5cfa XOR	%ECX,%ECX

0x5cfc VPXOR	%XMM1,%XMM1,%XMM1

0x5d00 VXORPS	%XMM2,%XMM2,%XMM2

0x5d04 VXORPS	%XMM3,%XMM3,%XMM3

  (66) 0x5d08 LEA	(%RAX,%RCX,1),%EDX

  (66) 0x5d0b VCVTPS2PD	(%RSI,%RDX,4),%YMM4

  (66) 0x5d10 VCVTPS2PD	0x10(%RSI,%RDX,4),%YMM5

  (66) 0x5d16 VCVTPS2PD	0x20(%RSI,%RDX,4),%YMM6

  (66) 0x5d1c VCVTPS2PD	0x30(%RSI,%RDX,4),%YMM7

  (66) 0x5d22 LEA	(%R12,%RCX,1),%EDX

  (66) 0x5d26 ADD	$0x10,%RCX

  (66) 0x5d2a VCVTPS2PD	(%R15,%RDX,4),%YMM8

  (66) 0x5d30 VCVTPS2PD	0x10(%R15,%RDX,4),%YMM9

  (66) 0x5d37 VFMADD231PD	%YMM8,%YMM4,%YMM0

  (66) 0x5d3c VFMADD231PD	%YMM9,%YMM5,%YMM1

  (66) 0x5d41 VCVTPS2PD	0x20(%R15,%RDX,4),%YMM8

  (66) 0x5d48 VCVTPS2PD	0x30(%R15,%RDX,4),%YMM5

  (66) 0x5d4f VFMADD231PD	%YMM8,%YMM6,%YMM2

  (66) 0x5d54 VFMADD231PD	%YMM5,%YMM7,%YMM3

  (66) 0x5d59 CMP	%RCX,%RDI

  (66) 0x5d5c JNE	5d08

0x5d5e VADDPD	%YMM0,%YMM1,%YMM0

0x5d62 VADDPD	%YMM2,%YMM3,%YMM1

0x5d66 VADDPD	%YMM0,%YMM1,%YMM0

0x5d6a VEXTRACTF128	$0x1,%YMM0,%XMM1

0x5d70 VADDPD	%XMM1,%XMM0,%XMM0

0x5d74 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x5d79 VADDSD	%XMM1,%XMM0,%XMM0

0x5d7d CMP	%EDI,0x28(%RSP)

0x5d81 JE	5a43

0x5d87 TESTB	$0xc,0x38(%RSP)

0x5d8c MOV	0x68(%RSP),%RSI

0x5d91 MOV	%RDI,%RDX

0x5d94 MOV	%RDI,%RCX

0x5d97 JE	5aaf

0x5d9d MOV	0x3b8(%RSP),%RDI

0x5da5 MOV	0x30(%RSP),%R8

0x5daa VMOVQ	%XMM0,%XMM0

  (67) 0x5dae LEA	(%RAX,%RDX,1),%ECX

  (67) 0x5db1 VCVTPS2PD	(%RSI,%RCX,4),%YMM1

  (67) 0x5db6 LEA	(%R8,%RDX,1),%ECX

  (67) 0x5dba ADD	$0x4,%RDX

  (67) 0x5dbe VCVTPS2PD	(%R15,%RCX,4),%YMM2

  (67) 0x5dc4 VFMADD231PD	%YMM2,%YMM1,%YMM0

  (67) 0x5dc9 CMP	%RDX,%RDI

  (67) 0x5dcc JNE	5dae

0x5dce VEXTRACTF128	$0x1,%YMM0,%XMM1

0x5dd4 MOV	%RDI,%RCX

0x5dd7 VADDPD	%XMM1,%XMM0,%XMM0

0x5ddb VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x5de0 VADDSD	%XMM1,%XMM0,%XMM0

0x5de4 CMP	%EDI,0x28(%RSP)

0x5de8 JE	5a43

0x5dee JMP	5aaf

/home/eoseret/llm-attention/attention_v2.cpp: 27 - 33

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.16
CQA speedup if FP arith vectorized	2.32
CQA speedup if fully vectorized	10.63
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.53
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.63
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	5.44
CQA cycles if fully vectorized	1.19
Front-end cycles	12.63
P0 cycles	7.50
P1 cycles	7.50
P2 cycles	7.50
P3 cycles	7.50
P4 cycles	7.50
P5 cycles	7.50
P6 cycles	8.25
P7 cycles	8.25
P8 cycles	8.25
P9 cycles	8.25
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	2.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	101.00
Nb uops	101.00
Nb loads	28.00
Nb stores	5.00
Nb stack references	17.00
FLOP/cycle	1.50
Nb FLOP add-sub	18.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.58
Bytes prefetched	0.00
Bytes loaded	186.00
Bytes stored	36.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	29.17
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	55.56
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	47.37
Vector-efficiency ratio all	16.83
Vector-efficiency ratio load	10.25
Vector-efficiency ratio store	11.25
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	27.78
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	16.86

Metric	Value
CQA speedup if no scalar integer	3.16
CQA speedup if FP arith vectorized	2.32
CQA speedup if fully vectorized	10.63
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.53
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.63
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	5.44
CQA cycles if fully vectorized	1.19
Front-end cycles	12.63
P0 cycles	7.50
P1 cycles	7.50
P2 cycles	7.50
P3 cycles	7.50
P4 cycles	7.50
P5 cycles	7.50
P6 cycles	8.25
P7 cycles	8.25
P8 cycles	8.25
P9 cycles	8.25
P10 cycles	3.00
P11 cycles	3.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	2.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	101.00
Nb uops	101.00
Nb loads	28.00
Nb stores	5.00
Nb stack references	17.00
FLOP/cycle	1.50
Nb FLOP add-sub	18.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.58
Bytes prefetched	0.00
Bytes loaded	186.00
Bytes stored	36.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	29.17
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	55.56
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	47.37
Vector-efficiency ratio all	16.83
Vector-efficiency ratio load	10.25
Vector-efficiency ratio store	11.25
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	27.78
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	16.86

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-znver5-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:27,30,33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 23 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.63 to 4.00 cycles (3.16x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions).

Details

29% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
55% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
47% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:30
- /home/eoseret/llm-attention/attention_v2.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 3 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 19 FP arithmetical operations:

18: addition or subtraction
1: divide

The binary loop is loading 186 bytes (23 double precision FP elements). The binary loop is storing 36 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	101
nb uops	101
loop length	463
used x86 registers	13
used mmx registers	0
used xmm registers	4
used ymm registers	4
used zmm registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.63 cycles
front end	12.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.50	7.50	7.50	7.50	7.50	7.50	8.25	8.25	8.25	8.25	3.00	3.00	4.00	4.00	0.50	0.50
cycles	7.50	7.50	7.50	7.50	7.50	7.50	8.25	8.25	8.25	8.25	3.00	3.00	4.00	4.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

2.50

Cycles summary

Front-end	12.63
Dispatch	8.25
DIV/SQRT	2.50
Overall L1	12.63

Vectorization ratios

INT

all	9%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	68%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	85%

INT+FP

all	29%
load	0%
store	0%
mul	0%
add-sub	55%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	47%

Vector efficiency ratios

INT

all	12%
load	10%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	25%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	32%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	23%

INT+FP

all	16%
load	10%
store	11%
mul	12%
add-sub	27%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.63 cycles. At this rate:

5% of peak load performance is reached (14.73 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.85 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.63 to 8.25 cycles (1.53x speedup).

ASM code

In the binary file, the address of the loop is: 5a83

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VDIVSS 0x2d4(%RSP),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
MOV 0x30(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x170(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x118(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x40(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
ADD %R12D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVSS %XMM0,(%RDX,%RCX,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
MOV 0x58(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %R13,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 59f7 <main+0x2c27>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
CMPL $0x4,0x28(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R12,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JB 5aad <main+0x2cdd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV %R12D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
ADD 0x98(%RSP),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SETB %CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR 0xe0(%RSP),%CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 5cd6 <main+0x2f06>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x38(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 5b0c <main+0x2d3c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x58(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x68(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV %R9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
IMUL %RCX,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
ADD 0x30(%RSP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 5b14 <main+0x2d44>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV 0x68(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0x28(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x3c0(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
SUB %R14,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $-0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 5a43 <main+0x2c73>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x58(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x7(%R8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x4(%R8),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x3(%R8),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%R8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
IMUL %RDI,%R12	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
IMUL %RDI,%R13	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
IMUL %RDI,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %R8,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x6(%R8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RCX,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x5(%R8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RCX,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x2(%R8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 5a43 <main+0x2c73>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
CMPL $0x10,0x28(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JAE 5ce9 <main+0x2f19>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x68(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 5d9d <main+0x2fcd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV 0x68(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x3a8(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VADDPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM2,%YMM3,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %EDI,0x28(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JE 5a43 <main+0x2c73>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
TESTB $0xc,0x38(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (1.6%)
MOV 0x68(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JE 5aaf <main+0x2cdf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x3b8(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x30(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (25.0%)
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %EDI,0x28(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 5a43 <main+0x2c73>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
JMP 5aaf <main+0x2cdf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-znver5-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:27,30,33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.63 to 4.00 cycles (3.16x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions).

Details

29% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
55% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
47% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:30
- /home/eoseret/llm-attention/attention_v2.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 19 FP arithmetical operations:

18: addition or subtraction
1: divide

The binary loop is loading 186 bytes (23 double precision FP elements). The binary loop is storing 36 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	101
nb uops	101
loop length	463
used x86 registers	13
used mmx registers	0
used xmm registers	4
used ymm registers	4
used zmm registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.63 cycles
front end	12.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.50	7.50	7.50	7.50	7.50	7.50	8.25	8.25	8.25	8.25	3.00	3.00	4.00	4.00	0.50	0.50
cycles	7.50	7.50	7.50	7.50	7.50	7.50	8.25	8.25	8.25	8.25	3.00	3.00	4.00	4.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

2.50

Cycles summary

Front-end	12.63
Dispatch	8.25
DIV/SQRT	2.50
Overall L1	12.63

Vectorization ratios

INT

all	9%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	68%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	85%

INT+FP

all	29%
load	0%
store	0%
mul	0%
add-sub	55%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	47%

Vector efficiency ratios

INT

all	12%
load	10%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	25%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	32%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	23%

INT+FP

all	16%
load	10%
store	11%
mul	12%
add-sub	27%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.63 cycles. At this rate:

5% of peak load performance is reached (14.73 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.85 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 5a83

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
VDIVSS 0x2d4(%RSP),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	10	2.50	scal (6.3%)
MOV 0x30(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x170(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x118(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x40(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
ADD %R12D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVSS %XMM0,(%RDX,%RCX,4)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (6.3%)
MOV 0x58(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %R13,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 59f7 <main+0x2c27>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
CMPL $0x4,0x28(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R12,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JB 5aad <main+0x2cdd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV %R12D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
ADD 0x98(%RSP),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SETB %CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
OR 0xe0(%RSP),%CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 5cd6 <main+0x2f06>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x38(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 5b0c <main+0x2d3c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x58(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x68(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV %R9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
IMUL %RCX,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
ADD 0x30(%RSP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 5b14 <main+0x2d44>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV 0x68(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV 0x28(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x3c0(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
SUB %R14,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $-0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 5a43 <main+0x2c73>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x58(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x7(%R8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x4(%R8),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x3(%R8),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%R8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	scal (12.5%)
IMUL %RDI,%R12	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
IMUL %RDI,%R13	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
IMUL %RDI,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %R8,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x6(%R8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RCX,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x5(%R8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RCX,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA 0x2(%R8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JMP 5a43 <main+0x2c73>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
CMPL $0x10,0x28(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JAE 5ce9 <main+0x2f19>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x68(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 5d9d <main+0x2fcd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A
MOV 0x68(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x3a8(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VADDPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM2,%YMM3,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %EDI,0x28(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JE 5a43 <main+0x2c73>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
TESTB $0xc,0x38(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (1.6%)
MOV 0x68(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
JE 5aaf <main+0x2cdf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
MOV 0x3b8(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x30(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	2	0.25	vect (25.0%)
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.13	N/A
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1-2	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %EDI,0x28(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JE 5a43 <main+0x2c73>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A
JMP 5aaf <main+0x2cdf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code