OV - attention-clang-znver5-256 - Loop 53 - attention-clang-znver5-256

	Loop Id: 53	Module: attention-clang-znver5-256	Source: attention_v2.cpp:30-31	Coverage: 34.43%

0x6c00 LEA	(%RAX,%R8,1),%R9D

0x6c04 LEA	0x6(%RAX,%R8,1),%R10D

0x6c09 VMOVSS	(%R12,%R9,4),%XMM1    [2]

0x6c0f LEA	(%RSI,%RDI,1),%R9D

0x6c13 VMOVSS	(%R14,%R9,4),%XMM2    [3]

0x6c19 LEA	0x1(%RAX,%R8,1),%R9D

0x6c1e VMOVSS	(%R12,%R10,4),%XMM13    [2]

0x6c24 VMOVSS	(%R12,%R9,4),%XMM3    [2]

0x6c2a LEA	(%RDX,%RDI,1),%R9D

0x6c2e VMOVSS	(%R14,%R9,4),%XMM4    [3]

0x6c34 LEA	0x2(%RAX,%R8,1),%R9D

0x6c39 VMOVSS	(%R12,%R9,4),%XMM5    [2]

0x6c3f LEA	(%RCX,%RDI,1),%R9D

0x6c43 VMOVSS	(%R14,%R9,4),%XMM6    [3]

0x6c49 LEA	0x3(%RAX,%R8,1),%R9D

0x6c4e VCVTSS2SD	%XMM1,%XMM1,%XMM1

0x6c52 VCVTSS2SD	%XMM2,%XMM2,%XMM2

0x6c56 VMOVSS	(%R12,%R9,4),%XMM7    [2]

0x6c5c LEA	(%R13,%RDI,1),%R9D

0x6c61 VMOVSS	(%R14,%R9,4),%XMM8    [3]

0x6c67 LEA	0x4(%RAX,%R8,1),%R9D

0x6c6c VFMADD213SD	%XMM0,%XMM1,%XMM2

0x6c71 VCVTSS2SD	%XMM3,%XMM3,%XMM0

0x6c75 VMOVSS	(%R12,%R9,4),%XMM9    [2]

0x6c7b LEA	(%RBX,%RDI,1),%R9D

0x6c7f VMOVSS	(%R14,%R9,4),%XMM10    [3]

0x6c85 LEA	0x5(%RAX,%R8,1),%R9D

0x6c8a VCVTSS2SD	%XMM4,%XMM4,%XMM1

0x6c8e VMOVSS	(%R12,%R9,4),%XMM11    [2]

0x6c94 MOV	0xa0(%RSP),%R9    [1]

0x6c9c VFMADD213SD	%XMM2,%XMM0,%XMM1

0x6ca1 VCVTSS2SD	%XMM5,%XMM5,%XMM0

0x6ca5 LEA	(%R9,%RDI,1),%R9D

0x6ca9 VCVTSS2SD	%XMM6,%XMM6,%XMM2

0x6cad VMOVSS	(%R14,%R9,4),%XMM12    [3]

0x6cb3 MOV	0x120(%RSP),%R9    [1]

0x6cbb VFMADD213SD	%XMM1,%XMM0,%XMM2

0x6cc0 VCVTSS2SD	%XMM7,%XMM7,%XMM0

0x6cc4 ADD	%EDI,%R9D

0x6cc7 VCVTSS2SD	%XMM8,%XMM8,%XMM1

0x6ccc VMOVSS	(%R14,%R9,4),%XMM14    [3]

0x6cd2 LEA	0x7(%RAX,%R8,1),%R9D

0x6cd7 ADD	$0x8,%R8

0x6cdb VMOVSS	(%R12,%R9,4),%XMM15    [2]

0x6ce1 MOV	0x140(%RSP),%R9    [1]

0x6ce9 VFMADD213SD	%XMM2,%XMM0,%XMM1

0x6cee VCVTSS2SD	%XMM9,%XMM9,%XMM0

0x6cf3 VCVTSS2SD	%XMM10,%XMM10,%XMM2

0x6cf8 ADD	%EDI,%R9D

0x6cfb ADD	%R15,%RDI

0x6cfe VMOVSS	(%R14,%R9,4),%XMM16    [3]

0x6d05 VFMADD213SD	%XMM1,%XMM0,%XMM2

0x6d0a VCVTSS2SD	%XMM11,%XMM11,%XMM0

0x6d0f VCVTSS2SD	%XMM12,%XMM12,%XMM1

0x6d14 VFMADD213SD	%XMM2,%XMM0,%XMM1

0x6d19 VCVTSS2SD	%XMM13,%XMM13,%XMM0

0x6d1e VCVTSS2SD	%XMM14,%XMM14,%XMM2

0x6d23 VFMADD213SD	%XMM1,%XMM0,%XMM2

0x6d28 VCVTSS2SD	%XMM15,%XMM15,%XMM1

0x6d2d VCVTSS2SD	%XMM16,%XMM16,%XMM0

0x6d33 VFMADD213SD	%XMM2,%XMM1,%XMM0

0x6d38 CMP	%R8,%R11

0x6d3b JNE	6c00

/home/eoseret/llm-attention/attention_v2.cpp: 30 - 31

--------------------------------------------------------------------------------

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.76
CQA speedup if fully vectorized	14.20
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.71
Bottlenecks
Function	main
Source	attention_v2.cpp:30-31
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.00
CQA cycles if no scalar integer	32.00
CQA cycles if FP arith vectorized	18.22
CQA cycles if fully vectorized	2.25
Front-end cycles	8.63
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	3.50
P3 cycles	3.50
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	6.50
P7 cycles	6.50
P8 cycles	6.50
P9 cycles	6.50
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	8.00
P13 cycles	8.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	32
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	63.00
Nb uops	69.00
Nb loads	19.00
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	0.50
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.75
Bytes prefetched	0.00
Bytes loaded	88.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	1.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.50
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.76
CQA speedup if fully vectorized	14.20
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.71
Bottlenecks
Function	main
Source	attention_v2.cpp:30-31
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.00
CQA cycles if no scalar integer	32.00
CQA cycles if FP arith vectorized	18.22
CQA cycles if fully vectorized	2.25
Front-end cycles	8.63
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	3.50
P3 cycles	3.50
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	6.50
P7 cycles	6.50
P8 cycles	6.50
P9 cycles	6.50
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	8.00
P13 cycles	8.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	32
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	63.00
Nb uops	69.00
Nb loads	19.00
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	0.50
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.75
Bytes prefetched	0.00
Bytes loaded	88.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	1.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.50
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:30-31
Module	attention-clang-znver5-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:30-31.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 32.00 to 2.25 cycles (14.20x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 8 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 7 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSS2SD (FP32 to FP64, scalar): 16 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 88 bytes (11 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	63
nb uops	69
loop length	321
used x86 registers	15
used mmx registers	0
used xmm registers	17
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.63 cycles
front end	8.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.00	3.00	3.50	3.50	3.00	3.00	6.50	6.50	6.50	6.50	4.00	4.00	8.00	8.00	0.00	0.00
cycles	3.00	3.00	3.50	3.50	3.00	3.00	6.50	6.50	6.50	6.50	4.00	4.00	8.00	8.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	32.00

Cycles summary

Front-end	8.63
Dispatch	8.00
Data deps.	32.00
Overall L1	32.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.00 cycles. At this rate:

1% of peak load performance is reached (2.75 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 6c00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
LEA (%RAX,%R8,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x6(%RAX,%R8,1),%R10D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VMOVSS (%R12,%R9,4),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RSI,%RDI,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R9,4),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x1(%RAX,%R8,1),%R9D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VMOVSS (%R12,%R10,4),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS (%R12,%R9,4),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RDX,%RDI,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R9,4),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x2(%RAX,%R8,1),%R9D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VMOVSS (%R12,%R9,4),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RCX,%RDI,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R9,4),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x3(%RAX,%R8,1),%R9D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VCVTSS2SD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R12,%R9,4),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%R13,%RDI,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R9,4),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x4(%RAX,%R8,1),%R9D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VFMADD213SD %XMM0,%XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM3,%XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R12,%R9,4),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RBX,%RDI,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R9,4),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x5(%RAX,%R8,1),%R9D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VCVTSS2SD %XMM4,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R12,%R9,4),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
MOV 0xa0(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VFMADD213SD %XMM2,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM5,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
LEA (%R9,%RDI,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VCVTSS2SD %XMM6,%XMM6,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R14,%R9,4),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
MOV 0x120(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VFMADD213SD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM7,%XMM7,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
ADD %EDI,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VCVTSS2SD %XMM8,%XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R14,%R9,4),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x7(%RAX,%R8,1),%R9D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
ADD $0x8,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R12,%R9,4),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
MOV 0x140(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VFMADD213SD %XMM2,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM9,%XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM10,%XMM10,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
ADD %EDI,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R15,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R9,4),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
VFMADD213SD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM11,%XMM11,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM12,%XMM12,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM2,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM13,%XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM14,%XMM14,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM15,%XMM15,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM16,%XMM16,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM2,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
CMP %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 6c00 <main+0x3e30>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:30-31
Module	attention-clang-znver5-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:30-31.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 8 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 7 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSS2SD (FP32 to FP64, scalar): 16 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 88 bytes (11 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	63
nb uops	69
loop length	321
used x86 registers	15
used mmx registers	0
used xmm registers	17
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.63 cycles
front end	8.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.00	3.00	3.50	3.50	3.00	3.00	6.50	6.50	6.50	6.50	4.00	4.00	8.00	8.00	0.00	0.00
cycles	3.00	3.00	3.50	3.50	3.00	3.00	6.50	6.50	6.50	6.50	4.00	4.00	8.00	8.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	32.00

Cycles summary

Front-end	8.63
Dispatch	8.00
Data deps.	32.00
Overall L1	32.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.00 cycles. At this rate:

1% of peak load performance is reached (2.75 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 6c00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
LEA (%RAX,%R8,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x6(%RAX,%R8,1),%R10D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VMOVSS (%R12,%R9,4),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RSI,%RDI,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R9,4),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x1(%RAX,%R8,1),%R9D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VMOVSS (%R12,%R10,4),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
VMOVSS (%R12,%R9,4),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RDX,%RDI,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R9,4),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x2(%RAX,%R8,1),%R9D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VMOVSS (%R12,%R9,4),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RCX,%RDI,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R9,4),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x3(%RAX,%R8,1),%R9D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VCVTSS2SD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R12,%R9,4),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%R13,%RDI,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R9,4),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x4(%RAX,%R8,1),%R9D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VFMADD213SD %XMM0,%XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM3,%XMM3,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R12,%R9,4),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA (%RBX,%RDI,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R9,4),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x5(%RAX,%R8,1),%R9D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
VCVTSS2SD %XMM4,%XMM4,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R12,%R9,4),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
MOV 0xa0(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VFMADD213SD %XMM2,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM5,%XMM5,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
LEA (%R9,%RDI,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VCVTSS2SD %XMM6,%XMM6,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R14,%R9,4),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
MOV 0x120(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VFMADD213SD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM7,%XMM7,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
ADD %EDI,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VCVTSS2SD %XMM8,%XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VMOVSS (%R14,%R9,4),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
LEA 0x7(%RAX,%R8,1),%R9D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
ADD $0x8,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R12,%R9,4),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
MOV 0x140(%RSP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VFMADD213SD %XMM2,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM9,%XMM9,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM10,%XMM10,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
ADD %EDI,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R15,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS (%R14,%R9,4),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (6.3%)
VFMADD213SD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM11,%XMM11,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM12,%XMM12,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM2,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM13,%XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM14,%XMM14,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
VCVTSS2SD %XMM15,%XMM15,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VCVTSS2SD %XMM16,%XMM16,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (6.3%)
VFMADD213SD %XMM2,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50	scal (12.5%)
CMP %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 6c00 <main+0x3e30>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0.33-0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code